Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.....................
/home/mcc/execution
total 812K
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.9K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 10K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.9K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 117 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 355 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 4.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 9 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 633K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is PhaseVariation-PT-D05CS100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666475600620
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-00
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-01
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-02
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-03
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-04
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-05
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-06
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-07
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-08
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-09
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-10
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-11
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-12
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-13
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-14
FORMULA_NAME PhaseVariation-PT-D05CS100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1527189180591

Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/CTLFireability.pnml.gal, -t, CGAL, -ctl, /home/mcc/execution/CTLFireability.ctl], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.pnml.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl
No direction supplied, using forward translation only.
Parsed 16 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,8.21904e+32,889.49,8199648,2,62074,5,6.56457e+07,6,0,910,4.66377e+07,0


Converting to forward existential form...Done !
original formula: (((((((pool__1_2_>=1)&&(cell___2_2__A_>=1))&&(run_dot>=1))||(((pool__3_1_>=1)&&(cell___4_1__B_>=1))&&(run_dot>=1)))&&((((pool__5_4_>=1)&&(cell___5_3__A_>=1))&&(run_dot>=1))||(((pool__2_4_>=1)&&(cell___2_3__A_>=1))&&(run_dot>=1))))&&(((pool__5_5_>=1)&&(cell___4_5__B_>=1))&&(run_dot>=1))) + EG(AF(((((pool__5_2_>=1)&&(cell___5_1__B_>=1))&&(run_dot>=1))&&(((pool__4_2_>=1)&&(cell___5_2__B_>=1))&&(run_dot>=1))))))
=> equivalent forward existential formula: ([(Init * ((((((pool__1_2_>=1)&&(cell___2_2__A_>=1))&&(run_dot>=1))||(((pool__3_1_>=1)&&(cell___4_1__B_>=1))&&(run_dot>=1)))&&((((pool__5_4_>=1)&&(cell___5_3__A_>=1))&&(run_dot>=1))||(((pool__2_4_>=1)&&(cell___2_3__A_>=1))&&(run_dot>=1))))&&(((pool__5_5_>=1)&&(cell___4_5__B_>=1))&&(run_dot>=1))))] != FALSE + [FwdG(Init,!(EG(!(((((pool__5_2_>=1)&&(cell___5_1__B_>=1))&&(run_dot>=1))&&(((pool__4_2_>=1)&&(cell___5_2__B_>=1))&&(run_dot>=1)))))))] != FALSE)
Reverse transition relation is NOT exact ! Due to transitions division2_mutate_1_3_A_1_2, division2_mutate_1_3_A_1_4, division2_mutate_1_3_A_2_2, division2_mutate_1_3_A_2_4, division2_mutate_1_3_B_1_2, division2_mutate_1_3_B_1_4, division2_mutate_1_3_B_2_2, division2_mutate_1_3_B_2_4, division2_mutate_1_4_A_1_3, division2_mutate_1_4_A_1_5, division2_mutate_1_4_A_2_3, division2_mutate_1_4_A_2_5, division2_mutate_1_4_B_1_3, division2_mutate_1_4_B_1_5, division2_mutate_1_4_B_2_3, division2_mutate_1_4_B_2_5, division2_mutate_2_3_A_1_2, division2_mutate_2_3_A_1_3, division2_mutate_2_3_A_1_4, division2_mutate_2_3_A_2_2, division2_mutate_2_3_A_2_4, division2_mutate_2_3_A_3_2, division2_mutate_2_3_A_3_3, division2_mutate_2_3_A_3_4, division2_mutate_2_3_B_1_2, division2_mutate_2_3_B_1_3, division2_mutate_2_3_B_1_4, division2_mutate_2_3_B_2_2, division2_mutate_2_3_B_2_4, division2_mutate_2_3_B_3_2, division2_mutate_2_3_B_3_3, division2_mutate_2_3_B_3_4, division2_mutate_2_4_A_1_3, division2_mutate_2_4_A_1_4, division2_mutate_2_4_A_1_5, division2_mutate_2_4_A_2_3, division2_mutate_2_4_A_2_5, division2_mutate_2_4_A_3_3, division2_mutate_2_4_A_3_4, division2_mutate_2_4_A_3_5, division2_mutate_2_4_B_1_3, division2_mutate_2_4_B_1_4, division2_mutate_2_4_B_1_5, division2_mutate_2_4_B_2_3, division2_mutate_2_4_B_2_5, division2_mutate_2_4_B_3_3, division2_mutate_2_4_B_3_4, division2_mutate_2_4_B_3_5, division2_mutate_2_5_A_1_4, division2_mutate_2_5_A_1_5, division2_mutate_2_5_A_3_4, division2_mutate_2_5_A_3_5, division2_mutate_2_5_B_1_4, division2_mutate_2_5_B_1_5, division2_mutate_2_5_B_3_4, division2_mutate_2_5_B_3_5, division2_mutate_3_1_A_2_1, division2_mutate_3_1_A_2_2, division2_mutate_3_1_A_4_1, division2_mutate_3_1_A_4_2, division2_mutate_3_1_B_2_1, division2_mutate_3_1_B_2_2, division2_mutate_3_1_B_4_1, division2_mutate_3_1_B_4_2, division2_mutate_3_2_A_2_1, division2_mutate_3_2_A_2_2, division2_mutate_3_2_A_2_3, division2_mutate_3_2_A_3_1, division2_mutate_3_2_A_3_3, division2_mutate_3_2_A_4_1, division2_mutate_3_2_A_4_2, division2_mutate_3_2_A_4_3, division2_mutate_3_2_B_2_1, division2_mutate_3_2_B_2_2, division2_mutate_3_2_B_2_3, division2_mutate_3_2_B_3_1, division2_mutate_3_2_B_3_3, division2_mutate_3_2_B_4_1, division2_mutate_3_2_B_4_2, division2_mutate_3_2_B_4_3, division2_mutate_3_3_A_2_2, division2_mutate_3_3_A_2_3, division2_mutate_3_3_A_2_4, division2_mutate_3_3_A_3_2, division2_mutate_3_3_A_3_4, division2_mutate_3_3_A_4_2, division2_mutate_3_3_A_4_3, division2_mutate_3_3_A_4_4, division2_mutate_3_3_B_2_2, division2_mutate_3_3_B_2_3, division2_mutate_3_3_B_2_4, division2_mutate_3_3_B_3_2, division2_mutate_3_3_B_3_4, division2_mutate_3_3_B_4_2, division2_mutate_3_3_B_4_3, division2_mutate_3_3_B_4_4, division2_mutate_3_4_A_2_3, division2_mutate_3_4_A_2_4, division2_mutate_3_4_A_2_5, division2_mutate_3_4_A_3_3, division2_mutate_3_4_A_3_5, division2_mutate_3_4_A_4_3, division2_mutate_3_4_A_4_4, division2_mutate_3_4_A_4_5, division2_mutate_3_4_B_2_3, division2_mutate_3_4_B_2_4, division2_mutate_3_4_B_2_5, division2_mutate_3_4_B_3_3, division2_mutate_3_4_B_3_5, division2_mutate_3_4_B_4_3, division2_mutate_3_4_B_4_4, division2_mutate_3_4_B_4_5, division2_mutate_3_5_A_2_4, division2_mutate_3_5_A_2_5, division2_mutate_3_5_A_4_4, division2_mutate_3_5_A_4_5, division2_mutate_3_5_B_2_4, division2_mutate_3_5_B_2_5, division2_mutate_3_5_B_4_4, division2_mutate_3_5_B_4_5, division2_mutate_4_1_A_3_1, division2_mutate_4_1_A_3_2, division2_mutate_4_1_A_5_1, division2_mutate_4_1_A_5_2, division2_mutate_4_1_B_3_1, division2_mutate_4_1_B_3_2, division2_mutate_4_1_B_5_1, division2_mutate_4_1_B_5_2, division2_mutate_4_2_A_3_1, division2_mutate_4_2_A_3_2, division2_mutate_4_2_A_3_3, division2_mutate_4_2_A_4_1, division2_mutate_4_2_A_4_3, division2_mutate_4_2_A_5_1, division2_mutate_4_2_A_5_2, division2_mutate_4_2_A_5_3, division2_mutate_4_2_B_3_1, division2_mutate_4_2_B_3_2, division2_mutate_4_2_B_3_3, division2_mutate_4_2_B_4_1, division2_mutate_4_2_B_4_3, division2_mutate_4_2_B_5_1, division2_mutate_4_2_B_5_2, division2_mutate_4_2_B_5_3, division2_mutate_4_3_A_3_2, division2_mutate_4_3_A_3_3, division2_mutate_4_3_A_3_4, division2_mutate_4_3_A_4_2, division2_mutate_4_3_A_4_4, division2_mutate_4_3_A_5_2, division2_mutate_4_3_A_5_3, division2_mutate_4_3_A_5_4, division2_mutate_4_3_B_3_2, division2_mutate_4_3_B_3_3, division2_mutate_4_3_B_3_4, division2_mutate_4_3_B_4_2, division2_mutate_4_3_B_4_4, division2_mutate_4_3_B_5_2, division2_mutate_4_3_B_5_3, division2_mutate_4_3_B_5_4, division2_mutate_4_4_A_3_3, division2_mutate_4_4_A_3_4, division2_mutate_4_4_A_3_5, division2_mutate_4_4_A_4_3, division2_mutate_4_4_A_4_5, division2_mutate_4_4_A_5_3, division2_mutate_4_4_A_5_4, division2_mutate_4_4_A_5_5, division2_mutate_4_4_B_3_3, division2_mutate_4_4_B_3_4, division2_mutate_4_4_B_3_5, division2_mutate_4_4_B_4_3, division2_mutate_4_4_B_4_5, division2_mutate_4_4_B_5_3, division2_mutate_4_4_B_5_4, division2_mutate_4_4_B_5_5, division2_mutate_4_5_A_3_4, division2_mutate_4_5_A_3_5, division2_mutate_4_5_A_5_4, division2_mutate_4_5_A_5_5, division2_mutate_4_5_B_3_4, division2_mutate_4_5_B_3_5, division2_mutate_4_5_B_5_4, division2_mutate_4_5_B_5_5, division2_mutate_5_2_A_4_1, division2_mutate_5_2_A_4_3, division2_mutate_5_2_A_5_1, division2_mutate_5_2_A_5_3, division2_mutate_5_2_B_4_1, division2_mutate_5_2_B_4_3, division2_mutate_5_2_B_5_1, division2_mutate_5_2_B_5_3, division2_mutate_5_3_A_4_2, division2_mutate_5_3_A_4_4, division2_mutate_5_3_A_5_2, division2_mutate_5_3_A_5_4, division2_mutate_5_3_B_4_2, division2_mutate_5_3_B_4_4, division2_mutate_5_3_B_5_2, division2_mutate_5_3_B_5_4, division2_mutate_5_4_A_4_3, division2_mutate_5_4_A_4_5, division2_mutate_5_4_A_5_3, division2_mutate_5_4_A_5_5, division2_mutate_5_4_B_4_3, division2_mutate_5_4_B_4_5, division2_mutate_5_4_B_5_3, division2_mutate_5_4_B_5_5, division2_replicate_1_3_A_1_2, division2_replicate_1_3_A_1_4, division2_replicate_1_3_A_2_2, division2_replicate_1_3_A_2_4, division2_replicate_1_3_B_1_2, division2_replicate_1_3_B_1_4, division2_replicate_1_3_B_2_2, division2_replicate_1_3_B_2_4, division2_replicate_1_4_A_1_3, division2_replicate_1_4_A_1_5, division2_replicate_1_4_A_2_3, division2_replicate_1_4_A_2_5, division2_replicate_1_4_B_1_3, division2_replicate_1_4_B_1_5, division2_replicate_1_4_B_2_3, division2_replicate_1_4_B_2_5, division2_replicate_2_3_A_1_2, division2_replicate_2_3_A_1_3, division2_replicate_2_3_A_1_4, division2_replicate_2_3_A_2_2, division2_replicate_2_3_A_2_4, division2_replicate_2_3_A_3_2, division2_replicate_2_3_A_3_3, division2_replicate_2_3_A_3_4, division2_replicate_2_3_B_1_2, division2_replicate_2_3_B_1_3, division2_replicate_2_3_B_1_4, division2_replicate_2_3_B_2_2, division2_replicate_2_3_B_2_4, division2_replicate_2_3_B_3_2, division2_replicate_2_3_B_3_3, division2_replicate_2_3_B_3_4, division2_replicate_2_4_A_1_3, division2_replicate_2_4_A_1_4, division2_replicate_2_4_A_1_5, division2_replicate_2_4_A_2_3, division2_replicate_2_4_A_2_5, division2_replicate_2_4_A_3_3, division2_replicate_2_4_A_3_4, division2_replicate_2_4_A_3_5, division2_replicate_2_4_B_1_3, division2_replicate_2_4_B_1_4, division2_replicate_2_4_B_1_5, division2_replicate_2_4_B_2_3, division2_replicate_2_4_B_2_5, division2_replicate_2_4_B_3_3, division2_replicate_2_4_B_3_4, division2_replicate_2_4_B_3_5, division2_replicate_2_5_A_1_4, division2_replicate_2_5_A_1_5, division2_replicate_2_5_A_3_4, division2_replicate_2_5_A_3_5, division2_replicate_2_5_B_1_4, division2_replicate_2_5_B_1_5, division2_replicate_2_5_B_3_4, division2_replicate_2_5_B_3_5, division2_replicate_3_1_A_2_1, division2_replicate_3_1_A_2_2, division2_replicate_3_1_A_4_1, division2_replicate_3_1_A_4_2, division2_replicate_3_1_B_2_1, division2_replicate_3_1_B_2_2, division2_replicate_3_1_B_4_1, division2_replicate_3_1_B_4_2, division2_replicate_3_2_A_2_1, division2_replicate_3_2_A_2_2, division2_replicate_3_2_A_2_3, division2_replicate_3_2_A_3_1, division2_replicate_3_2_A_3_3, division2_replicate_3_2_A_4_1, division2_replicate_3_2_A_4_2, division2_replicate_3_2_A_4_3, division2_replicate_3_2_B_2_1, division2_replicate_3_2_B_2_2, division2_replicate_3_2_B_2_3, division2_replicate_3_2_B_3_1, division2_replicate_3_2_B_3_3, division2_replicate_3_2_B_4_1, division2_replicate_3_2_B_4_2, division2_replicate_3_2_B_4_3, division2_replicate_3_3_A_2_2, division2_replicate_3_3_A_2_3, division2_replicate_3_3_A_2_4, division2_replicate_3_3_A_3_2, division2_replicate_3_3_A_3_4, division2_replicate_3_3_A_4_2, division2_replicate_3_3_A_4_3, division2_replicate_3_3_A_4_4, division2_replicate_3_3_B_2_2, division2_replicate_3_3_B_2_3, division2_replicate_3_3_B_2_4, division2_replicate_3_3_B_3_2, division2_replicate_3_3_B_3_4, division2_replicate_3_3_B_4_2, division2_replicate_3_3_B_4_3, division2_replicate_3_3_B_4_4, division2_replicate_3_4_A_2_3, division2_replicate_3_4_A_2_4, division2_replicate_3_4_A_2_5, division2_replicate_3_4_A_3_3, division2_replicate_3_4_A_3_5, division2_replicate_3_4_A_4_3, division2_replicate_3_4_A_4_4, division2_replicate_3_4_A_4_5, division2_replicate_3_4_B_2_3, division2_replicate_3_4_B_2_4, division2_replicate_3_4_B_2_5, division2_replicate_3_4_B_3_3, division2_replicate_3_4_B_3_5, division2_replicate_3_4_B_4_3, division2_replicate_3_4_B_4_4, division2_replicate_3_4_B_4_5, division2_replicate_3_5_A_2_4, division2_replicate_3_5_A_2_5, division2_replicate_3_5_A_4_4, division2_replicate_3_5_A_4_5, division2_replicate_3_5_B_2_4, division2_replicate_3_5_B_2_5, division2_replicate_3_5_B_4_4, division2_replicate_3_5_B_4_5, division2_replicate_4_1_A_3_1, division2_replicate_4_1_A_3_2, division2_replicate_4_1_A_5_1, division2_replicate_4_1_A_5_2, division2_replicate_4_1_B_3_1, division2_replicate_4_1_B_3_2, division2_replicate_4_1_B_5_1, division2_replicate_4_1_B_5_2, division2_replicate_4_2_A_3_1, division2_replicate_4_2_A_3_2, division2_replicate_4_2_A_3_3, division2_replicate_4_2_A_4_1, division2_replicate_4_2_A_4_3, division2_replicate_4_2_A_5_1, division2_replicate_4_2_A_5_2, division2_replicate_4_2_A_5_3, division2_replicate_4_2_B_3_1, division2_replicate_4_2_B_3_2, division2_replicate_4_2_B_3_3, division2_replicate_4_2_B_4_1, division2_replicate_4_2_B_4_3, division2_replicate_4_2_B_5_1, division2_replicate_4_2_B_5_2, division2_replicate_4_2_B_5_3, division2_replicate_4_3_A_3_2, division2_replicate_4_3_A_3_3, division2_replicate_4_3_A_3_4, division2_replicate_4_3_A_4_2, division2_replicate_4_3_A_4_4, division2_replicate_4_3_A_5_2, division2_replicate_4_3_A_5_3, division2_replicate_4_3_A_5_4, division2_replicate_4_3_B_3_2, division2_replicate_4_3_B_3_3, division2_replicate_4_3_B_3_4, division2_replicate_4_3_B_4_2, division2_replicate_4_3_B_4_4, division2_replicate_4_3_B_5_2, division2_replicate_4_3_B_5_3, division2_replicate_4_3_B_5_4, division2_replicate_4_4_A_3_3, division2_replicate_4_4_A_3_4, division2_replicate_4_4_A_3_5, division2_replicate_4_4_A_4_3, division2_replicate_4_4_A_4_5, division2_replicate_4_4_A_5_3, division2_replicate_4_4_A_5_4, division2_replicate_4_4_A_5_5, division2_replicate_4_4_B_3_3, division2_replicate_4_4_B_3_4, division2_replicate_4_4_B_3_5, division2_replicate_4_4_B_4_3, division2_replicate_4_4_B_4_5, division2_replicate_4_4_B_5_3, division2_replicate_4_4_B_5_4, division2_replicate_4_4_B_5_5, division2_replicate_4_5_A_3_4, division2_replicate_4_5_A_3_5, division2_replicate_4_5_A_5_4, division2_replicate_4_5_A_5_5, division2_replicate_4_5_B_3_4, division2_replicate_4_5_B_3_5, division2_replicate_4_5_B_5_4, division2_replicate_4_5_B_5_5, division2_replicate_5_2_A_4_1, division2_replicate_5_2_A_4_3, division2_replicate_5_2_A_5_1, division2_replicate_5_2_A_5_3, division2_replicate_5_2_B_4_1, division2_replicate_5_2_B_4_3, division2_replicate_5_2_B_5_1, division2_replicate_5_2_B_5_3, division2_replicate_5_3_A_4_2, division2_replicate_5_3_A_4_4, division2_replicate_5_3_A_5_2, division2_replicate_5_3_A_5_4, division2_replicate_5_3_B_4_2, division2_replicate_5_3_B_4_4, division2_replicate_5_3_B_5_2, division2_replicate_5_3_B_5_4, division2_replicate_5_4_A_4_3, division2_replicate_5_4_A_4_5, division2_replicate_5_4_A_5_3, division2_replicate_5_4_A_5_5, division2_replicate_5_4_B_4_3, division2_replicate_5_4_B_4_5, division2_replicate_5_4_B_5_3, division2_replicate_5_4_B_5_5, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/261/416/677
sparsehash FATAL ERROR: failed to allocate 36 groups

BK_STOP 1527191222218

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination CTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 7:13:02 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 7:13:02 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 7:13:02 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 135 ms
May 24, 2018 7:13:02 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 77 places.
May 24, 2018 7:13:03 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 677 transitions.
May 24, 2018 7:13:03 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 47 ms
May 24, 2018 7:13:03 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 229 ms
May 24, 2018 7:13:03 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/CTLFireability.pnml.gal : 5 ms
May 24, 2018 7:13:03 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSCTLTools
INFO: Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 2 ms
ITS-tools command line returned an error code 1

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D05CS100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D05CS100.tgz
mv PhaseVariation-PT-D05CS100 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is PhaseVariation-PT-D05CS100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666475600620"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;