Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..........................
/home/mcc/execution
total 212K
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.2K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.7K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 115 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 353 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 54K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is PermAdmissibility-COL-50, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666475400467
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-00
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-01
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-02
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-03
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-04
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-05
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-06
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-07
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-08
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-09
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-10
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-11
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-12
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-13
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-14
FORMULA_NAME PermAdmissibility-COL-50-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527180790489

16:53:14.356 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
16:53:14.358 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-00 with value :(c13_0>=2)
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-01 with value :(!(((((((((out6_0+out6_1)+out6_2)+out6_3)+out6_4)+out6_5)+out6_6)+out6_7)>=1)&&(c9_0>=1)))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-02 with value :((!(c5_0<=(((((((in2_0+in2_1)+in2_2)+in2_3)+in2_4)+in2_5)+in2_6)+in2_7)))&&(((c20_0>=3)||(c18_0<=(((((((in4_0+in4_1)+in4_2)+in4_3)+in4_4)+in4_5)+in4_6)+in4_7)))||(!((((((((in2_0+in2_1)+in2_2)+in2_3)+in2_4)+in2_5)+in2_6)+in2_7)>=2))))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-03 with value :(!((((((((out2_0+out2_1)+out2_2)+out2_3)+out2_4)+out2_5)+out2_6)+out2_7)<=c18_0))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-04 with value :((((((((((in2_0+in2_1)+in2_2)+in2_3)+in2_4)+in2_5)+in2_6)+in2_7)>=1)||(c16_0>=1))||(((((((((out2_0+out2_1)+out2_2)+out2_3)+out2_4)+out2_5)+out2_6)+out2_7)>=3)||((((((((aux7_0+aux7_1)+aux7_2)+aux7_3)+aux7_4)+aux7_5)+aux7_6)+aux7_7)>=2)))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-05 with value :(c15_0>=1)
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-06 with value :(((((((((in3_0+in3_1)+in3_2)+in3_3)+in3_4)+in3_5)+in3_6)+in3_7)<=(((((((out4_0+out4_1)+out4_2)+out4_3)+out4_4)+out4_5)+out4_6)+out4_7))||((((((((((aux5_0+aux5_1)+aux5_2)+aux5_3)+aux5_4)+aux5_5)+aux5_6)+aux5_7)<=(((((((out7_0+out7_1)+out7_2)+out7_3)+out7_4)+out7_5)+out7_6)+out7_7))||(c20_0<=(((((((aux14_0+aux14_1)+aux14_2)+aux14_3)+aux14_4)+aux14_5)+aux14_6)+aux14_7)))&&(!(c19_0>=1))))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-07 with value :(!((!((((((((aux12_0+aux12_1)+aux12_2)+aux12_3)+aux12_4)+aux12_5)+aux12_6)+aux12_7)<=c16_0))||(!(c5_0<=(((((((aux12_0+aux12_1)+aux12_2)+aux12_3)+aux12_4)+aux12_5)+aux12_6)+aux12_7)))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-08 with value :(!((((((((((out7_0+out7_1)+out7_2)+out7_3)+out7_4)+out7_5)+out7_6)+out7_7)>=3)&&((((((((aux9_0+aux9_1)+aux9_2)+aux9_3)+aux9_4)+aux9_5)+aux9_6)+aux9_7)<=c16_0))&&((c7_0<=(((((((in1_0+in1_1)+in1_2)+in1_3)+in1_4)+in1_5)+in1_6)+in1_7))&&(c5_0<=(((((((out1_0+out1_1)+out1_2)+out1_3)+out1_4)+out1_5)+out1_6)+out1_7)))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-09 with value :((((((((aux11_0+aux11_1)+aux11_2)+aux11_3)+aux11_4)+aux11_5)+aux11_6)+aux11_7)<=c15_0)
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-10 with value :(!(c18_0<=c8_0))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-11 with value :(((((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)>=2)&&(c6_0<=(((((((aux13_0+aux13_1)+aux13_2)+aux13_3)+aux13_4)+aux13_5)+aux13_6)+aux13_7)))&&(!(c8_0>=3)))||(c17_0>=2))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-12 with value :(((!(c16_0<=c11_0))&&(((((((((in1_0+in1_1)+in1_2)+in1_3)+in1_4)+in1_5)+in1_6)+in1_7)>=2)&&(c6_0<=(((((((in1_0+in1_1)+in1_2)+in1_3)+in1_4)+in1_5)+in1_6)+in1_7))))||(((((((((aux10_0+aux10_1)+aux10_2)+aux10_3)+aux10_4)+aux10_5)+aux10_6)+aux10_7)>=2)&&(((((((((out6_0+out6_1)+out6_2)+out6_3)+out6_4)+out6_5)+out6_6)+out6_7)<=(((((((out5_0+out5_1)+out5_2)+out5_3)+out5_4)+out5_5)+out5_6)+out5_7))||(c7_0<=(((((((aux13_0+aux13_1)+aux13_2)+aux13_3)+aux13_4)+aux13_5)+aux13_6)+aux13_7)))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-13 with value :(((c6_0<=c9_0)&&((((((((aux12_0+aux12_1)+aux12_2)+aux12_3)+aux12_4)+aux12_5)+aux12_6)+aux12_7)<=(((((((aux11_0+aux11_1)+aux11_2)+aux11_3)+aux11_4)+aux11_5)+aux11_6)+aux11_7)))||(!((c11_0>=1)||((((((((out5_0+out5_1)+out5_2)+out5_3)+out5_4)+out5_5)+out5_6)+out5_7)>=3))))
Read [invariant] property : PermAdmissibility-COL-50-ReachabilityCardinality-14 with value :(!((!(c11_0<=(((((((out3_0+out3_1)+out3_2)+out3_3)+out3_4)+out3_5)+out3_6)+out3_7)))&&((c110_0<=(((((((in1_0+in1_1)+in1_2)+in1_3)+in1_4)+in1_5)+in1_6)+in1_7))||((((((((aux15_0+aux15_1)+aux15_2)+aux15_3)+aux15_4)+aux15_5)+aux15_6)+aux15_7)>=1))))
Read [reachable] property : PermAdmissibility-COL-50-ReachabilityCardinality-15 with value :((!((c20_0<=c9_0)||((((((((in2_0+in2_1)+in2_2)+in2_3)+in2_4)+in2_5)+in2_6)+in2_7)<=c18_0)))||(((c20_0>=3)&&(c5_0>=2))||(!(c15_0<=c110_0))))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1024 rows 208 cols
invariant :2'c15_0 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :4'c13_0 + -2'aux9_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_0 + -2'aux10_2 + -2'aux10_4 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_0 + -2'aux12_2 + -2'aux12_4 + 2'in1_1 + 2'in1_3 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -2'in2_0 + -2'in2_2 + -2'in2_4 + 2'in3_1 + 2'in3_3 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_2 + -2'in4_4 + 2'aux8_1 + 2'aux8_3 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + -2'aux7_0 + -2'aux7_2 + -2'aux7_4 + 2'aux6_1 + 2'aux6_3 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + 2'aux5_1 + 2'aux5_3 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -4'c9_0 + -2'c110_0 + -2'aux16_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_0 + -2'aux15_2 + -2'aux15_4 + -1'aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + aux13_0 + 3'aux13_1 + aux13_2 + 3'aux13_3 + aux13_4 + 3'aux13_5 + 3'aux13_6 + 3'aux13_7 + -2'out1_0 + -2'out1_2 + -2'out1_4 + out2_0 + 3'out2_1 + out2_2 + 3'out2_3 + out2_4 + 3'out2_5 + 3'out2_6 + 3'out2_7 + -2'out3_0 + -2'out3_2 + -2'out3_4 + out4_0 + 3'out4_1 + out4_2 + 3'out4_3 + out4_4 + 3'out4_5 + 3'out4_6 + 3'out4_7 + -2'out5_0 + -2'out5_2 + -2'out5_4 + -1'out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_0 + -2'out7_2 + -2'out7_4 + -1'out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :c18_0 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 0
invariant :in1_0 + in1_1 + in1_2 + in1_3 + in1_4 + in1_5 + in1_6 + in1_7 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c20_0 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'c16_0 + -1'aux15_0 + -1'aux15_1 + -1'aux15_2 + -1'aux15_3 + -1'aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :-2'c5_0 + c8_0 + in4_0 + in4_1 + in4_2 + in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + -1'aux5_0 + -1'aux5_1 + -1'aux5_2 + -1'aux5_3 + -1'aux5_4 + -1'aux5_5 + -1'aux5_6 + -1'aux5_7 + 2'c9_0 + c110_0 = 0
invariant :-4'c13_0 + 2'aux12_0 + 2'aux12_1 + 2'aux12_2 + 2'aux12_3 + 2'aux12_4 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -2'aux13_0 + -2'aux13_1 + -2'aux13_2 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + -2'aux13_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :aux16_0 + aux16_1 + aux16_2 + aux16_3 + aux16_4 + aux16_5 + aux16_6 + aux16_7 + -2'c17_0 + -2'out2_0 + -2'out2_1 + -2'out2_2 + -2'out2_3 + -2'out2_4 + -2'out2_5 + -2'out2_6 + -2'out2_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_2 + 2'aux10_4 + -2'aux11_1 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + 2'aux12_0 + 2'aux12_2 + 2'aux12_4 + -2'in1_1 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 4'c5_0 + 2'in2_0 + 2'in2_2 + 2'in2_4 + -2'in3_1 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + 2'in4_0 + 2'in4_2 + 2'in4_4 + 2'aux8_0 + 2'aux8_2 + 2'aux8_4 + 2'aux7_0 + 2'aux7_2 + 2'aux7_4 + -2'aux6_1 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 2'aux5_0 + 2'aux5_2 + 2'aux5_4 + 2'c12_0 + 2'aux16_0 + 2'aux16_2 + 2'aux16_4 + 2'aux15_0 + 2'aux15_2 + 2'aux15_4 + aux14_0 + -1'aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + -1'aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'out1_0 + 2'out1_2 + 2'out1_4 + out2_0 + -1'out2_1 + out2_2 + -1'out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + 2'out3_0 + 2'out3_2 + 2'out3_4 + out4_0 + -1'out4_1 + out4_2 + -1'out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + 2'out5_0 + 2'out5_2 + 2'out5_4 + out6_0 + -1'out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + 2'out7_0 + 2'out7_2 + 2'out7_4 + out8_0 + -1'out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 100
invariant :2'c5_0 + c6_0 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c19_0 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 = 0
invariant :2'c13_0 + -2'c5_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + aux6_0 + aux6_1 + aux6_2 + aux6_3 + aux6_4 + aux6_5 + aux6_6 + aux6_7 + c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_3 + 2'aux9_4 + 2'aux9_7 + -2'aux10_5 + -2'aux10_6 + -2'aux11_5 + -2'aux11_6 + -2'aux12_5 + -2'aux12_6 + -2'in1_5 + -2'in1_6 + 4'c5_0 + -2'in2_5 + -2'in2_6 + -2'in3_5 + -2'in3_6 + -2'in4_5 + -2'in4_6 + -2'aux8_5 + -2'aux8_6 + -2'aux7_5 + -2'aux7_6 + -2'aux6_5 + -2'aux6_6 + 2'aux5_0 + 2'aux5_1 + 2'aux5_2 + 2'aux5_3 + 2'aux5_4 + 2'aux5_7 + -2'c110_0 + -2'aux16_5 + -2'aux16_6 + -2'aux15_5 + -2'aux15_6 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + aux14_7 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + aux13_7 + -2'out1_5 + -2'out1_6 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + out2_7 + -2'out3_5 + -2'out3_6 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + out4_7 + -2'out5_5 + -2'out5_6 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + out6_7 + -2'out7_5 + -2'out7_6 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + out8_7 = 0
invariant :aux9_5 + aux10_5 + aux11_5 + aux12_5 + in1_5 + in2_5 + in3_5 + in4_5 + aux8_5 + aux7_5 + aux6_5 + aux5_5 + aux16_5 + aux15_5 + aux14_5 + aux13_5 + out1_5 + out2_5 + out3_5 + out4_5 + out5_5 + out6_5 + out7_5 + out8_5 = 50
invariant :aux9_6 + aux10_6 + aux11_6 + aux12_6 + in1_6 + in2_6 + in3_6 + in4_6 + aux8_6 + aux7_6 + aux6_6 + aux5_6 + aux16_6 + aux15_6 + aux14_6 + aux13_6 + out1_6 + out2_6 + out3_6 + out4_6 + out5_6 + out6_6 + out7_6 + out8_6 = 50
invariant :in2_0 + in2_1 + in2_2 + in2_3 + in2_4 + in2_5 + in2_6 + in2_7 + -1'in4_0 + -1'in4_1 + -1'in4_2 + -1'in4_3 + -1'in4_4 + -1'in4_5 + -1'in4_6 + -1'in4_7 = 0
invariant :2'c13_0 + 2'c5_0 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + c110_0 + 2'c11_0 + 2'c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'c14_0 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_1 + 2'aux10_2 + 2'aux10_4 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + -2'aux12_3 + -2'aux12_5 + -2'aux12_6 + -2'aux12_7 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 8'c5_0 + 2'in2_0 + 2'in2_1 + 2'in2_2 + 2'in2_4 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -4'in4_3 + -2'in4_4 + -4'in4_5 + -4'in4_6 + -4'in4_7 + -2'aux8_3 + -2'aux8_5 + -2'aux8_6 + -2'aux8_7 + -2'aux7_3 + -2'aux7_5 + -2'aux7_6 + -2'aux7_7 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 4'aux5_0 + 4'aux5_1 + 4'aux5_2 + 2'aux5_3 + 4'aux5_4 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -2'aux16_3 + -2'aux16_5 + -2'aux16_6 + -2'aux16_7 + aux15_0 + aux15_1 + aux15_2 + -1'aux15_3 + aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + aux14_0 + aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'c17_0 + 2'out1_0 + 2'out1_1 + 2'out1_2 + 2'out1_4 + 2'out2_0 + 2'out2_1 + 2'out2_2 + 2'out2_4 + -2'out3_3 + -2'out3_5 + -2'out3_6 + -2'out3_7 + 2'out4_0 + 2'out4_1 + 2'out4_2 + 2'out4_4 + -2'out5_3 + -2'out5_5 + -2'out5_6 + -2'out5_7 + out6_0 + out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -2'out7_3 + -2'out7_5 + -2'out7_6 + -2'out7_7 + out8_0 + out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :aux9_3 + aux10_3 + aux11_3 + aux12_3 + in1_3 + -1'in2_0 + -1'in2_1 + -1'in2_2 + -1'in2_4 + -1'in2_5 + -1'in2_6 + -1'in2_7 + in3_3 + in4_0 + in4_1 + in4_2 + 2'in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + aux8_3 + aux7_3 + aux6_3 + aux5_3 + aux16_3 + aux15_3 + aux14_3 + aux13_3 + -1'out1_0 + -1'out1_1 + -1'out1_2 + -1'out1_4 + -1'out1_5 + -1'out1_6 + -1'out1_7 + out2_0 + out2_1 + out2_2 + 2'out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out3_3 + out4_3 + out5_3 + out6_3 + out7_3 + out8_3 = 50
invariant :-4'c13_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_2 + -2'aux10_4 + 2'aux11_0 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_2 + -2'aux12_4 + -2'in1_2 + -2'in1_4 + -2'in2_2 + -2'in2_4 + -2'in3_2 + -2'in3_4 + -2'in4_2 + -2'in4_4 + -2'aux8_2 + -2'aux8_4 + -2'aux7_2 + -2'aux7_4 + -2'aux6_2 + -2'aux6_4 + -2'aux5_2 + -2'aux5_4 + -4'c12_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_2 + -2'aux15_4 + aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -3'aux13_2 + -1'aux13_3 + -3'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -2'out1_2 + -2'out1_4 + -1'out2_0 + -1'out2_1 + -3'out2_2 + -1'out2_3 + -3'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -2'out3_2 + -2'out3_4 + -1'out4_0 + -1'out4_1 + -3'out4_2 + -1'out4_3 + -3'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + -2'out5_2 + -2'out5_4 + out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_2 + -2'out7_4 + out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = -200
invariant :aux9_4 + aux10_4 + aux11_4 + aux12_4 + in1_4 + in2_4 + in3_4 + in4_4 + aux8_4 + aux7_4 + aux6_4 + aux5_4 + aux16_4 + aux15_4 + aux14_4 + aux13_4 + out1_4 + out2_4 + out3_4 + out4_4 + out5_4 + out6_4 + out7_4 + out8_4 = 50
invariant :aux9_2 + aux10_2 + aux11_2 + aux12_2 + in1_2 + in2_2 + in3_2 + in4_2 + aux8_2 + aux7_2 + aux6_2 + aux5_2 + aux16_2 + aux15_2 + aux14_2 + aux13_2 + out1_2 + out2_2 + out3_2 + out4_2 + out5_2 + out6_2 + out7_2 + out8_2 = 50
invariant :2'c7_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -2'in4_3 + -2'in4_4 + -2'in4_5 + -2'in4_6 + -2'in4_7 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + -2'c9_0 + -1'c110_0 = 0
invariant :-2'aux9_0 + -2'aux9_1 + -2'aux9_2 + -2'aux9_3 + -2'aux9_4 + 2'aux10_5 + 2'aux10_6 + 2'aux10_7 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -4'c5_0 + 2'in2_5 + 2'in2_6 + 2'in2_7 + 2'in3_5 + 2'in3_6 + 2'in3_7 + 2'in4_5 + 2'in4_6 + 2'in4_7 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + 2'aux7_5 + 2'aux7_6 + 2'aux7_7 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + 2'c110_0 + 2'aux16_5 + 2'aux16_6 + 2'aux16_7 + 2'aux15_5 + 2'aux15_6 + 2'aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + aux13_5 + aux13_6 + aux13_7 + 2'out1_5 + 2'out1_6 + 2'out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + out2_5 + out2_6 + out2_7 + 2'out3_5 + 2'out3_6 + 2'out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + out4_5 + out4_6 + out4_7 + 2'out5_5 + 2'out5_6 + 2'out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + 2'out7_5 + 2'out7_6 + 2'out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :out1_0 + out1_1 + out1_2 + out1_3 + out1_4 + out1_5 + out1_6 + out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 = 0
invariant :out3_0 + out3_1 + out3_2 + out3_3 + out3_4 + out3_5 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :out5_0 + out5_1 + out5_2 + out5_3 + out5_4 + out5_5 + out5_6 + out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 = 0
invariant :out7_0 + out7_1 + out7_2 + out7_3 + out7_4 + out7_5 + out7_6 + out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :-4'c5_0 + 2'in4_0 + 2'in4_1 + 2'in4_2 + 2'in4_3 + 2'in4_4 + 2'in4_5 + 2'in4_6 + 2'in4_7 + aux7_0 + aux7_1 + aux7_2 + aux7_3 + aux7_4 + aux7_5 + aux7_6 + aux7_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + -2'aux5_5 + -2'aux5_6 + -2'aux5_7 + 2'c9_0 + c110_0 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 1024 rows 208 cols
invariant :2'c15_0 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :4'c13_0 + -2'aux9_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_0 + -2'aux10_2 + -2'aux10_4 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_0 + -2'aux12_2 + -2'aux12_4 + 2'in1_1 + 2'in1_3 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -2'in2_0 + -2'in2_2 + -2'in2_4 + 2'in3_1 + 2'in3_3 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_2 + -2'in4_4 + 2'aux8_1 + 2'aux8_3 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + -2'aux7_0 + -2'aux7_2 + -2'aux7_4 + 2'aux6_1 + 2'aux6_3 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + 2'aux5_1 + 2'aux5_3 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -4'c9_0 + -2'c110_0 + -2'aux16_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_0 + -2'aux15_2 + -2'aux15_4 + -1'aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + aux13_0 + 3'aux13_1 + aux13_2 + 3'aux13_3 + aux13_4 + 3'aux13_5 + 3'aux13_6 + 3'aux13_7 + -2'out1_0 + -2'out1_2 + -2'out1_4 + out2_0 + 3'out2_1 + out2_2 + 3'out2_3 + out2_4 + 3'out2_5 + 3'out2_6 + 3'out2_7 + -2'out3_0 + -2'out3_2 + -2'out3_4 + out4_0 + 3'out4_1 + out4_2 + 3'out4_3 + out4_4 + 3'out4_5 + 3'out4_6 + 3'out4_7 + -2'out5_0 + -2'out5_2 + -2'out5_4 + -1'out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_0 + -2'out7_2 + -2'out7_4 + -1'out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :c18_0 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 0
invariant :in1_0 + in1_1 + in1_2 + in1_3 + in1_4 + in1_5 + in1_6 + in1_7 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c20_0 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'c16_0 + -1'aux15_0 + -1'aux15_1 + -1'aux15_2 + -1'aux15_3 + -1'aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :-2'c5_0 + c8_0 + in4_0 + in4_1 + in4_2 + in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + -1'aux5_0 + -1'aux5_1 + -1'aux5_2 + -1'aux5_3 + -1'aux5_4 + -1'aux5_5 + -1'aux5_6 + -1'aux5_7 + 2'c9_0 + c110_0 = 0
invariant :-4'c13_0 + 2'aux12_0 + 2'aux12_1 + 2'aux12_2 + 2'aux12_3 + 2'aux12_4 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + aux15_0 + aux15_1 + aux15_2 + aux15_3 + aux15_4 + aux15_5 + aux15_6 + aux15_7 + -2'aux13_0 + -2'aux13_1 + -2'aux13_2 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + -2'aux13_7 + 2'c17_0 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :aux16_0 + aux16_1 + aux16_2 + aux16_3 + aux16_4 + aux16_5 + aux16_6 + aux16_7 + -2'c17_0 + -2'out2_0 + -2'out2_1 + -2'out2_2 + -2'out2_3 + -2'out2_4 + -2'out2_5 + -2'out2_6 + -2'out2_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_2 + 2'aux10_4 + -2'aux11_1 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + 2'aux12_0 + 2'aux12_2 + 2'aux12_4 + -2'in1_1 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 4'c5_0 + 2'in2_0 + 2'in2_2 + 2'in2_4 + -2'in3_1 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + 2'in4_0 + 2'in4_2 + 2'in4_4 + 2'aux8_0 + 2'aux8_2 + 2'aux8_4 + 2'aux7_0 + 2'aux7_2 + 2'aux7_4 + -2'aux6_1 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 2'aux5_0 + 2'aux5_2 + 2'aux5_4 + 2'c12_0 + 2'aux16_0 + 2'aux16_2 + 2'aux16_4 + 2'aux15_0 + 2'aux15_2 + 2'aux15_4 + aux14_0 + -1'aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + -1'aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'out1_0 + 2'out1_2 + 2'out1_4 + out2_0 + -1'out2_1 + out2_2 + -1'out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + 2'out3_0 + 2'out3_2 + 2'out3_4 + out4_0 + -1'out4_1 + out4_2 + -1'out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + 2'out5_0 + 2'out5_2 + 2'out5_4 + out6_0 + -1'out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + 2'out7_0 + 2'out7_2 + 2'out7_4 + out8_0 + -1'out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 100
invariant :2'c5_0 + c6_0 + -1'in3_0 + -1'in3_1 + -1'in3_2 + -1'in3_3 + -1'in3_4 + -1'in3_5 + -1'in3_6 + -1'in3_7 = 0
invariant :c19_0 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 = 0
invariant :2'c13_0 + -2'c5_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + aux6_0 + aux6_1 + aux6_2 + aux6_3 + aux6_4 + aux6_5 + aux6_6 + aux6_7 + c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_3 + 2'aux9_4 + 2'aux9_7 + -2'aux10_5 + -2'aux10_6 + -2'aux11_5 + -2'aux11_6 + -2'aux12_5 + -2'aux12_6 + -2'in1_5 + -2'in1_6 + 4'c5_0 + -2'in2_5 + -2'in2_6 + -2'in3_5 + -2'in3_6 + -2'in4_5 + -2'in4_6 + -2'aux8_5 + -2'aux8_6 + -2'aux7_5 + -2'aux7_6 + -2'aux6_5 + -2'aux6_6 + 2'aux5_0 + 2'aux5_1 + 2'aux5_2 + 2'aux5_3 + 2'aux5_4 + 2'aux5_7 + -2'c110_0 + -2'aux16_5 + -2'aux16_6 + -2'aux15_5 + -2'aux15_6 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + aux14_7 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + aux13_7 + -2'out1_5 + -2'out1_6 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + -1'out2_5 + -1'out2_6 + out2_7 + -2'out3_5 + -2'out3_6 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + -1'out4_5 + -1'out4_6 + out4_7 + -2'out5_5 + -2'out5_6 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + out6_7 + -2'out7_5 + -2'out7_6 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + out8_7 = 0
invariant :aux9_5 + aux10_5 + aux11_5 + aux12_5 + in1_5 + in2_5 + in3_5 + in4_5 + aux8_5 + aux7_5 + aux6_5 + aux5_5 + aux16_5 + aux15_5 + aux14_5 + aux13_5 + out1_5 + out2_5 + out3_5 + out4_5 + out5_5 + out6_5 + out7_5 + out8_5 = 50
invariant :aux9_6 + aux10_6 + aux11_6 + aux12_6 + in1_6 + in2_6 + in3_6 + in4_6 + aux8_6 + aux7_6 + aux6_6 + aux5_6 + aux16_6 + aux15_6 + aux14_6 + aux13_6 + out1_6 + out2_6 + out3_6 + out4_6 + out5_6 + out6_6 + out7_6 + out8_6 = 50
invariant :in2_0 + in2_1 + in2_2 + in2_3 + in2_4 + in2_5 + in2_6 + in2_7 + -1'in4_0 + -1'in4_1 + -1'in4_2 + -1'in4_3 + -1'in4_4 + -1'in4_5 + -1'in4_6 + -1'in4_7 = 0
invariant :2'c13_0 + 2'c5_0 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + c110_0 + 2'c11_0 + 2'c12_0 + aux13_0 + aux13_1 + aux13_2 + aux13_3 + aux13_4 + aux13_5 + aux13_6 + aux13_7 + out2_0 + out2_1 + out2_2 + out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out4_0 + out4_1 + out4_2 + out4_3 + out4_4 + out4_5 + out4_6 + out4_7 = 100
invariant :2'c14_0 + aux14_0 + aux14_1 + aux14_2 + aux14_3 + aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + out6_0 + out6_1 + out6_2 + out6_3 + out6_4 + out6_5 + out6_6 + out6_7 + out8_0 + out8_1 + out8_2 + out8_3 + out8_4 + out8_5 + out8_6 + out8_7 = 0
invariant :2'aux9_0 + 2'aux9_1 + 2'aux9_2 + 2'aux9_4 + 2'aux10_0 + 2'aux10_1 + 2'aux10_2 + 2'aux10_4 + -2'aux11_3 + -2'aux11_5 + -2'aux11_6 + -2'aux11_7 + -2'aux12_3 + -2'aux12_5 + -2'aux12_6 + -2'aux12_7 + -2'in1_3 + -2'in1_5 + -2'in1_6 + -2'in1_7 + 8'c5_0 + 2'in2_0 + 2'in2_1 + 2'in2_2 + 2'in2_4 + -2'in3_3 + -2'in3_5 + -2'in3_6 + -2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -4'in4_3 + -2'in4_4 + -4'in4_5 + -4'in4_6 + -4'in4_7 + -2'aux8_3 + -2'aux8_5 + -2'aux8_6 + -2'aux8_7 + -2'aux7_3 + -2'aux7_5 + -2'aux7_6 + -2'aux7_7 + -2'aux6_3 + -2'aux6_5 + -2'aux6_6 + -2'aux6_7 + 4'aux5_0 + 4'aux5_1 + 4'aux5_2 + 2'aux5_3 + 4'aux5_4 + 2'aux5_5 + 2'aux5_6 + 2'aux5_7 + -2'aux16_3 + -2'aux16_5 + -2'aux16_6 + -2'aux16_7 + aux15_0 + aux15_1 + aux15_2 + -1'aux15_3 + aux15_4 + -1'aux15_5 + -1'aux15_6 + -1'aux15_7 + aux14_0 + aux14_1 + aux14_2 + -1'aux14_3 + aux14_4 + -1'aux14_5 + -1'aux14_6 + -1'aux14_7 + aux13_0 + aux13_1 + aux13_2 + -1'aux13_3 + aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + 2'c17_0 + 2'out1_0 + 2'out1_1 + 2'out1_2 + 2'out1_4 + 2'out2_0 + 2'out2_1 + 2'out2_2 + 2'out2_4 + -2'out3_3 + -2'out3_5 + -2'out3_6 + -2'out3_7 + 2'out4_0 + 2'out4_1 + 2'out4_2 + 2'out4_4 + -2'out5_3 + -2'out5_5 + -2'out5_6 + -2'out5_7 + out6_0 + out6_1 + out6_2 + -1'out6_3 + out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 + -2'out7_3 + -2'out7_5 + -2'out7_6 + -2'out7_7 + out8_0 + out8_1 + out8_2 + -1'out8_3 + out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :aux9_3 + aux10_3 + aux11_3 + aux12_3 + in1_3 + -1'in2_0 + -1'in2_1 + -1'in2_2 + -1'in2_4 + -1'in2_5 + -1'in2_6 + -1'in2_7 + in3_3 + in4_0 + in4_1 + in4_2 + 2'in4_3 + in4_4 + in4_5 + in4_6 + in4_7 + aux8_3 + aux7_3 + aux6_3 + aux5_3 + aux16_3 + aux15_3 + aux14_3 + aux13_3 + -1'out1_0 + -1'out1_1 + -1'out1_2 + -1'out1_4 + -1'out1_5 + -1'out1_6 + -1'out1_7 + out2_0 + out2_1 + out2_2 + 2'out2_3 + out2_4 + out2_5 + out2_6 + out2_7 + out3_3 + out4_3 + out5_3 + out6_3 + out7_3 + out8_3 = 50
invariant :-4'c13_0 + -2'aux9_2 + -2'aux9_4 + -2'aux10_2 + -2'aux10_4 + 2'aux11_0 + 2'aux11_1 + 2'aux11_3 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + -2'aux12_2 + -2'aux12_4 + -2'in1_2 + -2'in1_4 + -2'in2_2 + -2'in2_4 + -2'in3_2 + -2'in3_4 + -2'in4_2 + -2'in4_4 + -2'aux8_2 + -2'aux8_4 + -2'aux7_2 + -2'aux7_4 + -2'aux6_2 + -2'aux6_4 + -2'aux5_2 + -2'aux5_4 + -4'c12_0 + -2'aux16_2 + -2'aux16_4 + -2'aux15_2 + -2'aux15_4 + aux14_0 + aux14_1 + -1'aux14_2 + aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -3'aux13_2 + -1'aux13_3 + -3'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux13_7 + -2'out1_2 + -2'out1_4 + -1'out2_0 + -1'out2_1 + -3'out2_2 + -1'out2_3 + -3'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 + -2'out3_2 + -2'out3_4 + -1'out4_0 + -1'out4_1 + -3'out4_2 + -1'out4_3 + -3'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 + -2'out5_2 + -2'out5_4 + out6_0 + out6_1 + -1'out6_2 + out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + -2'out7_2 + -2'out7_4 + out8_0 + out8_1 + -1'out8_2 + out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = -200
invariant :aux9_4 + aux10_4 + aux11_4 + aux12_4 + in1_4 + in2_4 + in3_4 + in4_4 + aux8_4 + aux7_4 + aux6_4 + aux5_4 + aux16_4 + aux15_4 + aux14_4 + aux13_4 + out1_4 + out2_4 + out3_4 + out4_4 + out5_4 + out6_4 + out7_4 + out8_4 = 50
invariant :aux9_2 + aux10_2 + aux11_2 + aux12_2 + in1_2 + in2_2 + in3_2 + in4_2 + aux8_2 + aux7_2 + aux6_2 + aux5_2 + aux16_2 + aux15_2 + aux14_2 + aux13_2 + out1_2 + out2_2 + out3_2 + out4_2 + out5_2 + out6_2 + out7_2 + out8_2 = 50
invariant :2'c7_0 + 2'in3_0 + 2'in3_1 + 2'in3_2 + 2'in3_3 + 2'in3_4 + 2'in3_5 + 2'in3_6 + 2'in3_7 + -2'in4_0 + -2'in4_1 + -2'in4_2 + -2'in4_3 + -2'in4_4 + -2'in4_5 + -2'in4_6 + -2'in4_7 + aux5_0 + aux5_1 + aux5_2 + aux5_3 + aux5_4 + aux5_5 + aux5_6 + aux5_7 + -2'c9_0 + -1'c110_0 = 0
invariant :-2'aux9_0 + -2'aux9_1 + -2'aux9_2 + -2'aux9_3 + -2'aux9_4 + 2'aux10_5 + 2'aux10_6 + 2'aux10_7 + 2'aux11_5 + 2'aux11_6 + 2'aux11_7 + 2'aux12_5 + 2'aux12_6 + 2'aux12_7 + 2'in1_5 + 2'in1_6 + 2'in1_7 + -4'c5_0 + 2'in2_5 + 2'in2_6 + 2'in2_7 + 2'in3_5 + 2'in3_6 + 2'in3_7 + 2'in4_5 + 2'in4_6 + 2'in4_7 + 2'aux8_5 + 2'aux8_6 + 2'aux8_7 + 2'aux7_5 + 2'aux7_6 + 2'aux7_7 + 2'aux6_5 + 2'aux6_6 + 2'aux6_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + 2'c110_0 + 2'aux16_5 + 2'aux16_6 + 2'aux16_7 + 2'aux15_5 + 2'aux15_6 + 2'aux15_7 + -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + aux14_5 + aux14_6 + aux14_7 + -1'aux13_0 + -1'aux13_1 + -1'aux13_2 + -1'aux13_3 + -1'aux13_4 + aux13_5 + aux13_6 + aux13_7 + 2'out1_5 + 2'out1_6 + 2'out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + out2_5 + out2_6 + out2_7 + 2'out3_5 + 2'out3_6 + 2'out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + out4_5 + out4_6 + out4_7 + 2'out5_5 + 2'out5_6 + 2'out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + out6_5 + out6_6 + out6_7 + 2'out7_5 + 2'out7_6 + 2'out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + out8_5 + out8_6 + out8_7 = 100
invariant :out1_0 + out1_1 + out1_2 + out1_3 + out1_4 + out1_5 + out1_6 + out1_7 + -1'out2_0 + -1'out2_1 + -1'out2_2 + -1'out2_3 + -1'out2_4 + -1'out2_5 + -1'out2_6 + -1'out2_7 = 0
invariant :out3_0 + out3_1 + out3_2 + out3_3 + out3_4 + out3_5 + out3_6 + out3_7 + -1'out4_0 + -1'out4_1 + -1'out4_2 + -1'out4_3 + -1'out4_4 + -1'out4_5 + -1'out4_6 + -1'out4_7 = 0
invariant :out5_0 + out5_1 + out5_2 + out5_3 + out5_4 + out5_5 + out5_6 + out5_7 + -1'out6_0 + -1'out6_1 + -1'out6_2 + -1'out6_3 + -1'out6_4 + -1'out6_5 + -1'out6_6 + -1'out6_7 = 0
invariant :out7_0 + out7_1 + out7_2 + out7_3 + out7_4 + out7_5 + out7_6 + out7_7 + -1'out8_0 + -1'out8_1 + -1'out8_2 + -1'out8_3 + -1'out8_4 + -1'out8_5 + -1'out8_6 + -1'out8_7 = 0
invariant :-4'c5_0 + 2'in4_0 + 2'in4_1 + 2'in4_2 + 2'in4_3 + 2'in4_4 + 2'in4_5 + 2'in4_6 + 2'in4_7 + aux7_0 + aux7_1 + aux7_2 + aux7_3 + aux7_4 + aux7_5 + aux7_6 + aux7_7 + -2'aux5_0 + -2'aux5_1 + -2'aux5_2 + -2'aux5_3 + -2'aux5_4 + -2'aux5_5 + -2'aux5_6 + -2'aux5_7 + 2'c9_0 + c110_0 = 0
FORMULA PermAdmissibility-COL-50-ReachabilityCardinality-02 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 31092 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 151 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality05==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality05==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality09==true], workingDir=/home/mcc/execution]
LTSmin run took 94277 ms.
Found Violation
FORMULA PermAdmissibility-COL-50-ReachabilityCardinality-09 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
255

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 4:53:13 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 4:53:13 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 4:53:13 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 24, 2018 4:53:15 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1173 ms
May 24, 2018 4:53:15 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 40 places.
May 24, 2018 4:53:15 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 24, 2018 4:53:15 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :input->aux9,aux10,aux11,aux12,in1,in2,in3,in4,aux8,aux7,aux6,aux5,aux16,aux15,aux14,aux13,out1,out2,out3,out4,out5,out6,out7,out8,
Dot->c16,c15,c14,c13,c5,c6,c7,c8,c9,c110,c11,c12,c17,c18,c19,c20,

May 24, 2018 4:53:15 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 16 transitions.
May 24, 2018 4:53:15 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 24, 2018 4:53:15 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 11 ms
May 24, 2018 4:53:15 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 289 ms
May 24, 2018 4:53:18 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 196 ms
May 24, 2018 4:53:18 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 31 ms
May 24, 2018 4:53:18 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
May 24, 2018 4:53:18 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 270 ms
May 24, 2018 4:53:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
May 24, 2018 4:53:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 167 ms.
May 24, 2018 4:53:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
May 24, 2018 4:53:19 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 4 ms.
May 24, 2018 4:53:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 3263 ms.
May 24, 2018 4:53:21 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 31 place invariants in 339 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=0 took 200 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=0 took 63 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=0 took 1 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=0 took 30 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=0 took 31 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=0 took 1 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=0 took 54 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=0 took 11 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
May 24, 2018 4:53:22 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 3 ms.
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=0 took 79 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=0 took 31 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=0 took 95 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=0 took 9 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=0 took 95 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=0 took 11 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=0 took 24 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=0 took 11 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=1 took 18 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=1 took 38 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=1 took 28 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=1 took 24 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=1 took 16 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=1 took 32 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=1 took 33 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=1 took 30 ms
May 24, 2018 4:53:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=1 took 83 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=1 took 56 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=1 took 27 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=1 took 28 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=1 took 19 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=1 took 40 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=1 took 19 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=1 took 32 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=2 took 268 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 31 place invariants in 296 ms
May 24, 2018 4:53:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=2 took 164 ms
May 24, 2018 4:53:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=2 took 457 ms
May 24, 2018 4:53:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=2 took 223 ms
May 24, 2018 4:53:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=2 took 174 ms
May 24, 2018 4:53:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=2 took 345 ms
May 24, 2018 4:53:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=2 took 517 ms
May 24, 2018 4:53:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=2 took 201 ms
May 24, 2018 4:53:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=2 took 229 ms
May 24, 2018 4:53:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=2 took 134 ms
May 24, 2018 4:53:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=2 took 326 ms
May 24, 2018 4:53:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=2 took 384 ms
May 24, 2018 4:53:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=2 took 318 ms
May 24, 2018 4:53:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=2 took 254 ms
May 24, 2018 4:53:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=2 took 235 ms
May 24, 2018 4:53:27 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 208 variables to be positive in 6320 ms
May 24, 2018 4:53:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 1024 transitions.
May 24, 2018 4:53:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/1024 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 4:53:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 248 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 4:53:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 1024 transitions.
May 24, 2018 4:53:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 116 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 4:53:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=2 took 793 ms
May 24, 2018 4:53:29 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 208 variables to be positive in 6414 ms
May 24, 2018 4:53:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=3 took 22877 ms
May 24, 2018 4:53:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=3 took 2122 ms
May 24, 2018 4:53:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(UNSAT) depth K=3 took 3669 ms
May 24, 2018 4:53:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=3 took 2870 ms
May 24, 2018 4:54:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=3 took 11968 ms
May 24, 2018 4:54:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=3 took 2968 ms
May 24, 2018 4:54:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=3 took 16218 ms
May 24, 2018 4:54:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=3 took 14066 ms
May 24, 2018 4:54:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=3 took 2408 ms
May 24, 2018 4:55:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-00
May 24, 2018 4:55:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(SAT) depth K=0 took 115268 ms
May 24, 2018 4:55:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=3 took 51817 ms
May 24, 2018 4:55:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-01
May 24, 2018 4:55:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(SAT) depth K=0 took 22147 ms
May 24, 2018 4:55:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=3 took 9249 ms
May 24, 2018 4:56:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=3 took 15255 ms
May 24, 2018 4:56:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(UNSAT) depth K=3 took 8414 ms
May 24, 2018 4:56:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate PermAdmissibility-COL-50-ReachabilityCardinality-02
May 24, 2018 4:56:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for PermAdmissibility-COL-50-ReachabilityCardinality-02
May 24, 2018 4:56:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-02(FALSE) depth K=0 took 32681 ms
May 24, 2018 4:56:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(UNSAT) depth K=3 took 31660 ms
May 24, 2018 4:56:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(UNSAT) depth K=3 took 1691 ms
May 24, 2018 4:56:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-03
May 24, 2018 4:56:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(SAT) depth K=0 took 28142 ms
May 24, 2018 4:57:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-04
May 24, 2018 4:57:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(SAT) depth K=0 took 26031 ms
May 24, 2018 4:57:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(UNSAT) depth K=3 took 30397 ms
May 24, 2018 4:57:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-05
May 24, 2018 4:57:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(SAT) depth K=0 took 18354 ms
May 24, 2018 4:58:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 1024 transitions.
May 24, 2018 4:58:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/1024) took 21916 ms. Total solver calls (SAT/UNSAT): 1002(1002/0)
May 24, 2018 4:59:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(1/1024) took 47669 ms. Total solver calls (SAT/UNSAT): 2003(2003/0)
May 24, 2018 4:59:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(UNSAT) depth K=4 took 131702 ms
May 24, 2018 4:59:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/1024) took 66864 ms. Total solver calls (SAT/UNSAT): 3019(3019/0)
May 24, 2018 5:00:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(3/1024) took 91356 ms. Total solver calls (SAT/UNSAT): 4021(4021/0)
May 24, 2018 5:00:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-06
May 24, 2018 5:00:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(SAT) depth K=0 took 167427 ms
May 24, 2018 5:00:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/1024) took 118258 ms. Total solver calls (SAT/UNSAT): 5035(5035/0)
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:00:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-07
May 24, 2018 5:00:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(SAT) depth K=0 took 20785 ms
May 24, 2018 5:00:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-08
May 24, 2018 5:00:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(SAT) depth K=0 took 11523 ms
May 24, 2018 5:00:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/1024) took 145041 ms. Total solver calls (SAT/UNSAT): 6041(6041/0)
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:01:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(UNSAT) depth K=4 took 105908 ms
May 24, 2018 5:01:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-09
May 24, 2018 5:01:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(SAT) depth K=0 took 23046 ms
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:01:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/1024) took 167328 ms. Total solver calls (SAT/UNSAT): 7046(7046/0)
May 24, 2018 5:01:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-10
May 24, 2018 5:01:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(SAT) depth K=0 took 3687 ms
May 24, 2018 5:01:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(7/1024) took 187210 ms. Total solver calls (SAT/UNSAT): 8044(8044/0)
May 24, 2018 5:01:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-11
May 24, 2018 5:01:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(SAT) depth K=0 took 20699 ms
May 24, 2018 5:02:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(8/1024) took 219567 ms. Total solver calls (SAT/UNSAT): 9038(9038/0)
May 24, 2018 5:02:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-12
May 24, 2018 5:02:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-12(SAT) depth K=0 took 49341 ms
May 24, 2018 5:02:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/1024) took 239870 ms. Total solver calls (SAT/UNSAT): 9988(9988/0)
May 24, 2018 5:02:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(10/1024) took 255026 ms. Total solver calls (SAT/UNSAT): 10996(10996/0)
May 24, 2018 5:02:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-13
May 24, 2018 5:02:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-13(SAT) depth K=0 took 17551 ms
May 24, 2018 5:03:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/1024) took 272783 ms. Total solver calls (SAT/UNSAT): 11948(11948/0)
May 24, 2018 5:03:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/1024) took 287588 ms. Total solver calls (SAT/UNSAT): 12954(12954/0)
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:03:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(13/1024) took 306688 ms. Total solver calls (SAT/UNSAT): 13912(13912/0)
May 24, 2018 5:03:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(UNSAT) depth K=4 took 154447 ms
May 24, 2018 5:03:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-14
May 24, 2018 5:03:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-14(SAT) depth K=0 took 68062 ms
May 24, 2018 5:03:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(14/1024) took 324851 ms. Total solver calls (SAT/UNSAT): 14869(14869/0)
May 24, 2018 5:04:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-15
May 24, 2018 5:04:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-15(SAT) depth K=0 took 10644 ms
May 24, 2018 5:04:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/1024) took 346096 ms. Total solver calls (SAT/UNSAT): 15817(15817/0)
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:04:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(16/1024) took 369955 ms. Total solver calls (SAT/UNSAT): 16819(16819/0)
May 24, 2018 5:05:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(17/1024) took 391937 ms. Total solver calls (SAT/UNSAT): 17820(17820/0)
May 24, 2018 5:05:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/1024) took 412061 ms. Total solver calls (SAT/UNSAT): 18820(18820/0)
May 24, 2018 5:05:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(19/1024) took 432272 ms. Total solver calls (SAT/UNSAT): 19820(19820/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:06:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-00
May 24, 2018 5:06:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-00(SAT) depth K=1 took 122964 ms
May 24, 2018 5:06:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/1024) took 459463 ms. Total solver calls (SAT/UNSAT): 20822(20822/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:06:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/1024) took 501893 ms. Total solver calls (SAT/UNSAT): 21822(21822/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:07:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/1024) took 544240 ms. Total solver calls (SAT/UNSAT): 22821(22821/0)
May 24, 2018 5:08:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(23/1024) took 569582 ms. Total solver calls (SAT/UNSAT): 23817(23817/0)
May 24, 2018 5:08:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/1024) took 591470 ms. Total solver calls (SAT/UNSAT): 24795(24795/0)
May 24, 2018 5:08:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(25/1024) took 603135 ms. Total solver calls (SAT/UNSAT): 25352(25352/0)
May 24, 2018 5:08:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(26/1024) took 623388 ms. Total solver calls (SAT/UNSAT): 26344(26344/0)
May 24, 2018 5:09:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(27/1024) took 640690 ms. Total solver calls (SAT/UNSAT): 27280(27280/0)
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:09:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(UNSAT) depth K=4 took 342065 ms
May 24, 2018 5:09:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/1024) took 662556 ms. Total solver calls (SAT/UNSAT): 28270(28270/0)
SMT solver raised 'unknown', retrying with same input.
May 24, 2018 5:09:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(29/1024) took 684865 ms. Total solver calls (SAT/UNSAT): 29212(29212/0)
SMT solver raised 'unknown', retrying with same input.
SMT solver raised 'unknown' twice, overapproximating result to 1.
May 24, 2018 5:10:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/1024) took 691994 ms. Total solver calls (SAT/UNSAT): 29553(29553/0)
May 24, 2018 5:10:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 692215 ms. Total solver calls (SAT/UNSAT): 29553(29553/0)
May 24, 2018 5:10:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 1024 transitions.
May 24, 2018 5:10:04 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 24, 2018 5:10:04 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 24, 2018 5:10:05 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 24, 2018 5:10:05 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an error :unknown
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeDoNotAccord(NecessaryEnablingsolver.java:628)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:538)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 5:10:06 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1007622ms conformant to PINS in folder :/home/mcc/execution
May 24, 2018 5:11:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-01
May 24, 2018 5:11:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-01(SAT) depth K=1 took 315768 ms
May 24, 2018 5:11:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(UNSAT) depth K=4 took 132290 ms
May 24, 2018 5:15:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(UNSAT) depth K=4 took 236057 ms
May 24, 2018 5:18:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-03
May 24, 2018 5:18:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-03(SAT) depth K=1 took 399893 ms
May 24, 2018 5:18:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-04
May 24, 2018 5:18:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-04(SAT) depth K=1 took 22156 ms
May 24, 2018 5:18:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(UNSAT) depth K=4 took 189839 ms
May 24, 2018 5:19:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-05
May 24, 2018 5:19:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-05(SAT) depth K=1 took 38776 ms
May 24, 2018 5:22:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-06
May 24, 2018 5:22:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-06(SAT) depth K=1 took 204243 ms
May 24, 2018 5:22:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-07
May 24, 2018 5:22:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-07(SAT) depth K=1 took 10125 ms
May 24, 2018 5:29:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-08
May 24, 2018 5:29:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(SAT) depth K=1 took 410960 ms
May 24, 2018 5:33:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-08(UNSAT) depth K=4 took 866422 ms
May 24, 2018 5:41:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-09
May 24, 2018 5:41:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(SAT) depth K=1 took 697357 ms
pins2lts-mc, 0.000: Registering PINS so language module
pins2lts-mc, 0.000, ** error **: out of memory trying to get 4294967296
java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, PermAdmissibilityCOL50ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
255
at fr.lip6.move.gal.application.LTSminRunner.checkProperty(LTSminRunner.java:167)
at fr.lip6.move.gal.application.LTSminRunner.access$9(LTSminRunner.java:122)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:91)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 5:43:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-09(UNSAT) depth K=4 took 592738 ms
May 24, 2018 5:45:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-10
May 24, 2018 5:45:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(SAT) depth K=1 took 233489 ms
May 24, 2018 5:46:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-10(UNSAT) depth K=4 took 228321 ms
May 24, 2018 5:47:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesPermAdmissibility-COL-50-ReachabilityCardinality-11
May 24, 2018 5:47:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(SAT) depth K=1 took 134785 ms
May 24, 2018 5:52:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-50-ReachabilityCardinality-11(UNSAT) depth K=4 took 356820 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-50"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-50.tgz
mv PermAdmissibility-COL-50 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-COL-50, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666475400467"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;