Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
................................................................
/home/mcc/execution
total 224K
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 115 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 353 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 54K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is PermAdmissibility-COL-05, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666475400447
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-05-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527179117399

16:25:19.952 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
16:25:19.956 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Flatten gal took : 631 ms
Constant places removed 88 places and 240 transitions.
Iterating post reduction 0 with 88 rules applied. Total rules applied 88 place count 120 transition count 784
Constant places removed 16 places and 192 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 104 place count 104 transition count 592
Symmetric choice reduction at 2 with 28 rule applications. Total rules 132 place count 104 transition count 592
Constant places removed 28 places and 252 transitions.
Iterating post reduction 2 with 28 rules applied. Total rules applied 160 place count 76 transition count 340
Applied a total of 160 rules in 43 ms. Remains 76 /208 variables (removed 132) and now considering 340/1024 (removed 684) transitions.
// Phase 1: matrix 340 rows 76 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 340 rows 76 cols
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 5375 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 78 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
255
sparsehash FATAL ERROR: failed to allocate 31 groups

BK_STOP 1527180131598

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 4:25:19 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 4:25:19 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 4:25:19 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 24, 2018 4:25:20 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1008 ms
May 24, 2018 4:25:20 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 40 places.
May 24, 2018 4:25:20 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 24, 2018 4:25:20 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :input->aux9,aux10,aux11,aux12,in1,in3,in2,in4,aux8,aux6,aux7,aux5,aux16,aux13,aux15,aux14,out1,out5,out4,out3,out2,out8,out7,out6,
Dot->c16,c15,c14,c13,c6,c5,c8,c7,c9,c12,c110,c11,c17,c20,c18,c19,

May 24, 2018 4:25:20 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 16 transitions.
May 24, 2018 4:25:20 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 24, 2018 4:25:20 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 7 ms
May 24, 2018 4:25:20 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 202 ms
May 24, 2018 4:25:21 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 20 ms
May 24, 2018 4:25:21 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 16 transitions. Expanding to a total of 1200 deterministic transitions.
May 24, 2018 4:25:21 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 9 ms.
May 24, 2018 4:25:22 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 4 ms
May 24, 2018 4:25:22 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 340 transitions.
May 24, 2018 4:25:22 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 0 place invariants in 21 ms
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 76 variables to be positive in 617 ms
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 340 transitions.
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/340 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 64 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 340 transitions.
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 27 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 4:25:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 340 transitions.
May 24, 2018 4:25:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/340) took 3001 ms. Total solver calls (SAT/UNSAT): 2091(2091/0)
May 24, 2018 4:25:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(140/340) took 6029 ms. Total solver calls (SAT/UNSAT): 5928(5928/0)
May 24, 2018 4:25:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(234/340) took 9202 ms. Total solver calls (SAT/UNSAT): 9774(9774/0)
May 24, 2018 4:25:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(299/340) took 12308 ms. Total solver calls (SAT/UNSAT): 10462(10462/0)
May 24, 2018 4:25:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(312/340) took 15324 ms. Total solver calls (SAT/UNSAT): 10595(10595/0)
May 24, 2018 4:25:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 16291 ms. Total solver calls (SAT/UNSAT): 10738(10738/0)
May 24, 2018 4:25:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 340 transitions.
May 24, 2018 4:34:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 525397 ms. Total solver calls (SAT/UNSAT): 14905(0/14905)
May 24, 2018 4:34:25 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 543448ms conformant to PINS in folder :/home/mcc/execution
pins2lts-mc, 0.000: Registering PINS so language module
pins2lts-mc, 0.000: Loading model from ./gal.so
pins2lts-mc, 0.000: library has no initializer
pins2lts-mc, 0.000: loading model GAL
pins2lts-mc, 0.008: completed loading model GAL
pins2lts-mc, 0.008: Initializing POR dependencies: labels 340, guards 340
pins2lts-mc, 0.081: There are 340 state labels and 1 edge labels
pins2lts-mc, 0.082: State length is 76, there are 340 groups
pins2lts-mc, 0.082: Running bfs using 1 core (sequential)
pins2lts-mc, 0.082: Using a non-indexing tree table with 2^27 elements
pins2lts-mc, 0.082: Successor permutation: none
pins2lts-mc, 0.082: Visible groups: 0 / 340, labels: 0 / 340
pins2lts-mc, 0.082: POR cycle proviso: none
pins2lts-mc, 0.082: Global bits: 0, count bits: 0, local bits: 0
pins2lts-mc, 0.193: 6 levels 1000 states 5704 transitions
pins2lts-mc, 0.298: 7 levels 2000 states 11762 transitions
pins2lts-mc, 0.500: 8 levels 4000 states 22068 transitions
pins2lts-mc, 0.902: 9 levels 8000 states 42593 transitions
pins2lts-mc, 1.700: 10 levels 16000 states 85129 transitions
pins2lts-mc, 3.259: 10 levels 32000 states 148280 transitions
pins2lts-mc, 6.533: 12 levels 64000 states 263268 transitions
pins2lts-mc, 12.891: 14 levels 128000 states 448616 transitions
pins2lts-mc, 26.951: 23 levels 256000 states 1125620 transitions
pins2lts-mc, 68.882: 24 levels 512000 states 4587490 transitions
pins2lts-mc, 177.378: 24 levels 1024000 states 13069116 transitions
pins2lts-mc, 369.639, ** error **: out of memory trying to get 8388608
java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
255
at fr.lip6.move.gal.application.LTSminRunner.checkProperty(LTSminRunner.java:167)
at fr.lip6.move.gal.application.LTSminRunner.access$9(LTSminRunner.java:122)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:91)
at java.lang.Thread.run(Thread.java:748)
ITS-tools command line returned an error code 1

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-05"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-05.tgz
mv PermAdmissibility-COL-05 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-COL-05, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666475400447"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;