Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 572K
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 39K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 64K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 27K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 36K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 200K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-PT-6, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666475000138
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-6-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527165758746

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : LamportFastMutEx-PT-6-ReachabilityCardinality-00 with value :(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)+P_ifyi_15_6)<=((((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)+P_sety_9_6))
Read [invariant] property : LamportFastMutEx-PT-6-ReachabilityCardinality-01 with value :((((((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)+P_ifxi_10_5)+P_ifxi_10_6)<=(((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)+P_b_6_false)+P_b_6_true))||(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)+x_6)>=3))||(((((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5)+P_start_1_6)<=(((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)+P_b_6_false)+P_b_6_true)))&&(!(((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5)+P_setbi_11_6)>=3)))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-02 with value :(!((!(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)+y_6)>=3))||(!(((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5)+P_setbi_11_6)<=((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)+P_fordo_12_6)))))
Read [invariant] property : LamportFastMutEx-PT-6-ReachabilityCardinality-03 with value :((!(((((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)+P_b_6_false)+P_b_6_true)<=((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)+y_6))&&(((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)+P_CS_21_6)<=((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)+P_ifyi_15_6))))||(((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)+P_setbi_24_6)<=(((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)+P_b_6_false)+P_b_6_true)))
Read [invariant] property : LamportFastMutEx-PT-6-ReachabilityCardinality-04 with value :(!(((((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)+P_ifxi_10_5)+P_ifxi_10_6)>=2)||(((((((((((((((((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_0_6)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_1_6)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_2_6)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_3_6)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_4_6)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5)+P_wait_5_6)+P_wait_6_0)+P_wait_6_1)+P_wait_6_2)+P_wait_6_3)+P_wait_6_4)+P_wait_6_5)+P_wait_6_6)>=1))&&((((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)+P_setbi_5_6)>=3)||(((((((((((((((((((((((((((((((((((((((((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_0_3)+P_done_0_4)+P_done_0_5)+P_done_0_6)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_1_3)+P_done_1_4)+P_done_1_5)+P_done_1_6)+P_done_2_0)+P_done_2_1)+P_done_2_2)+P_done_2_3)+P_done_2_4)+P_done_2_5)+P_done_2_6)+P_done_3_0)+P_done_3_1)+P_done_3_2)+P_done_3_3)+P_done_3_4)+P_done_3_5)+P_done_3_6)+P_done_4_0)+P_done_4_1)+P_done_4_2)+P_done_4_3)+P_done_4_4)+P_done_4_5)+P_done_4_6)+P_done_5_0)+P_done_5_1)+P_done_5_2)+P_done_5_3)+P_done_5_4)+P_done_5_5)+P_done_5_6)+P_done_6_0)+P_done_6_1)+P_done_6_2)+P_done_6_3)+P_done_6_4)+P_done_6_5)+P_done_6_6)>=1))))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-05 with value :(((((((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)+P_sety_9_6)<=((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)+P_setbi_24_6))&&(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)+P_ifyi_15_6)<=((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)+P_setbi_5_6)))&&(!((((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)+P_ifyi_15_6)>=3)||((((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)+P_b_6_false)+P_b_6_true)>=1))))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-06 with value :(!(((((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)+P_await_13_6)<=((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)+P_setbi_24_6))||(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)+y_6)<=((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)+P_setbi_5_6)))||(((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)+P_setbi_24_6)>=2)))
Read [invariant] property : LamportFastMutEx-PT-6-ReachabilityCardinality-07 with value :((((((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)+P_setx_3_6)>=3)||(((((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5)+P_start_1_6)>=1))||((((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)+P_setbi_5_6)<=((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)+P_fordo_12_6))||(((((((((((((((((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_0_6)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_1_6)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_2_6)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_3_6)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_4_6)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5)+P_wait_5_6)+P_wait_6_0)+P_wait_6_1)+P_wait_6_2)+P_wait_6_3)+P_wait_6_4)+P_wait_6_5)+P_wait_6_6)<=((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)+P_setbi_24_6))))&&(!(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)+x_6)>=3)))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-08 with value :((P_b_4_true>=1)&&(((y_6<=x_0)||(P_wait_0_3<=P_start_1_3))&&((P_sety_9_1>=3)||(P_done_6_5>=1))))
Read [invariant] property : LamportFastMutEx-PT-6-ReachabilityCardinality-09 with value :(P_awaity_5<=P_fordo_12_5)
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-10 with value :(P_wait_0_5>=2)
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-11 with value :(!((P_done_0_0<=P_done_0_6)||((P_setbi_24_1<=P_b_1_false)&&(P_done_5_2>=2))))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-12 with value :((!((P_wait_2_2<=P_CS_21_2)&&(P_wait_0_2<=P_wait_5_0)))&&(P_done_4_6>=3))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-13 with value :((((P_done_2_0>=2)||(P_sety_9_6<=P_done_4_5))&&(P_done_6_5>=1))&&(((P_ifyi_15_5>=1)&&(P_setbi_24_6<=P_sety_9_1))&&(!(P_awaity_2>=2))))
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-14 with value :(P_b_1_true>=2)
Read [reachable] property : LamportFastMutEx-PT-6-ReachabilityCardinality-15 with value :(P_done_4_5>=3)
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 315
// Phase 1: matrix 315 rows 217 cols
invariant :P_wait_5_6 + -1'P_await_13_5 + P_done_5_6 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_6_5 + -1'P_await_13_6 + P_done_6_5 = 0
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_wait_6_6 + -1'P_await_13_6 + P_done_6_6 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 + x_6 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
invariant :P_b_6_false + P_b_6_true = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_3_6 + -1'P_await_13_3 + P_done_3_6 = 0
invariant :P_wait_1_6 + -1'P_await_13_1 + P_done_1_6 = 0
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_4_6 + -1'P_await_13_4 + P_done_4_6 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_6 + -1'P_await_13_2 + P_done_2_6 = 0
invariant :P_start_1_6 + P_setx_3_6 + P_setbi_5_6 + P_ify0_4_6 + P_sety_9_6 + P_ifxi_10_6 + P_setbi_11_6 + P_fordo_12_6 + P_await_13_6 + P_ifyi_15_6 + P_awaity_6 + P_CS_21_6 + P_setbi_24_6 = 1
invariant :P_wait_6_2 + -1'P_await_13_6 + P_done_6_2 = 0
invariant :P_wait_6_0 + P_done_6_0 = 0
invariant :P_wait_6_4 + -1'P_await_13_6 + P_done_6_4 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_6_1 + -1'P_await_13_6 + P_done_6_1 = 0
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_6_3 + -1'P_await_13_6 + P_done_6_3 = 0
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_0_6 + -1'P_await_13_0 + P_done_0_6 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 + y_6 = 1
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 315
// Phase 1: matrix 315 rows 217 cols
invariant :P_wait_5_6 + -1'P_await_13_5 + P_done_5_6 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_6_5 + -1'P_await_13_6 + P_done_6_5 = 0
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_wait_6_6 + -1'P_await_13_6 + P_done_6_6 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 + x_6 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
invariant :P_b_6_false + P_b_6_true = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_3_6 + -1'P_await_13_3 + P_done_3_6 = 0
invariant :P_wait_1_6 + -1'P_await_13_1 + P_done_1_6 = 0
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_4_6 + -1'P_await_13_4 + P_done_4_6 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_6 + -1'P_await_13_2 + P_done_2_6 = 0
invariant :P_start_1_6 + P_setx_3_6 + P_setbi_5_6 + P_ify0_4_6 + P_sety_9_6 + P_ifxi_10_6 + P_setbi_11_6 + P_fordo_12_6 + P_await_13_6 + P_ifyi_15_6 + P_awaity_6 + P_CS_21_6 + P_setbi_24_6 = 1
invariant :P_wait_6_2 + -1'P_await_13_6 + P_done_6_2 = 0
invariant :P_wait_6_0 + P_done_6_0 = 0
invariant :P_wait_6_4 + -1'P_await_13_6 + P_done_6_4 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_6_1 + -1'P_await_13_6 + P_done_6_1 = 0
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_6_3 + -1'P_await_13_6 + P_done_6_3 = 0
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_0_6 + -1'P_await_13_0 + P_done_0_6 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 + y_6 = 1
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-02 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-03 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-05 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-10 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-11 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-12 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-14 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-15 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6342 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 59 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
LTSmin run took 3600 ms.
Found Violation
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-04 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
LTSmin run took 2332 ms.
Found Violation
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-06 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
255
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_PT\_6\_flat\_flat,5.47232e+11,2088.31,13137080,2,1.88998e+06,5,2.76711e+07,6,0,1263,4.29856e+07,0
Total reachable state count : 547231759144

Verifying 16 reachability properties.
Invariant property LamportFastMutEx-PT-6-ReachabilityCardinality-00 does not hold.
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-00,1,2088.62,13137256,2,218,6,2.76711e+07,7,0,1280,4.29856e+07,0
Invariant property LamportFastMutEx-PT-6-ReachabilityCardinality-01 does not hold.
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-01,1,2089.92,13137360,2,218,7,2.76711e+07,8,0,1482,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-02 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-02,0,2093.68,13137360,1,0,7,2.76711e+07,9,0,1510,4.29856e+07,0
Invariant property LamportFastMutEx-PT-6-ReachabilityCardinality-03 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-03,0,2098.78,13137360,1,0,7,2.76711e+07,10,0,1659,4.29856e+07,0
Invariant property LamportFastMutEx-PT-6-ReachabilityCardinality-04 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-04,1,2098.8,13137360,2,218,8,2.76711e+07,11,0,1775,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-05 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-05,0,2102.42,13137360,1,0,8,2.76711e+07,12,0,1874,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-06 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-06,5.85846e+09,2115.91,13137360,2,777605,9,2.76711e+07,13,0,2101,4.29856e+07,0
Invariant property LamportFastMutEx-PT-6-ReachabilityCardinality-07 does not hold.
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-07,1,2116.36,13137360,2,218,10,2.76711e+07,14,0,2210,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-08 is true.
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-08,4.61496e+09,2124.08,13137360,2,164090,11,2.76711e+07,15,0,2227,4.29856e+07,0
Invariant property LamportFastMutEx-PT-6-ReachabilityCardinality-09 does not hold.
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-09,5.09336e+08,2124.35,13137360,2,104623,12,2.76711e+07,16,0,2231,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-10 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-10,0,2127.82,13137360,1,0,12,2.76711e+07,17,0,2232,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-11 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-11,0,2130.82,13137360,1,0,12,2.76711e+07,18,0,2241,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-12 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-12,0,2130.83,13137360,1,0,12,2.76711e+07,19,0,2246,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-13 is true.
FORMULA LamportFastMutEx-PT-6-ReachabilityCardinality-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-13,2.43856e+08,2132.62,13137360,2,51389,13,2.76711e+07,20,0,2267,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-14 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-14,0,2143.12,13137360,1,0,13,2.76711e+07,21,0,2268,4.29856e+07,0
Reachability property LamportFastMutEx-PT-6-ReachabilityCardinality-15 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-6-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-6-ReachabilityCardinality-15,0,2143.19,13137360,1,0,13,2.76711e+07,22,0,2269,4.29856e+07,0
ITS tools runner thread asked to quit. Dying gracefully.

BK_STOP 1527167920591

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:42:40 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:42:40 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:42:40 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 96 ms
May 24, 2018 12:42:40 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 217 places.
May 24, 2018 12:42:40 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 420 transitions.
May 24, 2018 12:42:40 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 25 ms
May 24, 2018 12:42:41 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 156 ms
May 24, 2018 12:42:41 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 207 ms
May 24, 2018 12:42:41 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 200 ms
May 24, 2018 12:42:41 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 5 ms
May 24, 2018 12:42:41 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 12:42:41 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 420 transitions.
May 24, 2018 12:42:41 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 420 transitions.
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 65 place invariants in 129 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 756 ms.
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(UNSAT) depth K=0 took 21 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-02(UNSAT) depth K=0 took 16 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 420 transitions.
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-03(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(UNSAT) depth K=0 took 16 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-05(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(UNSAT) depth K=0 took 8 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(UNSAT) depth K=0 took 17 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(UNSAT) depth K=0 took 13 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(UNSAT) depth K=0 took 9 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-10(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-11(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-12(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(UNSAT) depth K=0 took 8 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-14(UNSAT) depth K=0 took 27 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-15(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(UNSAT) depth K=1 took 15 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 65 place invariants in 43 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(UNSAT) depth K=1 took 18 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-02(UNSAT) depth K=1 took 28 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-03(UNSAT) depth K=1 took 19 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(UNSAT) depth K=1 took 22 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-05(UNSAT) depth K=1 took 18 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(UNSAT) depth K=1 took 8 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(UNSAT) depth K=1 took 17 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(UNSAT) depth K=1 took 10 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(UNSAT) depth K=1 took 7 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-10(UNSAT) depth K=1 took 7 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-11(UNSAT) depth K=1 took 6 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-12(UNSAT) depth K=1 took 6 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(UNSAT) depth K=1 took 8 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-14(UNSAT) depth K=1 took 7 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-15(UNSAT) depth K=1 took 6 ms
May 24, 2018 12:42:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(UNSAT) depth K=2 took 95 ms
May 24, 2018 12:42:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(UNSAT) depth K=2 took 269 ms
May 24, 2018 12:42:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-02(UNSAT) depth K=2 took 100 ms
May 24, 2018 12:42:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-03(UNSAT) depth K=2 took 279 ms
May 24, 2018 12:42:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(UNSAT) depth K=2 took 335 ms
May 24, 2018 12:42:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-05(UNSAT) depth K=2 took 170 ms
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(UNSAT) depth K=2 took 129 ms
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(UNSAT) depth K=2 took 550 ms
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 217 variables to be positive in 2718 ms
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 420 transitions.
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/420 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 58 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 420 transitions.
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 18 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(UNSAT) depth K=2 took 232 ms
May 24, 2018 12:42:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(UNSAT) depth K=2 took 164 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-10(UNSAT) depth K=2 took 69 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 217 variables to be positive in 2672 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-11(UNSAT) depth K=2 took 311 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-00
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(SAT) depth K=0 took 451 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-12(UNSAT) depth K=2 took 244 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(UNSAT) depth K=2 took 84 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-14(UNSAT) depth K=2 took 98 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-01
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(SAT) depth K=0 took 368 ms
May 24, 2018 12:42:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-15(UNSAT) depth K=2 took 124 ms
May 24, 2018 12:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(UNSAT) depth K=3 took 1117 ms
May 24, 2018 12:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-02
May 24, 2018 12:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-02
May 24, 2018 12:42:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-02(FALSE) depth K=0 took 1210 ms
May 24, 2018 12:42:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-PT-6-ReachabilityCardinality-03
May 24, 2018 12:42:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-03
May 24, 2018 12:42:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-03(TRUE) depth K=0 took 5671 ms
May 24, 2018 12:42:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-04
May 24, 2018 12:42:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(SAT) depth K=0 took 437 ms
May 24, 2018 12:42:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(UNSAT) depth K=3 took 8766 ms
May 24, 2018 12:42:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-05
May 24, 2018 12:42:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-05
May 24, 2018 12:42:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-05(FALSE) depth K=0 took 5134 ms
May 24, 2018 12:42:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-06
May 24, 2018 12:42:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(SAT) depth K=0 took 1065 ms
May 24, 2018 12:42:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-02(UNSAT) depth K=3 took 4089 ms
May 24, 2018 12:43:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-07
May 24, 2018 12:43:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(SAT) depth K=0 took 1823 ms
May 24, 2018 12:43:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-08
May 24, 2018 12:43:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(SAT) depth K=0 took 499 ms
May 24, 2018 12:43:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-09
May 24, 2018 12:43:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(SAT) depth K=0 took 1234 ms
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-10
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-10
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-10(FALSE) depth K=0 took 206 ms
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-11
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-11
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-11(FALSE) depth K=0 took 251 ms
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-12
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-12
May 24, 2018 12:43:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-12(FALSE) depth K=0 took 209 ms
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-13
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(SAT) depth K=0 took 557 ms
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-14
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-14
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-14(FALSE) depth K=0 took 204 ms
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-6-ReachabilityCardinality-15
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-6-ReachabilityCardinality-15
May 24, 2018 12:43:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-15(FALSE) depth K=0 took 221 ms
May 24, 2018 12:43:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-03(UNSAT) depth K=3 took 7247 ms
May 24, 2018 12:43:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(UNSAT) depth K=3 took 1177 ms
May 24, 2018 12:43:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-00
May 24, 2018 12:43:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(SAT) depth K=1 took 6681 ms
May 24, 2018 12:43:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 420 transitions.
May 24, 2018 12:43:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/420) took 588 ms. Total solver calls (SAT/UNSAT): 65(0/65)
May 24, 2018 12:43:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-01
May 24, 2018 12:43:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(SAT) depth K=1 took 4532 ms
May 24, 2018 12:43:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-05(UNSAT) depth K=3 took 9825 ms
May 24, 2018 12:43:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(6/420) took 3886 ms. Total solver calls (SAT/UNSAT): 452(18/434)
May 24, 2018 12:43:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-04
May 24, 2018 12:43:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(SAT) depth K=1 took 6117 ms
May 24, 2018 12:43:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/420) took 6986 ms. Total solver calls (SAT/UNSAT): 774(30/744)
May 24, 2018 12:43:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-06
May 24, 2018 12:43:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(SAT) depth K=1 took 1089 ms
May 24, 2018 12:43:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(UNSAT) depth K=3 took 5873 ms
May 24, 2018 12:43:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/420) took 10590 ms. Total solver calls (SAT/UNSAT): 1184(36/1148)
May 24, 2018 12:43:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(UNSAT) depth K=3 took 4761 ms
May 24, 2018 12:43:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/420) took 14055 ms. Total solver calls (SAT/UNSAT): 1598(36/1562)
May 24, 2018 12:43:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(21/420) took 17736 ms. Total solver calls (SAT/UNSAT): 2003(47/1956)
May 24, 2018 12:43:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(UNSAT) depth K=3 took 4327 ms
May 24, 2018 12:43:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(UNSAT) depth K=3 took 2112 ms
May 24, 2018 12:43:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/420) took 21084 ms. Total solver calls (SAT/UNSAT): 2399(80/2319)
May 24, 2018 12:43:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-10(UNSAT) depth K=3 took 2227 ms
May 24, 2018 12:43:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(27/420) took 24324 ms. Total solver calls (SAT/UNSAT): 2786(113/2673)
May 24, 2018 12:43:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-11(UNSAT) depth K=3 took 4445 ms
May 24, 2018 12:43:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-12(UNSAT) depth K=3 took 618 ms
May 24, 2018 12:43:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(30/420) took 27522 ms. Total solver calls (SAT/UNSAT): 3164(143/3021)
May 24, 2018 12:43:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(UNSAT) depth K=3 took 2220 ms
May 24, 2018 12:43:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(33/420) took 30695 ms. Total solver calls (SAT/UNSAT): 3533(173/3360)
May 24, 2018 12:43:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-14(UNSAT) depth K=3 took 1373 ms
May 24, 2018 12:43:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-15(UNSAT) depth K=3 took 1972 ms
May 24, 2018 12:43:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(36/420) took 33756 ms. Total solver calls (SAT/UNSAT): 3893(201/3692)
May 24, 2018 12:43:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(39/420) took 36768 ms. Total solver calls (SAT/UNSAT): 4244(228/4016)
May 24, 2018 12:43:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-07
May 24, 2018 12:43:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(SAT) depth K=1 took 29595 ms
May 24, 2018 12:43:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/420) took 40554 ms. Total solver calls (SAT/UNSAT): 4698(262/4436)
May 24, 2018 12:43:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-08
May 24, 2018 12:43:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(SAT) depth K=1 took 2961 ms
May 24, 2018 12:43:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/420) took 44307 ms. Total solver calls (SAT/UNSAT): 5136(294/4842)
May 24, 2018 12:44:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-09
May 24, 2018 12:44:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(SAT) depth K=1 took 6023 ms
May 24, 2018 12:44:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(51/420) took 47947 ms. Total solver calls (SAT/UNSAT): 5558(323/5235)
May 24, 2018 12:44:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-13
May 24, 2018 12:44:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(SAT) depth K=1 took 4310 ms
May 24, 2018 12:44:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/420) took 51398 ms. Total solver calls (SAT/UNSAT): 5964(351/5613)
May 24, 2018 12:44:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(59/420) took 54702 ms. Total solver calls (SAT/UNSAT): 6354(375/5979)
May 24, 2018 12:44:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(63/420) took 59066 ms. Total solver calls (SAT/UNSAT): 6860(393/6467)
May 24, 2018 12:44:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(UNSAT) depth K=4 took 28816 ms
May 24, 2018 12:44:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(65/420) took 62694 ms. Total solver calls (SAT/UNSAT): 7305(393/6912)
May 24, 2018 12:44:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(67/420) took 66420 ms. Total solver calls (SAT/UNSAT): 7746(393/7353)
May 24, 2018 12:44:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(69/420) took 70091 ms. Total solver calls (SAT/UNSAT): 8183(416/7767)
May 24, 2018 12:44:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(71/420) took 73771 ms. Total solver calls (SAT/UNSAT): 8616(462/8154)
May 24, 2018 12:44:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/420) took 77363 ms. Total solver calls (SAT/UNSAT): 9045(508/8537)
May 24, 2018 12:44:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(75/420) took 81016 ms. Total solver calls (SAT/UNSAT): 9470(553/8917)
May 24, 2018 12:44:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(77/420) took 85010 ms. Total solver calls (SAT/UNSAT): 9891(597/9294)
May 24, 2018 12:44:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/420) took 88589 ms. Total solver calls (SAT/UNSAT): 10308(641/9667)
May 24, 2018 12:44:47 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(81/420) took 92120 ms. Total solver calls (SAT/UNSAT): 10721(684/10037)
May 24, 2018 12:44:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(83/420) took 96282 ms. Total solver calls (SAT/UNSAT): 11130(726/10404)
May 24, 2018 12:44:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(85/420) took 99748 ms. Total solver calls (SAT/UNSAT): 11535(768/10767)
May 24, 2018 12:44:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(87/420) took 104259 ms. Total solver calls (SAT/UNSAT): 11936(809/11127)
May 24, 2018 12:44:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-00
May 24, 2018 12:44:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(SAT) depth K=2 took 53893 ms
May 24, 2018 12:45:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/420) took 108402 ms. Total solver calls (SAT/UNSAT): 12333(849/11484)
May 24, 2018 12:45:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(91/420) took 111890 ms. Total solver calls (SAT/UNSAT): 12726(889/11837)
May 24, 2018 12:45:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(93/420) took 115406 ms. Total solver calls (SAT/UNSAT): 13115(928/12187)
May 24, 2018 12:45:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(95/420) took 119180 ms. Total solver calls (SAT/UNSAT): 13500(966/12534)
May 24, 2018 12:45:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(96/420) took 123653 ms. Total solver calls (SAT/UNSAT): 13691(985/12706)
May 24, 2018 12:45:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-01
May 24, 2018 12:45:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(SAT) depth K=2 took 22649 ms
May 24, 2018 12:45:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/420) took 127950 ms. Total solver calls (SAT/UNSAT): 14070(1023/13047)
May 24, 2018 12:45:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(100/420) took 132031 ms. Total solver calls (SAT/UNSAT): 14445(1059/13386)
May 24, 2018 12:45:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(102/420) took 136176 ms. Total solver calls (SAT/UNSAT): 14816(1095/13721)
May 24, 2018 12:45:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/420) took 139550 ms. Total solver calls (SAT/UNSAT): 15183(1131/14052)
May 24, 2018 12:45:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(111/420) took 142712 ms. Total solver calls (SAT/UNSAT): 15530(1149/14381)
May 24, 2018 12:45:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(116/420) took 146974 ms. Total solver calls (SAT/UNSAT): 15777(1161/14616)
May 24, 2018 12:45:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(119/420) took 150106 ms. Total solver calls (SAT/UNSAT): 16056(1167/14889)
May 24, 2018 12:45:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(121/420) took 153310 ms. Total solver calls (SAT/UNSAT): 16413(1224/15189)
May 24, 2018 12:45:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(123/420) took 156318 ms. Total solver calls (SAT/UNSAT): 16766(1277/15489)
May 24, 2018 12:45:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(125/420) took 160326 ms. Total solver calls (SAT/UNSAT): 17115(1326/15789)
May 24, 2018 12:45:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/420) took 163422 ms. Total solver calls (SAT/UNSAT): 17460(1349/16111)
May 24, 2018 12:46:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(130/420) took 167786 ms. Total solver calls (SAT/UNSAT): 17970(1412/16558)
May 24, 2018 12:46:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(133/420) took 172038 ms. Total solver calls (SAT/UNSAT): 18471(1449/17022)
May 24, 2018 12:46:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(136/420) took 176538 ms. Total solver calls (SAT/UNSAT): 18963(1449/17514)
May 24, 2018 12:46:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(138/420) took 179597 ms. Total solver calls (SAT/UNSAT): 19286(1449/17837)
May 24, 2018 12:46:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(141/420) took 183671 ms. Total solver calls (SAT/UNSAT): 19763(1483/18280)
May 24, 2018 12:46:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(144/420) took 187618 ms. Total solver calls (SAT/UNSAT): 20231(1534/18697)
May 24, 2018 12:46:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(147/420) took 191394 ms. Total solver calls (SAT/UNSAT): 20690(1584/19106)
May 24, 2018 12:46:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(UNSAT) depth K=4 took 130208 ms
May 24, 2018 12:46:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(150/420) took 195199 ms. Total solver calls (SAT/UNSAT): 21140(1632/19508)
May 24, 2018 12:46:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/420) took 199026 ms. Total solver calls (SAT/UNSAT): 21581(1680/19901)
May 24, 2018 12:46:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(156/420) took 202798 ms. Total solver calls (SAT/UNSAT): 22013(1725/20288)
May 24, 2018 12:46:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(159/420) took 206402 ms. Total solver calls (SAT/UNSAT): 22436(1770/20666)
May 24, 2018 12:46:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(162/420) took 209900 ms. Total solver calls (SAT/UNSAT): 22850(1813/21037)
May 24, 2018 12:46:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(165/420) took 214610 ms. Total solver calls (SAT/UNSAT): 23255(1855/21400)
May 24, 2018 12:46:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(166/420) took 217616 ms. Total solver calls (SAT/UNSAT): 23388(1869/21519)
May 24, 2018 12:46:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(169/420) took 221359 ms. Total solver calls (SAT/UNSAT): 23781(1909/21872)
May 24, 2018 12:46:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(172/420) took 224915 ms. Total solver calls (SAT/UNSAT): 24165(1948/22217)
May 24, 2018 12:47:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(UNSAT) depth K=4 took 34550 ms
May 24, 2018 12:47:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(175/420) took 228541 ms. Total solver calls (SAT/UNSAT): 24540(1986/22554)
May 24, 2018 12:47:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(178/420) took 232284 ms. Total solver calls (SAT/UNSAT): 24906(2022/22884)
May 24, 2018 12:47:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(181/420) took 235298 ms. Total solver calls (SAT/UNSAT): 25263(2058/23205)
May 24, 2018 12:47:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(186/420) took 238498 ms. Total solver calls (SAT/UNSAT): 25628(2058/23570)
May 24, 2018 12:47:16 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(191/420) took 241640 ms. Total solver calls (SAT/UNSAT): 25968(2079/23889)
May 24, 2018 12:47:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(197/420) took 244996 ms. Total solver calls (SAT/UNSAT): 26343(2107/24236)
May 24, 2018 12:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(UNSAT) depth K=4 took 20663 ms
May 24, 2018 12:47:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(203/420) took 248063 ms. Total solver calls (SAT/UNSAT): 26682(2130/24552)
May 24, 2018 12:47:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(210/420) took 251408 ms. Total solver calls (SAT/UNSAT): 27032(2150/24882)
May 24, 2018 12:47:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(218/420) took 254514 ms. Total solver calls (SAT/UNSAT): 27372(2164/25208)
May 24, 2018 12:47:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(227/420) took 257648 ms. Total solver calls (SAT/UNSAT): 27682(2175/25507)
May 24, 2018 12:47:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(237/420) took 260679 ms. Total solver calls (SAT/UNSAT): 28007(2205/25802)
May 24, 2018 12:47:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(249/420) took 263843 ms. Total solver calls (SAT/UNSAT): 28330(2205/26125)
May 24, 2018 12:47:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(260/420) took 266946 ms. Total solver calls (SAT/UNSAT): 28636(2265/26371)
May 24, 2018 12:47:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(271/420) took 269946 ms. Total solver calls (SAT/UNSAT): 28921(2333/26588)
May 24, 2018 12:47:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(279/420) took 273311 ms. Total solver calls (SAT/UNSAT): 29117(2369/26748)
May 24, 2018 12:47:51 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(291/420) took 276319 ms. Total solver calls (SAT/UNSAT): 29403(2413/26990)
May 24, 2018 12:47:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(302/420) took 279531 ms. Total solver calls (SAT/UNSAT): 29760(2415/27345)
May 24, 2018 12:47:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(306/420) took 282819 ms. Total solver calls (SAT/UNSAT): 30146(2415/27731)
May 24, 2018 12:48:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(310/420) took 286294 ms. Total solver calls (SAT/UNSAT): 30516(2460/28056)
May 24, 2018 12:48:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(314/420) took 289354 ms. Total solver calls (SAT/UNSAT): 30870(2504/28366)
May 24, 2018 12:48:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(319/420) took 293002 ms. Total solver calls (SAT/UNSAT): 31290(2554/28736)
May 24, 2018 12:48:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(324/420) took 296443 ms. Total solver calls (SAT/UNSAT): 31685(2601/29084)
May 24, 2018 12:48:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(329/420) took 299683 ms. Total solver calls (SAT/UNSAT): 32055(2645/29410)
May 24, 2018 12:48:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(334/420) took 302698 ms. Total solver calls (SAT/UNSAT): 32400(2685/29715)
May 24, 2018 12:48:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(340/420) took 306020 ms. Total solver calls (SAT/UNSAT): 32781(2728/30053)
May 24, 2018 12:48:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(346/420) took 309048 ms. Total solver calls (SAT/UNSAT): 33126(2760/30366)
May 24, 2018 12:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-04
May 24, 2018 12:48:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(SAT) depth K=2 took 182782 ms
May 24, 2018 12:48:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(357/420) took 312175 ms. Total solver calls (SAT/UNSAT): 33419(2778/30641)
May 24, 2018 12:48:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(365/420) took 315343 ms. Total solver calls (SAT/UNSAT): 33783(2788/30995)
May 24, 2018 12:48:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(373/420) took 318539 ms. Total solver calls (SAT/UNSAT): 34083(2825/31258)
May 24, 2018 12:48:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(382/420) took 322133 ms. Total solver calls (SAT/UNSAT): 34344(2856/31488)
May 24, 2018 12:48:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(399/420) took 325151 ms. Total solver calls (SAT/UNSAT): 34616(2883/31733)
May 24, 2018 12:48:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 325683 ms. Total solver calls (SAT/UNSAT): 34650(2883/31767)
May 24, 2018 12:48:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 420 transitions.
May 24, 2018 12:48:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 68 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:48:40 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 359604ms conformant to PINS in folder :/home/mcc/execution
May 24, 2018 12:48:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(UNSAT) depth K=4 took 93383 ms
May 24, 2018 12:48:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-06
May 24, 2018 12:48:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(SAT) depth K=2 took 31266 ms
May 24, 2018 12:49:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(UNSAT) depth K=4 took 29593 ms
May 24, 2018 12:50:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-07
May 24, 2018 12:50:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(SAT) depth K=2 took 70402 ms
May 24, 2018 12:50:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(UNSAT) depth K=4 took 43159 ms
May 24, 2018 12:50:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-08
May 24, 2018 12:50:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(SAT) depth K=2 took 24123 ms
May 24, 2018 12:50:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(UNSAT) depth K=4 took 32742 ms
May 24, 2018 12:50:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-09
May 24, 2018 12:50:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(SAT) depth K=2 took 23265 ms
May 24, 2018 12:51:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-13
May 24, 2018 12:51:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(SAT) depth K=2 took 9952 ms
May 24, 2018 12:52:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-00
May 24, 2018 12:52:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(SAT) depth K=3 took 77651 ms
May 24, 2018 12:54:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-01
May 24, 2018 12:54:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(SAT) depth K=3 took 126651 ms
May 24, 2018 12:54:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(UNSAT) depth K=5 took 228225 ms
May 24, 2018 12:57:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-04
May 24, 2018 12:57:55 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(SAT) depth K=3 took 207003 ms
pins2lts-mc, 0.000: Registering PINS so language module
pins2lts-mc, 0.000, ** error **: out of memory trying to get 4294967296
java.lang.RuntimeException: Unexpected exception when executing ltsmin :CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExPT6ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
255
at fr.lip6.move.gal.application.LTSminRunner.checkProperty(LTSminRunner.java:167)
at fr.lip6.move.gal.application.LTSminRunner.access$9(LTSminRunner.java:122)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:91)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 1:04:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-07
May 24, 2018 1:04:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-07(SAT) depth K=3 took 406316 ms
May 24, 2018 1:05:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-08
May 24, 2018 1:05:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-08(SAT) depth K=3 took 53596 ms
May 24, 2018 1:06:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-09
May 24, 2018 1:06:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-09(SAT) depth K=3 took 33574 ms
May 24, 2018 1:06:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-13
May 24, 2018 1:06:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-13(SAT) depth K=3 took 18901 ms
May 24, 2018 1:07:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(UNSAT) depth K=5 took 786617 ms
May 24, 2018 1:11:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-04(UNSAT) depth K=5 took 228903 ms
May 24, 2018 1:12:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-00
May 24, 2018 1:12:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-00(SAT) depth K=4 took 334332 ms
May 24, 2018 1:13:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-06(UNSAT) depth K=5 took 95750 ms
May 24, 2018 1:15:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-6-ReachabilityCardinality-01
May 24, 2018 1:15:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-6-ReachabilityCardinality-01(SAT) depth K=4 took 186666 ms
May 24, 2018 1:18:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 1:18:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-6-ReachabilityCardinality-07 SMT depth 5
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 24, 2018 1:18:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 5
May 24, 2018 1:18:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 5
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 1:18:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-6-ReachabilityCardinality-07 K-induction depth 4
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 24, 2018 1:18:40 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 8/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-6"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-6.tgz
mv LamportFastMutEx-PT-6 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-PT-6, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666475000138"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;