Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................................................
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 7.6K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 34K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 28K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 32K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.1K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 152K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666475000131
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-5-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527165431070

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-00 with value :((!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3)||((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=1)||((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=1))))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-01 with value :((!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=2))||((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))||((((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5)>=1))||((((((((((((((((((((((((((((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_0_3)+P_done_0_4)+P_done_0_5)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_1_3)+P_done_1_4)+P_done_1_5)+P_done_2_0)+P_done_2_1)+P_done_2_2)+P_done_2_3)+P_done_2_4)+P_done_2_5)+P_done_3_0)+P_done_3_1)+P_done_3_2)+P_done_3_3)+P_done_3_4)+P_done_3_5)+P_done_4_0)+P_done_4_1)+P_done_4_2)+P_done_4_3)+P_done_4_4)+P_done_4_5)+P_done_5_0)+P_done_5_1)+P_done_5_2)+P_done_5_3)+P_done_5_4)+P_done_5_5)>=3)))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-02 with value :((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)>=2)
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-03 with value :(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=1)&&(!((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)<=(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5))))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-04 with value :(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)>=1)&&((((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)>=1)&&((((((((((((((((((((((((((((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_0_3)+P_wait_0_4)+P_wait_0_5)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_1_3)+P_wait_1_4)+P_wait_1_5)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)+P_wait_2_3)+P_wait_2_4)+P_wait_2_5)+P_wait_3_0)+P_wait_3_1)+P_wait_3_2)+P_wait_3_3)+P_wait_3_4)+P_wait_3_5)+P_wait_4_0)+P_wait_4_1)+P_wait_4_2)+P_wait_4_3)+P_wait_4_4)+P_wait_4_5)+P_wait_5_0)+P_wait_5_1)+P_wait_5_2)+P_wait_5_3)+P_wait_5_4)+P_wait_5_5)>=1))&&((((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-05 with value :((((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5))&&(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=1)&&((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))))&&((((((((((((P_b_0_false+P_b_0_true)+P_b_1_false)+P_b_1_true)+P_b_2_false)+P_b_2_true)+P_b_3_false)+P_b_3_true)+P_b_4_false)+P_b_4_true)+P_b_5_false)+P_b_5_true)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-06 with value :(!((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)>=1))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-07 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-08 with value :((((P_ifxi_10_5<=x_2)&&(P_wait_4_3>=3))&&((x_2>=1)&&(P_setbi_24_4<=P_wait_1_5)))&&(y_1>=2))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-09 with value :((!((P_done_0_0<=P_setbi_5_2)||(P_setx_3_3>=3)))||(P_done_1_1>=1))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-10 with value :((((P_await_13_1>=3)&&(P_done_5_0<=P_wait_1_0))&&(!(P_b_4_false>=1)))&&((P_start_1_5<=P_wait_4_1)||((P_awaity_5>=2)&&(P_awaity_1>=2))))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-11 with value :(((P_done_1_0>=1)||(P_done_3_0<=P_done_2_0))&&(((P_fordo_12_3<=P_done_1_2)||(P_setbi_11_4<=P_done_3_1))&&(!(P_done_4_0>=1))))
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-12 with value :(((P_wait_2_1>=1)&&((P_wait_3_3<=P_wait_1_3)&&(P_b_2_false<=P_wait_1_5)))||(P_done_0_1>=3))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-13 with value :(P_fordo_12_0<=P_done_2_5)
Read [reachable] property : LamportFastMutEx-PT-5-ReachabilityCardinality-14 with value :((((P_done_3_1>=2)&&(P_done_2_2<=P_done_4_4))&&((P_sety_9_5>=2)||(P_wait_1_1<=P_setbi_24_2)))&&(!((P_await_13_2<=P_wait_5_2)||(P_start_1_2<=P_CS_21_4))))
Read [invariant] property : LamportFastMutEx-PT-5-ReachabilityCardinality-15 with value :(((P_done_5_4>=3)&&(!(P_awaity_3<=P_done_5_5)))||(P_done_0_4<=P_wait_2_4))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :P_wait_1_5 + -1'P_await_13_1 + P_done_1_5 = 0
invariant :P_wait_1_0 + P_done_1_0 = 0
invariant :P_wait_1_3 + -1'P_await_13_1 + P_done_1_3 = 0
invariant :P_wait_2_1 + -1'P_await_13_2 + P_done_2_1 = 0
invariant :P_wait_5_5 + -1'P_await_13_5 + P_done_5_5 = 0
invariant :P_wait_3_5 + -1'P_await_13_3 + P_done_3_5 = 0
invariant :P_wait_0_5 + -1'P_await_13_0 + P_done_0_5 = 0
invariant :P_wait_4_1 + -1'P_await_13_4 + P_done_4_1 = 0
invariant :P_wait_5_1 + -1'P_await_13_5 + P_done_5_1 = 0
invariant :P_wait_1_4 + -1'P_await_13_1 + P_done_1_4 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :P_b_1_false + P_b_1_true = 1
invariant :P_wait_2_4 + -1'P_await_13_2 + P_done_2_4 = 0
invariant :P_wait_3_2 + -1'P_await_13_3 + P_done_3_2 = 0
invariant :P_wait_4_2 + -1'P_await_13_4 + P_done_4_2 = 0
invariant :P_wait_4_5 + -1'P_await_13_4 + P_done_4_5 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :P_wait_5_0 + P_done_5_0 = 0
invariant :P_wait_3_4 + -1'P_await_13_3 + P_done_3_4 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_wait_4_3 + -1'P_await_13_4 + P_done_4_3 = 0
invariant :P_wait_3_3 + -1'P_await_13_3 + P_done_3_3 = 0
invariant :P_wait_5_3 + -1'P_await_13_5 + P_done_5_3 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :P_wait_0_1 + -1'P_await_13_0 + P_done_0_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :P_wait_2_5 + -1'P_await_13_2 + P_done_2_5 = 0
invariant :P_wait_3_0 + P_done_3_0 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :P_b_2_false + P_b_2_true = 1
invariant :P_wait_0_0 + P_done_0_0 = 0
invariant :P_b_5_false + P_b_5_true = 1
invariant :P_wait_1_2 + -1'P_await_13_1 + P_done_1_2 = 0
invariant :P_wait_1_1 + -1'P_await_13_1 + P_done_1_1 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :P_wait_0_3 + -1'P_await_13_0 + P_done_0_3 = 0
invariant :P_wait_4_4 + -1'P_await_13_4 + P_done_4_4 = 0
invariant :P_wait_5_4 + -1'P_await_13_5 + P_done_5_4 = 0
invariant :P_b_4_false + P_b_4_true = 1
invariant :P_wait_3_1 + -1'P_await_13_3 + P_done_3_1 = 0
invariant :P_wait_2_2 + -1'P_await_13_2 + P_done_2_2 = 0
invariant :P_wait_4_0 + P_done_4_0 = 0
invariant :P_wait_0_4 + -1'P_await_13_0 + P_done_0_4 = 0
invariant :P_wait_5_2 + -1'P_await_13_5 + P_done_5_2 = 0
invariant :P_wait_2_0 + P_done_2_0 = 0
invariant :P_b_3_false + P_b_3_true = 1
invariant :P_b_0_false + P_b_0_true = 0
invariant :P_wait_0_2 + -1'P_await_13_0 + P_done_0_2 = 0
invariant :P_wait_2_3 + -1'P_await_13_2 + P_done_2_3 = 0
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-05 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-08 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-10 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-13 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-14 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-15 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_PT\_5\_flat\_flat,5.30682e+08,42.9078,637772,2,90039,5,1.48601e+06,6,0,993,2.14125e+06,0
Total reachable state count : 530682432

Verifying 16 reachability properties.
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-00 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-00,1.86875e+07,43.984,638048,2,79381,6,1.48601e+06,7,0,1155,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-01 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-01 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-01,22505,44.7964,638088,2,10989,7,1.48601e+06,8,0,2667,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-02 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-02,0,44.9162,638152,1,0,7,1.48601e+06,9,0,2678,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-03 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-03,3.24525e+06,45.3443,638152,2,54765,8,1.48601e+06,10,0,2801,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-04 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-04,3.9978e+07,47.6145,638152,2,104840,9,1.48601e+06,11,0,4471,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-05 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-05,0,47.8004,638152,1,0,9,1.48601e+06,12,0,4568,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-06 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-06,1,47.8286,638152,2,175,10,1.48601e+06,13,0,4569,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-07 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-07,1,47.8298,638152,2,175,11,1.48601e+06,14,0,4578,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-08 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-08

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-08,0,47.9076,638152,1,0,11,1.48601e+06,15,0,4592,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-09 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-09,1,47.9116,638152,2,175,12,1.48601e+06,16,0,4602,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-10 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-10,0,48.063,638152,1,0,12,1.48601e+06,17,0,4611,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-11 does not hold.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-11,10097,48.0897,638152,2,1398,13,1.48601e+06,18,0,4633,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-12 is true.
FORMULA LamportFastMutEx-PT-5-ReachabilityCardinality-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-12,185344,48.113,638152,2,1692,14,1.48601e+06,19,0,4646,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-13 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-13,0,48.1945,638152,1,0,14,1.48601e+06,20,0,4651,2.14125e+06,0
Reachability property LamportFastMutEx-PT-5-ReachabilityCardinality-14 does not hold.
No reachable states exhibit your property : LamportFastMutEx-PT-5-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-14,0,48.341,638152,1,0,14,1.48601e+06,21,0,4670,2.14125e+06,0
Invariant property LamportFastMutEx-PT-5-ReachabilityCardinality-15 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-5-ReachabilityCardinality-15,0,48.5343,638152,1,0,14,1.48601e+06,22,0,4685,2.14125e+06,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527165486684

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:37:13 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:37:13 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:37:13 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 98 ms
May 24, 2018 12:37:13 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 174 places.
May 24, 2018 12:37:13 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 318 transitions.
May 24, 2018 12:37:13 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 33 ms
May 24, 2018 12:37:14 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 280 ms
May 24, 2018 12:37:14 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 49 ms
May 24, 2018 12:37:14 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 3 ms
May 24, 2018 12:37:14 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 12:37:14 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 104 ms
May 24, 2018 12:37:15 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
May 24, 2018 12:37:15 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
May 24, 2018 12:37:15 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 89 ms
May 24, 2018 12:37:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1446 ms.
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=0 took 35 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 318 transitions.
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-01(UNSAT) depth K=0 took 88 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=0 took 21 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=0 took 9 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=0 took 15 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=0 took 4 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=0 took 26 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=0 took 8 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 19 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=0 took 59 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=0 took 73 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=0 took 13 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=0 took 6 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=0 took 6 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=1 took 45 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-01(UNSAT) depth K=1 took 32 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=1 took 11 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=1 took 51 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=1 took 55 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=1 took 6 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=1 took 8 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=1 took 45 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=1 took 5 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=1 took 2 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=1 took 2 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=1 took 3 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=1 took 25 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=1 took 21 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=1 took 3 ms
May 24, 2018 12:37:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=1 took 23 ms
May 24, 2018 12:37:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=2 took 659 ms
May 24, 2018 12:37:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-01(UNSAT) depth K=2 took 200 ms
May 24, 2018 12:37:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=2 took 104 ms
May 24, 2018 12:37:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=2 took 62 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=2 took 218 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=2 took 236 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=2 took 132 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=2 took 27 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=2 took 60 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=2 took 157 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=2 took 32 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=2 took 233 ms
May 24, 2018 12:37:18 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 2673 ms
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=2 took 137 ms
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=2 took 117 ms
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=2 took 134 ms
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 4007 ms
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 26 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=2 took 201 ms
May 24, 2018 12:37:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 23 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-00
May 24, 2018 12:37:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(SAT) depth K=0 took 1108 ms
May 24, 2018 12:37:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-01
May 24, 2018 12:37:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-01(SAT) depth K=0 took 2799 ms
May 24, 2018 12:37:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-02
May 24, 2018 12:37:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(SAT) depth K=0 took 408 ms
May 24, 2018 12:37:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-03
May 24, 2018 12:37:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(SAT) depth K=0 took 487 ms
May 24, 2018 12:37:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(UNSAT) depth K=3 took 4252 ms
May 24, 2018 12:37:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-04
May 24, 2018 12:37:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(SAT) depth K=0 took 1042 ms
May 24, 2018 12:37:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-01(UNSAT) depth K=3 took 2445 ms
May 24, 2018 12:37:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(UNSAT) depth K=3 took 1203 ms
May 24, 2018 12:37:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(UNSAT) depth K=3 took 1963 ms
May 24, 2018 12:37:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-05
May 24, 2018 12:37:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-05
May 24, 2018 12:37:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(FALSE) depth K=0 took 4919 ms
May 24, 2018 12:37:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-06
May 24, 2018 12:37:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(SAT) depth K=0 took 594 ms
May 24, 2018 12:37:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-04(UNSAT) depth K=3 took 1003 ms
May 24, 2018 12:37:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-07
May 24, 2018 12:37:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(SAT) depth K=0 took 423 ms
May 24, 2018 12:37:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-08
May 24, 2018 12:37:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-08
May 24, 2018 12:37:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(FALSE) depth K=0 took 326 ms
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-09
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(SAT) depth K=0 took 1004 ms
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-10
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-10
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(FALSE) depth K=0 took 315 ms
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-11
May 24, 2018 12:37:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(SAT) depth K=0 took 464 ms
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-12
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(SAT) depth K=0 took 408 ms
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-PT-5-ReachabilityCardinality-13
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-13
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(TRUE) depth K=0 took 187 ms
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-PT-5-ReachabilityCardinality-14
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-14
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(FALSE) depth K=0 took 143 ms
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-PT-5-ReachabilityCardinality-15
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-PT-5-ReachabilityCardinality-15
May 24, 2018 12:37:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(TRUE) depth K=0 took 263 ms
May 24, 2018 12:37:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-05(UNSAT) depth K=3 took 3651 ms
May 24, 2018 12:37:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-06(UNSAT) depth K=3 took 1528 ms
May 24, 2018 12:37:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-07(UNSAT) depth K=3 took 2297 ms
May 24, 2018 12:37:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-08(UNSAT) depth K=3 took 1623 ms
May 24, 2018 12:37:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-00
May 24, 2018 12:37:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-00(SAT) depth K=1 took 6022 ms
May 24, 2018 12:37:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-09(UNSAT) depth K=3 took 1699 ms
May 24, 2018 12:37:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-10(UNSAT) depth K=3 took 1634 ms
May 24, 2018 12:37:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-11(UNSAT) depth K=3 took 4875 ms
May 24, 2018 12:37:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-12(UNSAT) depth K=3 took 1478 ms
May 24, 2018 12:37:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-13(UNSAT) depth K=3 took 2835 ms
May 24, 2018 12:37:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
May 24, 2018 12:37:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 474 ms. Total solver calls (SAT/UNSAT): 57(0/57)
May 24, 2018 12:37:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-14(UNSAT) depth K=3 took 1720 ms
May 24, 2018 12:37:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-01
May 24, 2018 12:37:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-01(SAT) depth K=1 took 14309 ms
May 24, 2018 12:37:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-15(UNSAT) depth K=3 took 2291 ms
May 24, 2018 12:37:56 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(4/318) took 3504 ms. Total solver calls (SAT/UNSAT): 283(10/273)
May 24, 2018 12:37:59 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/318) took 6659 ms. Total solver calls (SAT/UNSAT): 565(20/545)
May 24, 2018 12:38:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-02
May 24, 2018 12:38:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-02(SAT) depth K=1 took 7730 ms
May 24, 2018 12:38:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-PT-5-ReachabilityCardinality-03
May 24, 2018 12:38:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-PT-5-ReachabilityCardinality-03(SAT) depth K=1 took 2398 ms
May 24, 2018 12:38:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:38:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-5-ReachabilityCardinality-00 SMT depth 4
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 24, 2018 12:38:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
May 24, 2018 12:38:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout.
java.lang.RuntimeException: SMT solver raised an exception or timeout.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:480)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:38:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-PT-5-ReachabilityCardinality-04 K-induction depth 1
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 24, 2018 12:38:06 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 6/ 16 properties. Interrupting other analysis methods.
May 24, 2018 12:38:06 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 51741ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-PT-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666475000131"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;