Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..................
/home/mcc/execution
total 244K
-rw-r--r-- 1 mcc users 4.5K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 28K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 10K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.3K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 24K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 112 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 350 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.5K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 46K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-PT-2, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666474900110
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-2-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527165224782

FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : LamportFastMutEx-PT-2-ReachabilityCardinality-00 with value :(!(((P_awaity_0+P_awaity_1)+P_awaity_2)<=((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)))
Read [reachable] property : LamportFastMutEx-PT-2-ReachabilityCardinality-01 with value :(((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)>=1)
Read [invariant] property : LamportFastMutEx-PT-2-ReachabilityCardinality-03 with value :(((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)<=((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2))
Read [reachable] property : LamportFastMutEx-PT-2-ReachabilityCardinality-05 with value :(!(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)>=1)||(((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_2_0)+P_done_2_1)+P_done_2_2)>=1))||((((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)<=((P_sety_9_0+P_sety_9_1)+P_sety_9_2))||(((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)<=((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)))))
Read [invariant] property : LamportFastMutEx-PT-2-ReachabilityCardinality-06 with value :((((((((((P_done_0_0+P_done_0_1)+P_done_0_2)+P_done_1_0)+P_done_1_1)+P_done_1_2)+P_done_2_0)+P_done_2_1)+P_done_2_2)>=3)||(((((((((P_wait_0_0+P_wait_0_1)+P_wait_0_2)+P_wait_1_0)+P_wait_1_1)+P_wait_1_2)+P_wait_2_0)+P_wait_2_1)+P_wait_2_2)<=((P_start_1_0+P_start_1_1)+P_start_1_2)))
Read [reachable] property : LamportFastMutEx-PT-2-ReachabilityCardinality-08 with value :((P_setx_3_1<=P_awaity_1)&&((!(P_ifyi_15_2<=P_wait_0_2))&&(P_wait_1_1<=P_done_0_2)))
Read [reachable] property : LamportFastMutEx-PT-2-ReachabilityCardinality-15 with value :((!((P_done_0_1<=y_1)||(P_wait_1_1>=1)))&&(!((P_wait_0_0>=2)||(P_b_0_false<=P_done_1_0))))
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_PT\_2\_flat\_flat,380,0.052798,4620,2,462,5,1999,6,0,363,2085,0
Total reachable state count : 380

Verifying 7 reachability properties.
Reachability property LamportFastMutEx-PT-2-ReachabilityCardinality-00 is true.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-00,1,0.053694,4648,2,70,6,1999,7,0,373,2085,0
Reachability property LamportFastMutEx-PT-2-ReachabilityCardinality-01 is true.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-01,1,0.054986,4784,2,70,7,1999,8,0,387,2085,0
Invariant property LamportFastMutEx-PT-2-ReachabilityCardinality-03 does not hold.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-03,1,0.055991,4952,2,70,8,1999,9,0,403,2085,0
Reachability property LamportFastMutEx-PT-2-ReachabilityCardinality-05 is true.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-05,1,0.061349,5016,2,70,9,1999,10,0,485,2085,0
Invariant property LamportFastMutEx-PT-2-ReachabilityCardinality-06 does not hold.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-06,1,0.063157,5016,2,70,9,1999,11,0,519,2085,0
Reachability property LamportFastMutEx-PT-2-ReachabilityCardinality-08 is true.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-08,10,0.063957,5016,2,130,10,1999,12,0,537,2085,0
Reachability property LamportFastMutEx-PT-2-ReachabilityCardinality-15 does not hold.
FORMULA LamportFastMutEx-PT-2-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : LamportFastMutEx-PT-2-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-PT-2-ReachabilityCardinality-15,0,0.065207,5016,1,0,10,1999,13,0,546,2085,0
WARNING : LTS min runner thread failed on error :java.lang.RuntimeException: Could not set logic :(error "Error writing to Z3 solver: java.io.IOException: Stream closed")

BK_STOP 1527165228111

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:33:46 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:33:46 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:33:46 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 49 ms
May 24, 2018 12:33:46 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 69 places.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 96 transitions.
May 24, 2018 12:33:47 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 23 ms
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Invariant property LamportFastMutEx-PT-2-ReachabilityCardinality-02 is trivially false : it is not verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property LamportFastMutEx-PT-2-ReachabilityCardinality-04 is trivially true : it is verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property LamportFastMutEx-PT-2-ReachabilityCardinality-07 is trivially true : it is verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property LamportFastMutEx-PT-2-ReachabilityCardinality-09 is trivially true : it is verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Invariant property LamportFastMutEx-PT-2-ReachabilityCardinality-10 is trivially false : it is not verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property LamportFastMutEx-PT-2-ReachabilityCardinality-11 is trivially true : it is verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property LamportFastMutEx-PT-2-ReachabilityCardinality-12 is trivially true : it is verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property LamportFastMutEx-PT-2-ReachabilityCardinality-13 is trivially true : it is verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Invariant property LamportFastMutEx-PT-2-ReachabilityCardinality-14 is trivially false : it is not verified in initial state.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 68 ms
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 20 ms
May 24, 2018 12:33:47 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 3 ms
May 24, 2018 12:33:47 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 0 ms
May 24, 2018 12:33:47 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 19 ms
java.lang.RuntimeException: Could not set logic :(error "Error writing to Z3 solver: java.io.IOException: Stream closed")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.startSolver(NextBMCSolver.java:115)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.initSolver(Gal2PinsTransformerNext.java:858)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:70)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:33:47 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 96 transitions.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 0 in 283 ms.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 24, 2018 12:33:47 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 7 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-2"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-2.tgz
mv LamportFastMutEx-PT-2 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-PT-2, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666474900110"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;