Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
................................................................
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.4K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 41K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666474900082
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527163701265

12:08:24.003 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
12:08:24.006 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-00 with value :((!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3)||((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=1)||((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=1))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-01 with value :((!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=2))||((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))||((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)>=1))||((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=3)))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-02 with value :((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)>=2)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-03 with value :(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=1)&&(!((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)<=(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-04 with value :(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)>=1)&&((((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)>=1)&&((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)>=1))&&((((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-05 with value :((((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5))&&(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=1)&&((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))))&&((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-06 with value :(!((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)>=1))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-07 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-08 with value :(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((y_0+y_1)+y_2)+y_3)+y_4)+y_5))||(((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3)||(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))||((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-09 with value :((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-10 with value :((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=2)
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-11 with value :(((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5))||((!((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)<=(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)))&&(!((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)<=(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5)))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-12 with value :(!((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-13 with value :((!(((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=2)&&((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)+P_ifxi_10_5)<=(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5))||((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-14 with value :((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)>=2)
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-15 with value :((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=3)&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))&&((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5))))||(!(((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=3)&&((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5)>=3))))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-05 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-08 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-13 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-14 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-15 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 4656 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 87 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
LTSmin run took 1873 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-00 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality01==true], workingDir=/home/mcc/execution]
LTSmin run took 1627 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-01 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
LTSmin run took 2847 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-03 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
LTSmin run took 34927 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-06 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
LTSmin run took 1036 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality09==true], workingDir=/home/mcc/execution]
LTSmin run took 580 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
LTSmin run took 10973 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-10 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality11==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality11==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality12==true], workingDir=/home/mcc/execution]
LTSmin run took 191552 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_COL\_5\_flat\_flat,5.30682e+08,1200.06,8611728,2,811987,5,2.67202e+07,6,0,1013,4.72308e+07,0
Total reachable state count : 530682432

Verifying 16 reachability properties.
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-00 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-00,1,1201.33,8611756,2,175,6,2.67202e+07,7,0,1052,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-01 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-01,22505,1203.73,8611796,2,28090,7,2.67202e+07,8,0,6635,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-02 does not hold.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-5-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-02,0,1205.06,8611860,1,0,7,2.67202e+07,9,0,6646,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-03 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-03,5.27412e+06,1207.48,8611860,2,216736,8,2.67202e+07,10,0,6774,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-04 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-04,3.9978e+07,1254.44,8611860,2,440099,9,2.67202e+07,11,0,25163,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-05 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-5-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-05,0,1259.38,8611860,1,0,9,2.67202e+07,12,0,25285,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-06 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-06,1,1259.54,8611860,2,175,10,2.67202e+07,13,0,25286,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-07 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-07,1,1259.56,8611860,2,175,11,2.67202e+07,14,0,25295,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-08 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-08,0,1263.15,8611860,1,0,11,2.67202e+07,15,0,25356,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-09 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-09,97,1263.17,8611860,2,315,12,2.67202e+07,16,0,25362,4.72308e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-10 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-10,1,1263.18,8611860,2,175,13,2.67202e+07,17,0,25371,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-11 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-11,0,1264.55,8611860,1,0,13,2.67202e+07,18,0,25424,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-12 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-12,1,1264.81,8611860,2,175,14,2.67202e+07,19,0,25436,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-13 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-13,0,1267.31,8611860,1,0,14,2.67202e+07,20,0,25478,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-14 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-14,0,1268.81,8611860,1,0,14,2.67202e+07,21,0,25498,4.72308e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-15 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-15,0,1272.38,8611860,1,0,14,2.67202e+07,22,0,25651,4.72308e+07,0
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527165001029

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:08:23 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:08:23 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:08:23 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 24, 2018 12:08:24 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1078 ms
May 24, 2018 12:08:24 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
May 24, 2018 12:08:24 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 24, 2018 12:08:24 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

May 24, 2018 12:08:24 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
May 24, 2018 12:08:24 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 24, 2018 12:08:24 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 7 ms
May 24, 2018 12:08:24 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
May 24, 2018 12:08:24 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
May 24, 2018 12:08:24 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 13.0 instantiations of transitions. Total transitions/syncs built is 317
May 24, 2018 12:08:24 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 98 ms
May 24, 2018 12:08:25 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 36 ms
May 24, 2018 12:08:25 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 10 ms
May 24, 2018 12:08:25 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 12:08:25 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 46 ms
May 24, 2018 12:08:25 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 66 transitions. Expanding to a total of 383 deterministic transitions.
May 24, 2018 12:08:25 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 4 ms.
May 24, 2018 12:08:25 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 66 transitions. Expanding to a total of 383 deterministic transitions.
May 24, 2018 12:08:25 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 5 ms.
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 91 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 581 ms.
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=0 took 26 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=0 took 21 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=0 took 16 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 66 transitions. Expanding to a total of 383 deterministic transitions.
May 24, 2018 12:08:26 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 1 ms.
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=0 took 13 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=0 took 18 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=0 took 56 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=0 took 4 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=0 took 11 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=0 took 3 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=0 took 1 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=0 took 12 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=0 took 1 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=0 took 2 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=1 took 32 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=1 took 32 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=1 took 4 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=1 took 21 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=1 took 19 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=1 took 6 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=1 took 6 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 38 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=1 took 14 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=1 took 12 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=1 took 17 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=1 took 13 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=1 took 16 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=1 took 24 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=1 took 11 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=1 took 11 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=1 took 22 ms
May 24, 2018 12:08:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=2 took 243 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=2 took 129 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=2 took 101 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=2 took 129 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=2 took 129 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=2 took 109 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=2 took 36 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=2 took 83 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=2 took 107 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=2 took 56 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=2 took 70 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=2 took 34 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 1883 ms
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 30 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 9 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:08:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=2 took 76 ms
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=2 took 49 ms
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 1545 ms
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=2 took 200 ms
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=2 took 99 ms
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=0 took 473 ms
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 24, 2018 12:08:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=0 took 226 ms
May 24, 2018 12:08:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 24, 2018 12:08:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=0 took 341 ms
May 24, 2018 12:08:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 24, 2018 12:08:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=0 took 809 ms
May 24, 2018 12:08:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 24, 2018 12:08:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=0 took 487 ms
May 24, 2018 12:08:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=3 took 2604 ms
May 24, 2018 12:08:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=3 took 4047 ms
May 24, 2018 12:08:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-5-ReachabilityCardinality-05
May 24, 2018 12:08:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-05
May 24, 2018 12:08:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(FALSE) depth K=0 took 4637 ms
May 24, 2018 12:08:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 24, 2018 12:08:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=0 took 197 ms
May 24, 2018 12:08:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=3 took 477 ms
May 24, 2018 12:08:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 24, 2018 12:08:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=0 took 1281 ms
May 24, 2018 12:08:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-08
May 24, 2018 12:08:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-08
May 24, 2018 12:08:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(TRUE) depth K=0 took 356 ms
May 24, 2018 12:08:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=3 took 1749 ms
May 24, 2018 12:08:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=3 took 672 ms
May 24, 2018 12:08:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 24, 2018 12:08:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=0 took 3300 ms
May 24, 2018 12:08:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=3 took 2601 ms
May 24, 2018 12:08:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 24, 2018 12:08:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=0 took 402 ms
May 24, 2018 12:08:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=3 took 431 ms
May 24, 2018 12:08:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=3 took 369 ms
May 24, 2018 12:08:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=3 took 2213 ms
May 24, 2018 12:08:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=3 took 387 ms
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=0 took 3637 ms
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=3 took 505 ms
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=0 took 285 ms
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-13
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-13
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(TRUE) depth K=0 took 281 ms
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-14
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-14
May 24, 2018 12:08:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(TRUE) depth K=0 took 214 ms
May 24, 2018 12:08:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant LamportFastMutEx-COL-5-ReachabilityCardinality-15
May 24, 2018 12:08:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-5-ReachabilityCardinality-15
May 24, 2018 12:08:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(TRUE) depth K=0 took 1379 ms
May 24, 2018 12:08:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=3 took 3811 ms
May 24, 2018 12:08:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 24, 2018 12:08:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=1 took 2800 ms
May 24, 2018 12:08:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=3 took 4646 ms
May 24, 2018 12:08:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=3 took 979 ms
May 24, 2018 12:08:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=3 took 4643 ms
May 24, 2018 12:08:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 24, 2018 12:08:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=1 took 10588 ms
May 24, 2018 12:09:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=3 took 2148 ms
May 24, 2018 12:09:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
May 24, 2018 12:09:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 24, 2018 12:09:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=1 took 7223 ms
May 24, 2018 12:09:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 641 ms. Total solver calls (SAT/UNSAT): 57(0/57)
May 24, 2018 12:09:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/318) took 3959 ms. Total solver calls (SAT/UNSAT): 342(25/317)
May 24, 2018 12:09:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 24, 2018 12:09:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=1 took 4211 ms
May 24, 2018 12:09:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(11/318) took 7422 ms. Total solver calls (SAT/UNSAT): 678(25/653)
May 24, 2018 12:09:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 24, 2018 12:09:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=1 took 4999 ms
May 24, 2018 12:09:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/318) took 11206 ms. Total solver calls (SAT/UNSAT): 1112(49/1063)
May 24, 2018 12:09:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 24, 2018 12:09:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=1 took 3523 ms
May 24, 2018 12:09:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(18/318) took 15574 ms. Total solver calls (SAT/UNSAT): 1427(60/1367)
May 24, 2018 12:09:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 24, 2018 12:09:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=1 took 3786 ms
May 24, 2018 12:09:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=4 took 23585 ms
May 24, 2018 12:09:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/318) took 19430 ms. Total solver calls (SAT/UNSAT): 1833(90/1743)
May 24, 2018 12:09:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 24, 2018 12:09:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=1 took 4077 ms
May 24, 2018 12:09:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(24/318) took 22586 ms. Total solver calls (SAT/UNSAT): 2030(95/1935)
May 24, 2018 12:09:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 24, 2018 12:09:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=1 took 2316 ms
May 24, 2018 12:09:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 24, 2018 12:09:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=1 took 1540 ms
May 24, 2018 12:09:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 24, 2018 12:09:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=1 took 609 ms
May 24, 2018 12:09:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/318) took 26414 ms. Total solver calls (SAT/UNSAT): 2412(125/2287)
May 24, 2018 12:09:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=4 took 11573 ms
May 24, 2018 12:09:36 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/318) took 29869 ms. Total solver calls (SAT/UNSAT): 2778(147/2631)
May 24, 2018 12:09:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(35/318) took 33429 ms. Total solver calls (SAT/UNSAT): 3042(165/2877)
May 24, 2018 12:09:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(39/318) took 36464 ms. Total solver calls (SAT/UNSAT): 3380(189/3191)
May 24, 2018 12:09:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/318) took 39477 ms. Total solver calls (SAT/UNSAT): 3702(209/3493)
May 24, 2018 12:09:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 24, 2018 12:09:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=2 took 16437 ms
May 24, 2018 12:09:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(47/318) took 42626 ms. Total solver calls (SAT/UNSAT): 4008(235/3773)
May 24, 2018 12:09:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=4 took 14777 ms
May 24, 2018 12:09:53 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(50/318) took 46761 ms. Total solver calls (SAT/UNSAT): 4512(235/4277)
May 24, 2018 12:09:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(53/318) took 51010 ms. Total solver calls (SAT/UNSAT): 5007(254/4753)
May 24, 2018 12:10:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=4 took 9704 ms
May 24, 2018 12:10:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/318) took 54094 ms. Total solver calls (SAT/UNSAT): 5332(292/5040)
May 24, 2018 12:10:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/318) took 58112 ms. Total solver calls (SAT/UNSAT): 5653(330/5323)
May 24, 2018 12:10:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-01
May 24, 2018 12:10:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(SAT) depth K=2 took 20236 ms
May 24, 2018 12:10:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(60/318) took 62378 ms. Total solver calls (SAT/UNSAT): 6127(384/5743)
May 24, 2018 12:10:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(63/318) took 66537 ms. Total solver calls (SAT/UNSAT): 6592(437/6155)
May 24, 2018 12:10:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 24, 2018 12:10:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=2 took 7244 ms
May 24, 2018 12:10:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/318) took 71153 ms. Total solver calls (SAT/UNSAT): 7048(488/6560)
May 24, 2018 12:10:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(68/318) took 75365 ms. Total solver calls (SAT/UNSAT): 7347(521/6826)
May 24, 2018 12:10:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=4 took 22394 ms
May 24, 2018 12:10:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(71/318) took 81534 ms. Total solver calls (SAT/UNSAT): 7788(569/7219)
May 24, 2018 12:10:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(73/318) took 85485 ms. Total solver calls (SAT/UNSAT): 8077(600/7477)
May 24, 2018 12:10:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 24, 2018 12:10:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=2 took 19656 ms
May 24, 2018 12:10:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(76/318) took 89122 ms. Total solver calls (SAT/UNSAT): 8503(645/7858)
May 24, 2018 12:10:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(82/318) took 92238 ms. Total solver calls (SAT/UNSAT): 8863(680/8183)
May 24, 2018 12:10:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=4 took 17461 ms
May 24, 2018 12:10:42 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(90/318) took 96065 ms. Total solver calls (SAT/UNSAT): 9302(685/8617)
May 24, 2018 12:10:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(93/318) took 99681 ms. Total solver calls (SAT/UNSAT): 9707(754/8953)
May 24, 2018 12:10:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(96/318) took 103887 ms. Total solver calls (SAT/UNSAT): 10103(795/9308)
May 24, 2018 12:10:51 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=4 took 11822 ms
May 24, 2018 12:10:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(98/318) took 108293 ms. Total solver calls (SAT/UNSAT): 10362(832/9530)
May 24, 2018 12:10:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/318) took 111569 ms. Total solver calls (SAT/UNSAT): 10743(880/9863)
May 24, 2018 12:11:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(104/318) took 114716 ms. Total solver calls (SAT/UNSAT): 11115(880/10235)
May 24, 2018 12:11:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 24, 2018 12:11:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=2 took 26281 ms
May 24, 2018 12:11:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 24, 2018 12:11:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=2 took 2137 ms
May 24, 2018 12:11:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=4 took 13173 ms
May 24, 2018 12:11:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(107/318) took 119977 ms. Total solver calls (SAT/UNSAT): 11478(880/10598)
May 24, 2018 12:11:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(110/318) took 123578 ms. Total solver calls (SAT/UNSAT): 11832(922/10910)
May 24, 2018 12:11:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(114/318) took 127441 ms. Total solver calls (SAT/UNSAT): 12290(977/11313)
May 24, 2018 12:11:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=4 took 9880 ms
May 24, 2018 12:11:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(118/318) took 131357 ms. Total solver calls (SAT/UNSAT): 12732(1029/11703)
May 24, 2018 12:11:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 24, 2018 12:11:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=2 took 15515 ms
May 24, 2018 12:11:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(122/318) took 134961 ms. Total solver calls (SAT/UNSAT): 13158(1078/12080)
May 24, 2018 12:11:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 24, 2018 12:11:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=2 took 2437 ms
May 24, 2018 12:11:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 24, 2018 12:11:23 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=2 took 1283 ms
May 24, 2018 12:11:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(126/318) took 138446 ms. Total solver calls (SAT/UNSAT): 13568(1125/12443)
May 24, 2018 12:11:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(130/318) took 141786 ms. Total solver calls (SAT/UNSAT): 13962(1169/12793)
May 24, 2018 12:11:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=4 took 15036 ms
May 24, 2018 12:11:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(134/318) took 145073 ms. Total solver calls (SAT/UNSAT): 14340(1210/13130)
May 24, 2018 12:11:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(138/318) took 148205 ms. Total solver calls (SAT/UNSAT): 14672(1245/13427)
May 24, 2018 12:11:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(145/318) took 151561 ms. Total solver calls (SAT/UNSAT): 15057(1262/13795)
May 24, 2018 12:11:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(150/318) took 155270 ms. Total solver calls (SAT/UNSAT): 15302(1272/14030)
May 24, 2018 12:11:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=4 took 13316 ms
May 24, 2018 12:11:45 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(153/318) took 158355 ms. Total solver calls (SAT/UNSAT): 15437(1275/14162)
May 24, 2018 12:11:48 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(160/318) took 161789 ms. Total solver calls (SAT/UNSAT): 15717(1292/14425)
May 24, 2018 12:11:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(168/318) took 165873 ms. Total solver calls (SAT/UNSAT): 15977(1305/14672)
May 24, 2018 12:11:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(176/318) took 169005 ms. Total solver calls (SAT/UNSAT): 16206(1330/14876)
May 24, 2018 12:11:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 24, 2018 12:11:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=2 took 33909 ms
May 24, 2018 12:11:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(183/318) took 172129 ms. Total solver calls (SAT/UNSAT): 16378(1330/15048)
May 24, 2018 12:11:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 24, 2018 12:11:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=2 took 2158 ms
May 24, 2018 12:12:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(194/318) took 175450 ms. Total solver calls (SAT/UNSAT): 16649(1346/15303)
May 24, 2018 12:12:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(207/318) took 178494 ms. Total solver calls (SAT/UNSAT): 16949(1410/15539)
May 24, 2018 12:12:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(224/318) took 181621 ms. Total solver calls (SAT/UNSAT): 17283(1450/15833)
May 24, 2018 12:12:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(231/318) took 184721 ms. Total solver calls (SAT/UNSAT): 17618(1450/16168)
May 24, 2018 12:12:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(236/318) took 187802 ms. Total solver calls (SAT/UNSAT): 17958(1487/16471)
May 24, 2018 12:12:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(242/318) took 191013 ms. Total solver calls (SAT/UNSAT): 18333(1538/16795)
May 24, 2018 12:12:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(248/318) took 194746 ms. Total solver calls (SAT/UNSAT): 18672(1583/17089)
May 24, 2018 12:12:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(254/318) took 198147 ms. Total solver calls (SAT/UNSAT): 18975(1622/17353)
May 24, 2018 12:12:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(262/318) took 201251 ms. Total solver calls (SAT/UNSAT): 19323(1660/17663)
May 24, 2018 12:12:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(276/318) took 204301 ms. Total solver calls (SAT/UNSAT): 19663(1669/17994)
May 24, 2018 12:12:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(291/318) took 207366 ms. Total solver calls (SAT/UNSAT): 20008(1715/18293)
May 24, 2018 12:12:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 208525 ms. Total solver calls (SAT/UNSAT): 20133(1725/18408)
May 24, 2018 12:12:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 318 transitions.
May 24, 2018 12:12:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 2914 ms. Total solver calls (SAT/UNSAT): 235(0/235)
May 24, 2018 12:12:38 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 252651ms conformant to PINS in folder :/home/mcc/execution
May 24, 2018 12:13:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-00
May 24, 2018 12:13:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(SAT) depth K=3 took 95203 ms
May 24, 2018 12:13:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 24, 2018 12:13:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=3 took 4416 ms
May 24, 2018 12:14:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-03
May 24, 2018 12:14:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(SAT) depth K=3 took 71474 ms
May 24, 2018 12:15:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=5 took 233281 ms
May 24, 2018 12:15:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 24, 2018 12:15:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=3 took 56599 ms
May 24, 2018 12:17:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-01(UNSAT) depth K=5 took 112886 ms
May 24, 2018 12:18:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-06
May 24, 2018 12:18:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(SAT) depth K=3 took 133917 ms
May 24, 2018 12:18:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=5 took 48007 ms
May 24, 2018 12:18:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-07
May 24, 2018 12:18:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(SAT) depth K=3 took 44825 ms
May 24, 2018 12:19:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=5 took 81029 ms
May 24, 2018 12:20:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-09
May 24, 2018 12:20:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(SAT) depth K=3 took 99802 ms
May 24, 2018 12:20:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-10
May 24, 2018 12:20:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(SAT) depth K=3 took 22138 ms
May 24, 2018 12:20:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=5 took 79732 ms
May 24, 2018 12:21:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-11
May 24, 2018 12:21:38 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(SAT) depth K=3 took 50825 ms
May 24, 2018 12:22:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-12
May 24, 2018 12:22:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(SAT) depth K=3 took 49776 ms
May 24, 2018 12:22:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=5 took 92060 ms
May 24, 2018 12:23:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=5 took 72430 ms
May 24, 2018 12:24:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-02
May 24, 2018 12:24:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(SAT) depth K=4 took 115791 ms
May 24, 2018 12:24:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=5 took 69243 ms
May 24, 2018 12:26:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=5 took 77900 ms
May 24, 2018 12:28:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=5 took 144662 ms
May 24, 2018 12:29:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-5-ReachabilityCardinality-04
May 24, 2018 12:29:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(SAT) depth K=4 took 286843 ms
May 24, 2018 12:29:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=5 took 53487 ms
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-04 SMT depth 6
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 6
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 6
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:30:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-11 K-induction depth 4
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 24, 2018 12:30:00 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 5/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-5.tgz
mv LamportFastMutEx-COL-5 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666474900082"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;