Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......................................................................
/home/mcc/execution
total 212K
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.1K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 113 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 351 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_pt
-rw-r--r-- 1 mcc users 2 May 15 18:50 instance
-rw-r--r-- 1 mcc users 5 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 40K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is LamportFastMutEx-COL-4, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r116-csrt-152666474900075
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-COL-4-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527163253447

12:00:56.195 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
12:00:56.197 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : LamportFastMutEx-COL-4-ReachabilityCardinality-00 with value :((((((y_0+y_1)+y_2)+y_3)+y_4)>=1)&&(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)<=((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4))||(((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)<=((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)))||(((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)<=((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-01 with value :((((((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)>=2)&&(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)>=1))||((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)>=1)&&(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=1)))&&((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=3)||((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)<=((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-02 with value :((!((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)<=((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4))||(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)>=3)))&&(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=1)||(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=3))&&((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)>=1)&&(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)<=((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-03 with value :(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)>=3)
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-04 with value :(((!(((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)<=((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)))||(((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=2))&&((!(((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)>=3))&&(!(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)>=1))))
Read [invariant] property : LamportFastMutEx-COL-4-ReachabilityCardinality-05 with value :(true)
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-06 with value :((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)>=2)&&(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=3))
Read [invariant] property : LamportFastMutEx-COL-4-ReachabilityCardinality-07 with value :(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)<=((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4))
Read [invariant] property : LamportFastMutEx-COL-4-ReachabilityCardinality-08 with value :((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)<=((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4))&&(!((((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)<=((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4))&&(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)>=3))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-09 with value :(((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)>=1)&&(!(((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)<=((((y_0+y_1)+y_2)+y_3)+y_4))))&&((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)>=2)&&(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)<=((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)))&&(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)>=3)))
Read [invariant] property : LamportFastMutEx-COL-4-ReachabilityCardinality-10 with value :((((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)>=3)||(((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)<=((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)))&&(((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)<=((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)))||(((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=2)&&(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=3))||((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)>=2)||(((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)<=((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-11 with value :(!(((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)<=((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4))||(((((x_0+x_1)+x_2)+x_3)+x_4)<=((((y_0+y_1)+y_2)+y_3)+y_4)))||((((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)<=((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4))&&(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)<=(((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-12 with value :(((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)>=2)||(!(((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)>=1)))&&(((((x_0+x_1)+x_2)+x_3)+x_4)>=2))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-13 with value :(false)
Read [invariant] property : LamportFastMutEx-COL-4-ReachabilityCardinality-14 with value :((!(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)>=3))&&((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)>=1)||(!(((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)>=3))))
Read [reachable] property : LamportFastMutEx-COL-4-ReachabilityCardinality-15 with value :((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)<=((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4))&&(((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)>=3)&&(((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)<=((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)))&&((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)>=2)||(((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)>=1))))
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-05 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-13 FALSE TECHNIQUES SAT_SMT TAUTOLOGY
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 185
// Phase 1: matrix 185 rows 135 cols
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :b_8 + b_9 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 = 1
invariant :wait_6 + -1'P_await_13_1 + done_6 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 = 1
invariant :wait_16 + -1'P_await_13_3 + done_16 = 0
invariant :wait_24 + -1'P_await_13_4 + done_24 = 0
invariant :wait_17 + -1'P_await_13_3 + done_17 = 0
invariant :wait_21 + -1'P_await_13_4 + done_21 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_10 + done_10 = 0
invariant :wait_5 + done_5 = 0
invariant :wait_18 + -1'P_await_13_3 + done_18 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :b_2 + b_3 = 1
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :b_0 + b_1 = 0
invariant :wait_12 + -1'P_await_13_2 + done_12 = 0
invariant :wait_11 + -1'P_await_13_2 + done_11 = 0
invariant :wait_20 + done_20 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :wait_0 + done_0 = 0
invariant :wait_23 + -1'P_await_13_4 + done_23 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :b_6 + b_7 = 1
invariant :wait_22 + -1'P_await_13_4 + done_22 = 0
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :b_4 + b_5 = 1
invariant :wait_15 + done_15 = 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 185
// Phase 1: matrix 185 rows 135 cols
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :b_8 + b_9 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 = 1
invariant :wait_6 + -1'P_await_13_1 + done_6 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 = 1
invariant :wait_16 + -1'P_await_13_3 + done_16 = 0
invariant :wait_24 + -1'P_await_13_4 + done_24 = 0
invariant :wait_17 + -1'P_await_13_3 + done_17 = 0
invariant :wait_21 + -1'P_await_13_4 + done_21 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_10 + done_10 = 0
invariant :wait_5 + done_5 = 0
invariant :wait_18 + -1'P_await_13_3 + done_18 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :b_2 + b_3 = 1
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :b_0 + b_1 = 0
invariant :wait_12 + -1'P_await_13_2 + done_12 = 0
invariant :wait_11 + -1'P_await_13_2 + done_11 = 0
invariant :wait_20 + done_20 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :wait_0 + done_0 = 0
invariant :wait_23 + -1'P_await_13_4 + done_23 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :b_6 + b_7 = 1
invariant :wait_22 + -1'P_await_13_4 + done_22 = 0
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :b_4 + b_5 = 1
invariant :wait_15 + done_15 = 0
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-06 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-09 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-11 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-12 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx\_COL\_4\_flat\_flat,1.91478e+06,40.4763,417916,2,67418,5,1.49717e+06,6,0,792,1.81337e+06,0
Total reachable state count : 1914784

Verifying 16 reachability properties.
Invariant property LamportFastMutEx-COL-4-ReachabilityCardinality-00 does not hold.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-00,96,40.7704,418196,2,666,6,1.49717e+06,7,0,986,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-01 is true.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-01,4,40.8055,418300,2,150,7,1.49717e+06,8,0,1045,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-02 is true.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-02,7299,41.1231,418300,2,9485,8,1.49717e+06,9,0,2463,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-03 is true.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-03,1,41.1931,418300,2,136,9,1.49717e+06,10,0,2474,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-04 is true.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-04,1,41.1969,418300,2,136,10,1.49717e+06,11,0,2489,1.81337e+06,0
Invariant property LamportFastMutEx-COL-4-ReachabilityCardinality-05 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-05,0,41.197,418300,1,0,10,1.49717e+06,11,0,2489,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-06 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-4-ReachabilityCardinality-06

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-06,0,41.3501,418300,1,0,10,1.49717e+06,12,0,2513,1.81337e+06,0
Invariant property LamportFastMutEx-COL-4-ReachabilityCardinality-07 does not hold.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-07,3,41.3521,418300,2,141,11,1.49717e+06,13,0,2525,1.81337e+06,0
Invariant property LamportFastMutEx-COL-4-ReachabilityCardinality-08 does not hold.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-08,1,41.3592,418300,2,136,11,1.49717e+06,14,0,2577,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-09 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-4-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-09,0,41.4643,418300,1,0,11,1.49717e+06,15,0,2632,1.81337e+06,0
Invariant property LamportFastMutEx-COL-4-ReachabilityCardinality-10 does not hold.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-10,78672,44.3559,418300,2,43590,12,1.49717e+06,16,0,6239,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-11 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-4-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-11,0,44.6376,418308,1,0,12,1.49717e+06,17,0,6287,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-12 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-4-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-12,0,44.7711,418308,1,0,12,1.49717e+06,18,0,6300,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-13 does not hold.
No reachable states exhibit your property : LamportFastMutEx-COL-4-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-13,0,44.7713,418308,1,0,12,1.49717e+06,18,0,6300,1.81337e+06,0
Invariant property LamportFastMutEx-COL-4-ReachabilityCardinality-14 does not hold.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-14,4,44.7942,418308,2,148,13,1.49717e+06,19,0,6320,1.81337e+06,0
Reachability property LamportFastMutEx-COL-4-ReachabilityCardinality-15 does not hold.
FORMULA LamportFastMutEx-COL-4-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-4-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-4-ReachabilityCardinality-15,0,45.0118,418308,1,0,13,1.49717e+06,20,0,6391,1.81337e+06,0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527163305231

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 24, 2018 12:00:55 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 24, 2018 12:00:55 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 24, 2018 12:00:55 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 24, 2018 12:00:56 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 928 ms
May 24, 2018 12:00:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
May 24, 2018 12:00:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 24, 2018 12:00:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

May 24, 2018 12:00:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
May 24, 2018 12:00:56 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 24, 2018 12:00:56 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 7 ms
May 24, 2018 12:00:56 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
May 24, 2018 12:00:56 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
May 24, 2018 12:00:56 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 11.0 instantiations of transitions. Total transitions/syncs built is 253
May 24, 2018 12:00:56 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 217 ms
May 24, 2018 12:00:57 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 42 ms
May 24, 2018 12:00:57 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 6 ms
May 24, 2018 12:00:57 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 24, 2018 12:00:58 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 23 ms
May 24, 2018 12:00:58 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 69 transitions. Expanding to a total of 298 deterministic transitions.
May 24, 2018 12:00:58 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 69 transitions. Expanding to a total of 298 deterministic transitions.
May 24, 2018 12:00:58 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 10 ms.
May 24, 2018 12:00:58 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 61 ms.
May 24, 2018 12:00:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 2 / 16 in 1483 ms.
May 24, 2018 12:00:59 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 69 transitions. Expanding to a total of 298 deterministic transitions.
May 24, 2018 12:00:59 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 32 ms.
May 24, 2018 12:00:59 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 37 place invariants in 209 ms
May 24, 2018 12:00:59 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 37 place invariants in 61 ms
May 24, 2018 12:00:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(UNSAT) depth K=0 took 388 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(UNSAT) depth K=0 took 126 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(UNSAT) depth K=0 took 25 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-03(UNSAT) depth K=0 took 59 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-04(UNSAT) depth K=0 took 32 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-06(UNSAT) depth K=0 took 6 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-07(UNSAT) depth K=0 took 31 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-08(UNSAT) depth K=0 took 27 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-09(UNSAT) depth K=0 took 7 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-10(UNSAT) depth K=0 took 6 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-11(UNSAT) depth K=0 took 38 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-12(UNSAT) depth K=0 took 25 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-14(UNSAT) depth K=0 took 40 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-15(UNSAT) depth K=0 took 36 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(UNSAT) depth K=1 took 53 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(UNSAT) depth K=1 took 19 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(UNSAT) depth K=1 took 23 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-03(UNSAT) depth K=1 took 20 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-04(UNSAT) depth K=1 took 24 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-06(UNSAT) depth K=1 took 32 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-07(UNSAT) depth K=1 took 2 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-08(UNSAT) depth K=1 took 8 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-09(UNSAT) depth K=1 took 13 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-10(UNSAT) depth K=1 took 10 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-11(UNSAT) depth K=1 took 7 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-12(UNSAT) depth K=1 took 23 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-14(UNSAT) depth K=1 took 14 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-15(UNSAT) depth K=1 took 18 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(UNSAT) depth K=2 took 113 ms
May 24, 2018 12:01:00 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(UNSAT) depth K=2 took 98 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(UNSAT) depth K=2 took 171 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-03(UNSAT) depth K=2 took 126 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-04(UNSAT) depth K=2 took 138 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-06(UNSAT) depth K=2 took 151 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-07(UNSAT) depth K=2 took 63 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-08(UNSAT) depth K=2 took 179 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-09(UNSAT) depth K=2 took 126 ms
May 24, 2018 12:01:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-10(UNSAT) depth K=2 took 75 ms
May 24, 2018 12:01:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-11(UNSAT) depth K=2 took 138 ms
May 24, 2018 12:01:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-12(UNSAT) depth K=2 took 149 ms
May 24, 2018 12:01:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-14(UNSAT) depth K=2 took 128 ms
May 24, 2018 12:01:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-15(UNSAT) depth K=2 took 88 ms
May 24, 2018 12:01:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(UNSAT) depth K=3 took 498 ms
May 24, 2018 12:01:03 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 135 variables to be positive in 3779 ms
May 24, 2018 12:01:03 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(UNSAT) depth K=3 took 854 ms
May 24, 2018 12:01:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-00
May 24, 2018 12:01:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(SAT) depth K=0 took 494 ms
May 24, 2018 12:01:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(UNSAT) depth K=3 took 348 ms
May 24, 2018 12:01:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-01
May 24, 2018 12:01:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(SAT) depth K=0 took 185 ms
May 24, 2018 12:01:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-03(UNSAT) depth K=3 took 788 ms
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-04(UNSAT) depth K=3 took 412 ms
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 135 variables to be positive in 6205 ms
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 230 transitions.
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/230 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 24 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 230 transitions.
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 29 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-02
May 24, 2018 12:01:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(SAT) depth K=0 took 1531 ms
May 24, 2018 12:01:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-03
May 24, 2018 12:01:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-03(SAT) depth K=0 took 195 ms
May 24, 2018 12:01:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-06(UNSAT) depth K=3 took 793 ms
May 24, 2018 12:01:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-04
May 24, 2018 12:01:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-04(SAT) depth K=0 took 403 ms
May 24, 2018 12:01:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-4-ReachabilityCardinality-06
May 24, 2018 12:01:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-4-ReachabilityCardinality-06
May 24, 2018 12:01:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-06(FALSE) depth K=0 took 740 ms
May 24, 2018 12:01:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-07
May 24, 2018 12:01:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-07(SAT) depth K=0 took 941 ms
May 24, 2018 12:01:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-08
May 24, 2018 12:01:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-08(SAT) depth K=0 took 419 ms
May 24, 2018 12:01:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-07(UNSAT) depth K=3 took 3387 ms
May 24, 2018 12:01:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-4-ReachabilityCardinality-09
May 24, 2018 12:01:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-4-ReachabilityCardinality-09
May 24, 2018 12:01:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-09(FALSE) depth K=0 took 1546 ms
May 24, 2018 12:01:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-08(UNSAT) depth K=3 took 1956 ms
May 24, 2018 12:01:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-10
May 24, 2018 12:01:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-10(SAT) depth K=0 took 1779 ms
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-09(UNSAT) depth K=3 took 744 ms
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-4-ReachabilityCardinality-11
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-4-ReachabilityCardinality-11
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-11(FALSE) depth K=0 took 641 ms
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate LamportFastMutEx-COL-4-ReachabilityCardinality-12
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for LamportFastMutEx-COL-4-ReachabilityCardinality-12
May 24, 2018 12:01:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-12(FALSE) depth K=0 took 248 ms
May 24, 2018 12:01:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-14
May 24, 2018 12:01:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-14(SAT) depth K=0 took 437 ms
May 24, 2018 12:01:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-10(UNSAT) depth K=3 took 1571 ms
May 24, 2018 12:01:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-15
May 24, 2018 12:01:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-15(SAT) depth K=0 took 901 ms
May 24, 2018 12:01:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-11(UNSAT) depth K=3 took 415 ms
May 24, 2018 12:01:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-12(UNSAT) depth K=3 took 3243 ms
May 24, 2018 12:01:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-14(UNSAT) depth K=3 took 536 ms
May 24, 2018 12:01:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-15(UNSAT) depth K=3 took 540 ms
May 24, 2018 12:01:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-00
May 24, 2018 12:01:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(SAT) depth K=1 took 4573 ms
May 24, 2018 12:01:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-01
May 24, 2018 12:01:21 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(SAT) depth K=1 took 2522 ms
May 24, 2018 12:01:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-02
May 24, 2018 12:01:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(SAT) depth K=1 took 4955 ms
May 24, 2018 12:01:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-00(UNSAT) depth K=4 took 8171 ms
May 24, 2018 12:01:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-03
May 24, 2018 12:01:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-03(SAT) depth K=1 took 3528 ms
May 24, 2018 12:01:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-04
May 24, 2018 12:01:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-04(SAT) depth K=1 took 2215 ms
May 24, 2018 12:01:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-01(UNSAT) depth K=4 took 5410 ms
May 24, 2018 12:01:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-07
May 24, 2018 12:01:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-07(SAT) depth K=1 took 492 ms
May 24, 2018 12:01:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-08
May 24, 2018 12:01:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-08(SAT) depth K=1 took 1571 ms
May 24, 2018 12:01:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-10
May 24, 2018 12:01:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-10(SAT) depth K=1 took 1279 ms
May 24, 2018 12:01:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-14
May 24, 2018 12:01:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-14(SAT) depth K=1 took 4213 ms
May 24, 2018 12:01:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-02(UNSAT) depth K=4 took 10343 ms
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesLamportFastMutEx-COL-4-ReachabilityCardinality-15
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property LamportFastMutEx-COL-4-ReachabilityCardinality-15(SAT) depth K=1 took 4743 ms
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout.
java.lang.RuntimeException: SMT solver raised an exception or timeout.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeAblingForPredicate(NecessaryEnablingsolver.java:755)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:502)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-4-ReachabilityCardinality-03 SMT depth 4
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
May 24, 2018 12:01:44 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 6/ 16 properties. Interrupting other analysis methods.
May 24, 2018 12:01:44 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 46342ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-4"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-4.tgz
mv LamportFastMutEx-COL-4 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is LamportFastMutEx-COL-4, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r116-csrt-152666474900075"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;