Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................
/home/mcc/execution
total 256K
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 3.3K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 118 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 356 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 4.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 24K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rwxr-xr-x 1 mcc users 79K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is HypertorusGrid-PT-d2k3p2b04, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r104-smll-152658634200146
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HypertorusGrid-PT-d2k3p2b04-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1526803229570

Flatten gal took : 105 ms
Applied a total of 0 rules in 12 ms. Remains 117 /117 variables (removed 0) and now considering 144/144 (removed 0) transitions.
// Phase 1: matrix 144 rows 117 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 144 rows 117 cols
invariant :po_d2_n1_2_3 + pol_d2_n1_2_3 = 1
invariant :pi_d2_n1_3_2 + pil_d2_n1_3_2 = 1
invariant :pi_d1_n1_2_3 + pil_d1_n1_2_3 = 1
invariant :pi_d1_n1_3_1 + pil_d1_n1_3_1 = 1
invariant :pi_d2_n1_2_2 + pil_d2_n1_2_2 = 1
invariant :pi_d1_n1_2_1 + pil_d1_n1_2_1 = 1
invariant :pb_d1_n1_3_1 + pb_d1_n2_3_1 + pb_d2_n1_3_1 + pb_d2_n2_3_1 + pbl_3_1 = 12
invariant :pb_d1_n1_1_3 + pb_d1_n2_1_3 + pb_d2_n1_1_3 + pb_d2_n2_1_3 + pbl_1_3 = 12
invariant :pi_d1_n1_1_2 + pil_d1_n1_1_2 = 1
invariant :pi_d2_n1_2_1 + pil_d2_n1_2_1 = 1
invariant :po_d2_n1_3_3 + pol_d2_n1_3_3 = 1
invariant :po_d2_n1_3_2 + pol_d2_n1_3_2 = 1
invariant :pi_d2_n1_1_1 + pil_d2_n1_1_1 = 1
invariant :pb_d1_n1_2_2 + pb_d1_n2_2_2 + pb_d2_n1_2_2 + pb_d2_n2_2_2 + -1'pbl_1_1 + -1'pbl_1_2 + -1'pbl_1_3 + -1'pbl_2_1 + -1'pbl_2_3 + -1'pbl_3_1 + -1'pbl_3_2 + -1'pbl_3_3 + -1'pil_d1_n1_1_1 + -1'pil_d1_n1_1_2 + -1'pil_d1_n1_1_3 + -1'pil_d1_n1_2_1 + -1'pil_d1_n1_2_2 + -1'pil_d1_n1_2_3 + -1'pil_d1_n1_3_1 + -1'pil_d1_n1_3_2 + -1'pil_d1_n1_3_3 + -1'pil_d2_n1_1_1 + -1'pil_d2_n1_1_2 + -1'pil_d2_n1_1_3 + -1'pil_d2_n1_2_1 + -1'pil_d2_n1_2_2 + -1'pil_d2_n1_2_3 + -1'pil_d2_n1_3_1 + -1'pil_d2_n1_3_2 + -1'pil_d2_n1_3_3 + -1'pol_d1_n1_1_1 + -1'pol_d1_n1_1_2 + -1'pol_d1_n1_1_3 + -1'pol_d1_n1_2_1 + -1'pol_d1_n1_2_2 + -1'pol_d1_n1_2_3 + -1'pol_d1_n1_3_1 + -1'pol_d1_n1_3_2 + -1'pol_d1_n1_3_3 + -1'pol_d2_n1_1_1 + -1'pol_d2_n1_1_2 + -1'pol_d2_n1_1_3 + -1'pol_d2_n1_2_1 + -1'pol_d2_n1_2_2 + -1'pol_d2_n1_2_3 + -1'pol_d2_n1_3_1 + -1'pol_d2_n1_3_2 + -1'pol_d2_n1_3_3 = -60
invariant :po_d1_n1_3_2 + pol_d1_n1_3_2 = 1
invariant :po_d1_n1_2_1 + pol_d1_n1_2_1 = 1
invariant :pb_d1_n1_2_1 + pb_d1_n2_2_1 + pb_d2_n1_2_1 + pb_d2_n2_2_1 + pbl_2_1 = 12
invariant :po_d1_n1_3_3 + pol_d1_n1_3_3 = 1
invariant :pi_d2_n1_1_3 + pil_d2_n1_1_3 = 1
invariant :pi_d1_n1_3_2 + pil_d1_n1_3_2 = 1
invariant :pi_d1_n1_2_2 + pil_d1_n1_2_2 = 1
invariant :po_d2_n1_2_2 + pol_d2_n1_2_2 = 1
invariant :po_d1_n1_2_2 + pol_d1_n1_2_2 = 1
invariant :pb_d1_n1_1_2 + pb_d1_n2_1_2 + pb_d2_n1_1_2 + pb_d2_n2_1_2 + pbl_1_2 = 12
invariant :pi_d2_n1_2_3 + pil_d2_n1_2_3 = 1
invariant :po_d2_n1_1_2 + pol_d2_n1_1_2 = 1
invariant :po_d2_n1_1_3 + pol_d2_n1_1_3 = 1
invariant :pi_d1_n1_1_3 + pil_d1_n1_1_3 = 1
invariant :pi_d2_n1_3_1 + pil_d2_n1_3_1 = 1
invariant :po_d2_n1_1_1 + pol_d2_n1_1_1 = 1
invariant :pb_d1_n1_3_2 + pb_d1_n2_3_2 + pb_d2_n1_3_2 + pb_d2_n2_3_2 + pbl_3_2 = 12
invariant :po_d2_n1_3_1 + pol_d2_n1_3_1 = 1
invariant :po_d2_n1_2_1 + pol_d2_n1_2_1 = 1
invariant :po_d1_n1_1_3 + pol_d1_n1_1_3 = 1
invariant :pi_d2_n1_1_2 + pil_d2_n1_1_2 = 1
invariant :pi_d1_n1_1_1 + pil_d1_n1_1_1 = 1
invariant :po_d1_n1_2_3 + pol_d1_n1_2_3 = 1
invariant :po_d1_n1_3_1 + pol_d1_n1_3_1 = 1
invariant :pbl_1_1 + pbl_1_2 + pbl_1_3 + pbl_2_1 + pbl_2_2 + pbl_2_3 + pbl_3_1 + pbl_3_2 + pbl_3_3 + pil_d1_n1_1_1 + pil_d1_n1_1_2 + pil_d1_n1_1_3 + pil_d1_n1_2_1 + pil_d1_n1_2_2 + pil_d1_n1_2_3 + pil_d1_n1_3_1 + pil_d1_n1_3_2 + pil_d1_n1_3_3 + pil_d2_n1_1_1 + pil_d2_n1_1_2 + pil_d2_n1_1_3 + pil_d2_n1_2_1 + pil_d2_n1_2_2 + pil_d2_n1_2_3 + pil_d2_n1_3_1 + pil_d2_n1_3_2 + pil_d2_n1_3_3 + pol_d1_n1_1_1 + pol_d1_n1_1_2 + pol_d1_n1_1_3 + pol_d1_n1_2_1 + pol_d1_n1_2_2 + pol_d1_n1_2_3 + pol_d1_n1_3_1 + pol_d1_n1_3_2 + pol_d1_n1_3_3 + pol_d2_n1_1_1 + pol_d2_n1_1_2 + pol_d2_n1_1_3 + pol_d2_n1_2_1 + pol_d2_n1_2_2 + pol_d2_n1_2_3 + pol_d2_n1_3_1 + pol_d2_n1_3_2 + pol_d2_n1_3_3 = 72
invariant :pi_d1_n1_3_3 + pil_d1_n1_3_3 = 1
invariant :pi_d2_n1_3_3 + pil_d2_n1_3_3 = 1
invariant :pb_d1_n1_2_3 + pb_d1_n2_2_3 + pb_d2_n1_2_3 + pb_d2_n2_2_3 + pbl_2_3 = 12
invariant :po_d1_n1_1_1 + pol_d1_n1_1_1 = 1
invariant :pb_d1_n1_3_3 + pb_d1_n2_3_3 + pb_d2_n1_3_3 + pb_d2_n2_3_3 + pbl_3_3 = 12
invariant :po_d1_n1_1_2 + pol_d1_n1_1_2 = 1
invariant :pb_d1_n1_1_1 + pb_d1_n2_1_1 + pb_d2_n1_1_1 + pb_d2_n2_1_1 + pbl_1_1 = 12
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 2644 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 44 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,5.47584e+35,908.961,11169384,2,90208,5,6.62387e+07,6,0,615,7.40319e+07,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,5.79395e+11,1278.98,11169700,2,5.78683e+06,7,6.62387e+07,9,1,3544,7.69168e+07,2

System contains 5.79395e+11 deadlocks (shown below if less than --print-limit option) !
FORMULA HypertorusGrid-PT-d2k3p2b04-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
[ 579394654932 states ] showing 10 first states
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=9 pb_d2_n2_1_3=3 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 pol_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n2_2_1=12 pol_d1_n1_3_1=1 pi_d1_n1_3_1=1 pol_d1_n1_1_1=1 pol_d2_n1_1_2=1 pi_d1_n1_2_1=1 pb_d1_n2_1_1=12 pol_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=9 pb_d2_n2_1_3=3 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 pol_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n2_2_1=12 pol_d1_n1_3_1=1 pi_d1_n1_3_1=1 po_d1_n1_1_1=1 pol_d2_n1_1_2=1 pil_d1_n1_2_1=1 pb_d1_n1_1_1=12 pol_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=9 pb_d2_n2_1_3=3 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 pol_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n1_2_1=12 pol_d1_n1_3_1=1 pil_d1_n1_3_1=1 pol_d1_n1_1_1=1 pol_d2_n1_1_2=1 pi_d1_n1_2_1=1 pb_d1_n2_1_1=12 po_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=9 pb_d2_n2_1_3=3 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 pol_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n1_2_1=12 pol_d1_n1_3_1=1 pil_d1_n1_3_1=1 po_d1_n1_1_1=1 pol_d2_n1_1_2=1 pil_d1_n1_2_1=1 pb_d1_n1_1_1=12 po_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=9 pb_d2_n2_1_3=3 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 po_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 pol_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pb_d2_n1_2_1=12 pi_d2_n1_1_1=1 pol_d1_n1_3_1=1 pil_d1_n1_3_1=1 pol_d1_n1_1_1=1 pol_d2_n1_1_2=1 pi_d1_n1_2_1=1 pb_d1_n2_1_1=12 pol_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=9 pb_d2_n2_1_3=3 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 po_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 pol_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pb_d2_n1_2_1=12 pi_d2_n1_1_1=1 pol_d1_n1_3_1=1 pil_d1_n1_3_1=1 po_d1_n1_1_1=1 pol_d2_n1_1_2=1 pil_d1_n1_2_1=1 pb_d1_n1_1_1=12 pol_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=10 pb_d2_n2_1_3=2 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 po_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n2_2_1=12 pol_d1_n1_3_1=1 pi_d1_n1_3_1=1 pol_d1_n1_1_1=1 pol_d2_n1_1_2=1 pi_d1_n1_2_1=1 pb_d1_n2_1_1=12 pol_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=10 pb_d2_n2_1_3=2 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 po_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n2_2_1=12 pol_d1_n1_3_1=1 pi_d1_n1_3_1=1 po_d1_n1_1_1=1 pol_d2_n1_1_2=1 pil_d1_n1_2_1=1 pb_d1_n1_1_1=12 pol_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=10 pb_d2_n2_1_3=2 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 po_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n1_2_1=12 pol_d1_n1_3_1=1 pil_d1_n1_3_1=1 pol_d1_n1_1_1=1 pol_d2_n1_1_2=1 pi_d1_n1_2_1=1 pb_d1_n2_1_1=12 po_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
[ po_d1_n1_1_3=1 pi_d1_n1_3_3=1 po_d1_n1_3_3=1 pil_d2_n1_3_3=1 pb_d2_n2_3_3=12 pil_d1_n1_2_3=1 pil_d1_n1_1_3=1 pol_d1_n1_2_3=1 pb_d2_n2_2_3=12 pil_d2_n1_2_3=1 po_d2_n1_3_1=1 pbl_1_3=10 pb_d2_n2_1_3=2 pil_d2_n1_1_3=1 pol_d2_n1_3_3=1 pol_d2_n1_2_1=1 pol_d2_n1_2_3=1 pol_d1_n1_1_2=1 pbl_3_2=12 pil_d1_n1_3_2=1 pol_d2_n1_1_1=1 pol_d1_n1_3_2=1 pbl_2_2=12 pil_d2_n1_3_2=1 pol_d2_n1_1_3=1 pil_d1_n1_2_2=1 pol_d1_n1_2_2=1 pil_d1_n1_1_2=1 pbl_1_2=12 pil_d2_n1_2_2=1 pi_d2_n1_3_1=1 pil_d2_n1_1_2=1 pi_d2_n1_2_1=1 po_d2_n1_3_2=1 pb_d2_n1_3_1=12 pol_d2_n1_2_2=1 pi_d2_n1_1_1=1 pb_d1_n1_2_1=12 pol_d1_n1_3_1=1 pil_d1_n1_3_1=1 po_d1_n1_1_1=1 pol_d2_n1_1_2=1 pil_d1_n1_2_1=1 pb_d1_n1_1_1=12 po_d1_n1_2_1=1 pil_d1_n1_1_1=1 ]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1526804519222

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 20, 2018 8:00:31 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 20, 2018 8:00:31 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 20, 2018 8:00:32 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 73 ms
May 20, 2018 8:00:32 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 117 places.
May 20, 2018 8:00:32 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 144 transitions.
May 20, 2018 8:00:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 18 ms
May 20, 2018 8:00:32 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 101 ms
May 20, 2018 8:00:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 6 ms
May 20, 2018 8:00:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 144 transitions.
May 20, 2018 8:00:32 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 4 ms
May 20, 2018 8:00:32 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 144 transitions.
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 46 place invariants in 24 ms
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 117 variables to be positive in 269 ms
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 144 transitions.
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/144 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 12 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 144 transitions.
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 11 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 20, 2018 8:00:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 144 transitions.
May 20, 2018 8:00:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(5/144) took 3647 ms. Total solver calls (SAT/UNSAT): 843(837/6)
May 20, 2018 8:00:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(9/144) took 6794 ms. Total solver calls (SAT/UNSAT): 1385(1375/10)
May 20, 2018 8:00:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(15/144) took 10174 ms. Total solver calls (SAT/UNSAT): 2168(2152/16)
May 20, 2018 8:00:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(20/144) took 13377 ms. Total solver calls (SAT/UNSAT): 2793(2772/21)
May 20, 2018 8:00:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(26/144) took 16938 ms. Total solver calls (SAT/UNSAT): 3510(3483/27)
May 20, 2018 8:00:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(32/144) took 20353 ms. Total solver calls (SAT/UNSAT): 4191(4158/33)
May 20, 2018 8:00:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(37/144) took 23410 ms. Total solver calls (SAT/UNSAT): 4731(4693/38)
May 20, 2018 8:01:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/144) took 27045 ms. Total solver calls (SAT/UNSAT): 5346(5302/44)
May 20, 2018 8:01:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(48/144) took 30157 ms. Total solver calls (SAT/UNSAT): 5831(5782/49)
May 20, 2018 8:01:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(55/144) took 33559 ms. Total solver calls (SAT/UNSAT): 6468(6412/56)
May 20, 2018 8:01:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(62/144) took 36729 ms. Total solver calls (SAT/UNSAT): 7056(6993/63)
May 20, 2018 8:01:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(70/144) took 39922 ms. Total solver calls (SAT/UNSAT): 7668(7597/71)
May 20, 2018 8:01:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(79/144) took 43114 ms. Total solver calls (SAT/UNSAT): 8280(8200/80)
May 20, 2018 8:01:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/144) took 46413 ms. Total solver calls (SAT/UNSAT): 8865(8775/90)
May 20, 2018 8:01:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(101/144) took 49470 ms. Total solver calls (SAT/UNSAT): 9435(9333/102)
May 20, 2018 8:01:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(115/144) took 52488 ms. Total solver calls (SAT/UNSAT): 9918(9810/108)
May 20, 2018 8:01:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 54956 ms. Total solver calls (SAT/UNSAT): 10296(10188/108)
May 20, 2018 8:01:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 144 transitions.
May 20, 2018 8:01:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 10731 ms. Total solver calls (SAT/UNSAT): 486(0/486)
May 20, 2018 8:01:39 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 66244ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HypertorusGrid-PT-d2k3p2b04"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/HypertorusGrid-PT-d2k3p2b04.tgz
mv HypertorusGrid-PT-d2k3p2b04 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is HypertorusGrid-PT-d2k3p2b04, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r104-smll-152658634200146"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;