About the Execution of ITS-Tools.L for GlobalResAllocation-PT-03
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
15755.710 | 7735.00 | 21849.00 | 88.50 | TTTTFTFTTTFFFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
...................................................................................................
/home/mcc/execution
total 9.9M
-rw-r--r-- 1 mcc users 5.5K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 350K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.1M May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 14K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 87K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 234K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.0K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 31K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 566K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.8M May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 3 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 5.7M May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is GlobalResAllocation-PT-03, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r093-blw7-152650005700411
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-00
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-01
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-02
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-03
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-04
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-05
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-06
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-07
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-08
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-09
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-10
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-11
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-12
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-13
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-14
FORMULA_NAME GlobalResAllocation-PT-03-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1527467013295
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
its-reach command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : GlobalResAllocation-PT-03-ReachabilityCardinality-02 with value :((((((pr_released_2+pr_released_3)+pr_released_1)<=(((((Resources_1+Resources_2)+Resources_3)+Resources_4)+Resources_5)+Resources_6))&&(((Processes_1+Processes_2)+Processes_3)<=((pr_released_2+pr_released_3)+pr_released_1)))||(((pr_in_2+pr_in_1)+pr_in_3)<=(((((Resources_1+Resources_2)+Resources_3)+Resources_4)+Resources_5)+Resources_6)))||((((((((((((((((((in_critical_s_1_1+in_critical_s_2_1)+in_critical_s_3_1)+in_critical_s_1_2)+in_critical_s_3_2)+in_critical_s_2_2)+in_critical_s_2_3)+in_critical_s_1_3)+in_critical_s_1_4)+in_critical_s_3_3)+in_critical_s_3_4)+in_critical_s_2_4)+in_critical_s_2_5)+in_critical_s_1_5)+in_critical_s_1_6)+in_critical_s_3_5)+in_critical_s_3_6)+in_critical_s_2_6)>=3))
Read [reachable] property : GlobalResAllocation-PT-03-ReachabilityCardinality-06 with value :((!(((pr_released_2+pr_released_3)+pr_released_1)>=3))&&(!(((((((((((((((((((in_critical_s_1_1+in_critical_s_2_1)+in_critical_s_3_1)+in_critical_s_1_2)+in_critical_s_3_2)+in_critical_s_2_2)+in_critical_s_2_3)+in_critical_s_1_3)+in_critical_s_1_4)+in_critical_s_3_3)+in_critical_s_3_4)+in_critical_s_2_4)+in_critical_s_2_5)+in_critical_s_1_5)+in_critical_s_1_6)+in_critical_s_3_5)+in_critical_s_3_6)+in_critical_s_2_6)<=((pr_released_2+pr_released_3)+pr_released_1))||((((((((((((((((((in_critical_s_1_1+in_critical_s_2_1)+in_critical_s_3_1)+in_critical_s_1_2)+in_critical_s_3_2)+in_critical_s_2_2)+in_critical_s_2_3)+in_critical_s_1_3)+in_critical_s_1_4)+in_critical_s_3_3)+in_critical_s_3_4)+in_critical_s_2_4)+in_critical_s_2_5)+in_critical_s_1_5)+in_critical_s_1_6)+in_critical_s_3_5)+in_critical_s_3_6)+in_critical_s_2_6)>=1))))
Read [invariant] property : GlobalResAllocation-PT-03-ReachabilityCardinality-08 with value :(((!(in_critical_s_3_1>=3))||(!(in_critical_s_1_6>=2)))||((in_critical_s_1_4>=3)||((pr_in_1>=1)&&(pr_released_2>=1))))
Read [invariant] property : GlobalResAllocation-PT-03-ReachabilityCardinality-09 with value :(((!(in_critical_s_3_6>=2))&&(!(in_critical_s_1_2>=2)))||((Resources_4>=1)&&(in_critical_s_3_3>=3)))
Read [reachable] property : GlobalResAllocation-PT-03-ReachabilityCardinality-10 with value :(in_critical_s_3_2>=3)
Read [reachable] property : GlobalResAllocation-PT-03-ReachabilityCardinality-11 with value :((((Resources_1>=1)&&(in_critical_s_2_3<=in_critical_s_1_6))||(in_critical_s_2_6>=2))&&((!(in_critical_s_2_1<=Resources_6))&&(!(in_critical_s_3_6>=3))))
Read [reachable] property : GlobalResAllocation-PT-03-ReachabilityCardinality-12 with value :(!((in_critical_s_2_6<=pr_in_2)||((in_critical_s_2_2<=in_critical_s_2_1)||(Resources_5>=2))))
Read [reachable] property : GlobalResAllocation-PT-03-ReachabilityCardinality-13 with value :(Resources_6>=3)
Read [invariant] property : GlobalResAllocation-PT-03-ReachabilityCardinality-14 with value :(!(in_critical_s_3_1>=2))
Read [invariant] property : GlobalResAllocation-PT-03-ReachabilityCardinality-15 with value :((pr_released_1>=1)||(!((Processes_2>=3)&&(in_critical_s_2_5<=pr_released_2))))
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation\_PT\_03\_flat\_flat,6320,1.40943,75680,2,3279,5,30549,6,0,1238,17904,0
Total reachable state count : 6320
Verifying 10 reachability properties.
Invariant property GlobalResAllocation-PT-03-ReachabilityCardinality-02 is true.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-02,0,1.44898,75712,1,0,5,30549,7,0,2046,17904,0
Reachability property GlobalResAllocation-PT-03-ReachabilityCardinality-06 does not hold.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : GlobalResAllocation-PT-03-ReachabilityCardinality-06
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-06,0,1.48266,75944,1,0,5,30549,8,0,2660,17904,0
Invariant property GlobalResAllocation-PT-03-ReachabilityCardinality-08 is true.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-08,0,1.48747,76072,1,0,5,30549,9,0,2670,17904,0
Invariant property GlobalResAllocation-PT-03-ReachabilityCardinality-09 is true.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-09,0,1.48894,76072,1,0,5,30549,10,0,2675,17904,0
Reachability property GlobalResAllocation-PT-03-ReachabilityCardinality-10 does not hold.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : GlobalResAllocation-PT-03-ReachabilityCardinality-10
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-10,0,1.48919,76072,1,0,5,30549,11,0,2676,17904,0
Reachability property GlobalResAllocation-PT-03-ReachabilityCardinality-11 does not hold.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : GlobalResAllocation-PT-03-ReachabilityCardinality-11
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-11,0,1.49285,76072,1,0,5,30549,12,0,2695,17904,0
Reachability property GlobalResAllocation-PT-03-ReachabilityCardinality-12 does not hold.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : GlobalResAllocation-PT-03-ReachabilityCardinality-12
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-12,0,1.49387,76072,1,0,5,30549,13,0,2703,17904,0
Reachability property GlobalResAllocation-PT-03-ReachabilityCardinality-13 does not hold.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : GlobalResAllocation-PT-03-ReachabilityCardinality-13
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-13,0,1.49601,76072,1,0,5,30549,14,0,2703,17904,0
Invariant property GlobalResAllocation-PT-03-ReachabilityCardinality-14 is true.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-14,0,1.49657,76072,1,0,5,30549,15,0,2703,17904,0
Invariant property GlobalResAllocation-PT-03-ReachabilityCardinality-15 is true.
FORMULA GlobalResAllocation-PT-03-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
GlobalResAllocation-PT-03-ReachabilityCardinality-15,0,1.49901,76072,1,0,5,30549,16,0,2712,17904,0
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1527467021030
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 28, 2018 12:23:34 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 28, 2018 12:23:34 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 28, 2018 12:23:35 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 337 ms
May 28, 2018 12:23:35 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 33 places.
May 28, 2018 12:23:35 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 4791 transitions.
May 28, 2018 12:23:37 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1527 ms
May 28, 2018 12:23:38 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1219 ms
May 28, 2018 12:23:38 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 1295 ms
May 28, 2018 12:23:39 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 114 ms
May 28, 2018 12:23:39 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 0 ms
May 28, 2018 12:23:39 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 4791 transitions.
May 28, 2018 12:23:39 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (4791) to apply POR reductions. Disabling POR matrices.
May 28, 2018 12:23:39 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 4791 transitions.
May 28, 2018 12:23:39 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1937ms conformant to PINS in folder :/home/mcc/execution
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.checkProperties(Gal2SMTFrontEnd.java:131)
at fr.lip6.move.gal.application.SMTRunner$2.run(SMTRunner.java:110)
at java.lang.Thread.run(Thread.java:748)
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-PT-03"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-PT-03.tgz
mv GlobalResAllocation-PT-03 execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is GlobalResAllocation-PT-03, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r093-blw7-152650005700411"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;