Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.2K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 9.0K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.2K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 106 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 344 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 325K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DLCround-PT-06a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r069-smll-152649741800047
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-06a-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527244238493

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-00 with value :(((u6.p41>=2)&&((u105.p192>=1)||(u8.p62>=1)))&&((u6.p43==0)||(u57.p144==1)))
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-01 with value :((u26.p113==0)||(u91.p178==1))
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-02 with value :((u6.p42==0)||(u48.p135==1))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-03 with value :((!(((u109.p196==0)||(u83.p170==1))||((u13.p100==0)||(u4.p26==1))))&&((!((u66.p153==0)||(u10.p87==1)))&&(!(u87.p174>=3))))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-04 with value :(((u49.p136>=2)&&((u68.p155>=2)&&((u11.p95==0)||(u2.p11==1))))&&((!(u9.p76>=2))&&(u28.p115>=1)))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-05 with value :(((!((u66.p153==0)||(u3.p21==1)))&&(u97.p184>=2))&&(((u102.p189>=3)||(u34.p121>=3))&&(((u94.p181==0)||(u68.p155==1))&&((u42.p129==0)||(u2.p9==1)))))
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-06 with value :(((u2.p13==0)||(u36.p123==1))||((u65.p152>=1)||(!((u9.p74==0)||(u6.p47==1)))))
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-07 with value :(!((!(u7.p53>=2))&&(((u29.p116==0)||(u56.p143==1))&&(u4.p27>=3))))
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-08 with value :((u18.p105==0)||(u64.p151==1))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-09 with value :(((((u3.p19==0)||(u57.p144==1))||((u24.p111==0)||(u1.p4==1)))&&((u26.p113>=3)&&((u43.p130==0)||(u2.p13==1))))&&((u17.p104==0)||(u65.p152==1)))
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-10 with value :(((!(u83.p170>=2))&&(u5.p33>=2))||(!(((u110.p0==0)||(u1.p6==1))&&(u4.p23>=2))))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-11 with value :(((u4.p26>=2)&&((u33.p120>=1)||((u19.p106==0)||(u62.p149==1))))&&((u28.p115==0)||(u5.p36==1)))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-12 with value :(((((u104.p191==0)||(u106.p193==1))&&((u86.p173==0)||(u10.p86==1)))||((u9.p78>=3)&&(u106.p193>=3)))&&(u9.p69>=2))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-13 with value :(u102.p189>=2)
Read [invariant] property : DLCround-PT-06a-ReachabilityCardinality-14 with value :(!((((u11.p89==0)||(u4.p27==1))||((u6.p44==0)||(u85.p172==1)))&&((u51.p138>=2)&&(u3.p21>=2))))
Read [reachable] property : DLCround-PT-06a-ReachabilityCardinality-15 with value :(u11.p91>=3)
built 197 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 154
// Phase 1: matrix 154 rows 197 cols
invariant :p160 + -1'p196 = 0
invariant :p186 + -1'p196 = 0
invariant :p173 + -1'p196 = 0
invariant :p49 + p50 + p51 + p52 + p53 + p54 + p55 + p56 + p57 + p58 + -1'p196 = 0
invariant :p152 + -1'p196 = 0
invariant :p103 + -1'p196 = 0
invariant :p162 + -1'p196 = 0
invariant :p176 + -1'p196 = 0
invariant :p191 + -1'p196 = 0
invariant :p142 + -1'p196 = 0
invariant :p117 + -1'p196 = 0
invariant :p129 + -1'p196 = 0
invariant :p167 + -1'p196 = 0
invariant :p99 + -1'p196 = 0
invariant :p131 + -1'p196 = 0
invariant :p124 + -1'p196 = 0
invariant :p110 + -1'p196 = 0
invariant :p188 + -1'p196 = 0
invariant :p111 + -1'p196 = 0
invariant :p189 + -1'p196 = 0
invariant :p194 + -1'p196 = 0
invariant :p163 + -1'p196 = 0
invariant :p0 + p196 = 1
invariant :p150 + -1'p196 = 0
invariant :p172 + -1'p196 = 0
invariant :p104 + -1'p196 = 0
invariant :p149 + -1'p196 = 0
invariant :p119 + -1'p196 = 0
invariant :p161 + -1'p196 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p196 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p196 = 0
invariant :p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + -1'p196 = 0
invariant :p123 + -1'p196 = 0
invariant :p120 + -1'p196 = 0
invariant :p146 + -1'p196 = 0
invariant :p105 + -1'p196 = 0
invariant :p155 + -1'p196 = 0
invariant :p102 + -1'p196 = 0
invariant :p130 + -1'p196 = 0
invariant :p183 + -1'p196 = 0
invariant :p127 + -1'p196 = 0
invariant :p116 + -1'p196 = 0
invariant :p138 + -1'p196 = 0
invariant :p121 + -1'p196 = 0
invariant :p181 + -1'p196 = 0
invariant :p174 + -1'p196 = 0
invariant :p89 + p90 + p91 + p92 + p93 + p94 + p95 + p96 + p97 + p98 + -1'p196 = 0
invariant :p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + -1'p196 = 0
invariant :p122 + -1'p196 = 0
invariant :p112 + -1'p196 = 0
invariant :p126 + -1'p196 = 0
invariant :p187 + -1'p196 = 0
invariant :p178 + -1'p196 = 0
invariant :p118 + -1'p196 = 0
invariant :p190 + -1'p196 = 0
invariant :p101 + -1'p196 = 0
invariant :p137 + -1'p196 = 0
invariant :p135 + -1'p196 = 0
invariant :p156 + -1'p196 = 0
invariant :p193 + -1'p196 = 0
invariant :p113 + -1'p196 = 0
invariant :p182 + -1'p196 = 0
invariant :p140 + -1'p196 = 0
invariant :p115 + -1'p196 = 0
invariant :p170 + -1'p196 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p196 = 0
invariant :p192 + -1'p196 = 0
invariant :p147 + -1'p196 = 0
invariant :p148 + -1'p196 = 0
invariant :p153 + -1'p196 = 0
invariant :p133 + -1'p196 = 0
invariant :p158 + -1'p196 = 0
invariant :p132 + -1'p196 = 0
invariant :p114 + -1'p196 = 0
invariant :p144 + -1'p196 = 0
invariant :p145 + -1'p196 = 0
invariant :p109 + -1'p196 = 0
invariant :p143 + -1'p196 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + -1'p196 = 0
invariant :p100 + -1'p196 = 0
invariant :p179 + -1'p196 = 0
invariant :p169 + -1'p196 = 0
invariant :p180 + -1'p196 = 0
invariant :p125 + -1'p196 = 0
invariant :p166 + -1'p196 = 0
invariant :p175 + -1'p196 = 0
invariant :p195 + -1'p196 = 0
invariant :p141 + -1'p196 = 0
invariant :p164 + -1'p196 = 0
invariant :p151 + -1'p196 = 0
invariant :p185 + -1'p196 = 0
invariant :p107 + -1'p196 = 0
invariant :p128 + -1'p196 = 0
invariant :p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + -1'p196 = 0
invariant :p168 + -1'p196 = 0
invariant :p134 + -1'p196 = 0
invariant :p139 + -1'p196 = 0
invariant :p165 + -1'p196 = 0
invariant :p108 + -1'p196 = 0
invariant :p177 + -1'p196 = 0
invariant :p184 + -1'p196 = 0
invariant :p154 + -1'p196 = 0
invariant :p157 + -1'p196 = 0
invariant :p171 + -1'p196 = 0
invariant :p69 + p70 + p71 + p72 + p73 + p74 + p75 + p76 + p77 + p78 + -1'p196 = 0
invariant :p136 + -1'p196 = 0
invariant :p159 + -1'p196 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p196 = 0
invariant :p106 + -1'p196 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_06a\_flat\_flat\_flat\_flat\_mod,2.401e+10,0.488829,8748,226,21,2545,609,1405,2190,68,741,0
Total reachable state count : 24010000001

Verifying 16 reachability properties.
Reachability property DLCround-PT-06a-ReachabilityCardinality-00 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-00

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-00,0,0.49155,8780,1,0,2545,609,1418,2190,74,741,84
Invariant property DLCround-PT-06a-ReachabilityCardinality-01 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-01,0,0.492476,9124,1,0,2545,609,1423,2190,76,741,241
Invariant property DLCround-PT-06a-ReachabilityCardinality-02 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-02,0,0.493287,9124,1,0,2545,609,1427,2190,76,741,271
Reachability property DLCround-PT-06a-ReachabilityCardinality-03 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-03

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-03,0,0.494975,9124,1,0,2545,609,1449,2190,80,741,497
Reachability property DLCround-PT-06a-ReachabilityCardinality-04 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-04

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-04,0,0.496351,9124,1,0,2545,609,1470,2190,87,741,665
Reachability property DLCround-PT-06a-ReachabilityCardinality-05 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-05

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-05,0,0.497803,9124,1,0,2545,609,1493,2190,89,741,665
Invariant property DLCround-PT-06a-ReachabilityCardinality-06 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-06,0,0.500078,9124,1,0,2545,609,1506,2190,93,741,870
Invariant property DLCround-PT-06a-ReachabilityCardinality-07 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-07,0,0.501663,9124,1,0,2545,609,1521,2190,97,741,942
Invariant property DLCround-PT-06a-ReachabilityCardinality-08 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-08,0,0.502543,9124,1,0,2545,609,1525,2190,97,741,1052
Reachability property DLCround-PT-06a-ReachabilityCardinality-09 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-09,0,0.504751,9124,1,0,2545,609,1548,2190,101,741,1365
Invariant property DLCround-PT-06a-ReachabilityCardinality-10 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-10,0,0.506693,9124,1,0,2545,609,1564,2190,103,741,1840
Reachability property DLCround-PT-06a-ReachabilityCardinality-11 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-11,0,0.508727,9124,1,0,2545,609,1580,2190,106,741,1960
Reachability property DLCround-PT-06a-ReachabilityCardinality-12 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-12,0,0.510049,9124,1,0,2545,609,1598,2190,106,741,2062
Reachability property DLCround-PT-06a-ReachabilityCardinality-13 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-13,0,0.510408,9124,1,0,2545,609,1599,2190,106,741,2062
Invariant property DLCround-PT-06a-ReachabilityCardinality-14 is true.
FORMULA DLCround-PT-06a-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-14,0,0.512738,9124,1,0,2545,609,1616,2190,108,741,2232
Reachability property DLCround-PT-06a-ReachabilityCardinality-15 does not hold.
FORMULA DLCround-PT-06a-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-06a-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-06a-ReachabilityCardinality-15,0,0.513146,9124,1,0,2545,609,1618,2190,109,741,2232
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527244244952

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 10:30:40 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 25, 2018 10:30:40 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 10:30:40 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 171 ms
May 25, 2018 10:30:40 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 197 places.
May 25, 2018 10:30:41 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1313 transitions.
May 25, 2018 10:30:41 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 25, 2018 10:30:41 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 49 ms
May 25, 2018 10:30:41 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 390 ms
May 25, 2018 10:30:41 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 25, 2018 10:30:41 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 231 ms
May 25, 2018 10:30:41 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 412 ms
May 25, 2018 10:30:42 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1313 transitions.
May 25, 2018 10:30:42 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1313 transitions.
May 25, 2018 10:30:42 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 343 ms
May 25, 2018 10:30:42 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 25, 2018 10:30:42 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 173 ms
May 25, 2018 10:30:42 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 25, 2018 10:30:42 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 2062 redundant transitions.
May 25, 2018 10:30:42 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 18 ms
May 25, 2018 10:30:42 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 109 place invariants in 85 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1344 ms.
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-00(UNSAT) depth K=0 took 4 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-01(UNSAT) depth K=0 took 0 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-02(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-03(UNSAT) depth K=0 took 8 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-04(UNSAT) depth K=0 took 10 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-05(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-06(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-07(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-08(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1313 transitions.
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-09(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-10(UNSAT) depth K=0 took 19 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-11(UNSAT) depth K=0 took 15 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-12(UNSAT) depth K=0 took 13 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-13(UNSAT) depth K=0 took 16 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-06a-ReachabilityCardinality-14(UNSAT) depth K=0 took 1 ms
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying DLCround-PT-06a-ReachabilityCardinality-15 SMT depth 0
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 0
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 0
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Failed to check-sat")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 10:30:43 AM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (define-fun _enabled__76 ((step Int)) Bool (_enabledsrc__76 (select s step))) with error
May 25, 2018 10:30:43 AM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (define-fun trsrc76 ((src (Array Int Int))(dst (Array Int Int))) Bool (and (_enabledsrc__76 src) (= (store (store src 50 (- (select src 50) 1)) 57 (+ (select src 57) 1)) dst))) with error (error "Error writing to Z3 solver: java.io.IOException: Stream closed")
Exception in thread "Thread-8" java.lang.RuntimeException: Error when declaring system variables to SMT solver.(error "Error writing to Z3 solver: java.io.IOException: Stream closed")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.init(NextBMCSolver.java:93)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:59)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 10:30:43 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 16 properties. Interrupting other analysis methods.
May 25, 2018 10:30:43 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1945ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-06a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-06a.tgz
mv DLCround-PT-06a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DLCround-PT-06a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r069-smll-152649741800047"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;