Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
/home/mcc/execution
total 368K
-rw-r--r-- 1 mcc users 3.1K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.3K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.3K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 106 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 344 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.9K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 200K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is DLCround-PT-04a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r069-smll-152649741700019
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-04a-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1527234535192

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Normalized transition count is 122
// Phase 1: matrix 122 rows 139 cols
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-00 with value :(((((u37.p106==0)||(u49.p118==1))||((u44.p113==0)||(u51.p120==1)))||(!((u22.p91==0)||(u9.p74==1))))||((u65.p134==0)||(u7.p54==1)))
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-01 with value :(((((u65.p134==0)||(u4.p24==1))||((u5.p32==0)||(u5.p33==1)))||(u46.p115>=2))||(((u5.p37>=3)||(u4.p23>=2))||(((u1.p4==0)||(u2.p13==1))||(u49.p118>=1))))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-02 with value :(u7.p50>=3)
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-03 with value :(((u69.p138>=3)||((u4.p25>=1)||(u2.p11>=1)))||(!(((u29.p98==0)||(u9.p74==1))&&(u4.p27>=3))))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-04 with value :(((u5.p35==0)||(u7.p53==1))&&(u8.p67>=3))
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-05 with value :((((u6.p41>=2)&&(u5.p36>=1))||((u24.p93>=3)||((u23.p92==0)||(u58.p127==1))))||(!((u3.p16>=3)||((u6.p39==0)||(u9.p70==1)))))
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-06 with value :(!((u4.p27>=3)&&(!((u4.p25==0)||(u23.p92==1)))))
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-07 with value :(!(u7.p50>=3))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-08 with value :((u8.p63>=3)&&((u38.p107==0)||(u63.p132==1)))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-09 with value :(u5.p34>=3)
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-10 with value :(!((((u5.p32==0)||(u8.p60==1))||(u67.p136>=1))||((u2.p9>=3)||(u1.p7>=3))))
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-11 with value :(!((((u66.p135==0)||(u1.p2==1))&&(u20.p89>=2))&&((u4.p22>=3)&&(u20.p89>=1))))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-12 with value :((u6.p40>=3)||((!((u63.p132==0)||(u23.p92==1)))&&((u7.p52>=3)&&(u18.p87>=1))))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-13 with value :((u4.p23>=2)&&((((u2.p10==0)||(u64.p133==1))&&(u6.p46>=1))&&((u29.p98>=1)||((u6.p43==0)||(u55.p124==1)))))
Read [reachable] property : DLCround-PT-04a-ReachabilityCardinality-14 with value :(((!((u5.p37==0)||(u58.p127==1)))||((u11.p80==0)||(u15.p84==1)))&&((((u41.p110==0)||(u2.p13==1))&&(u28.p97>=3))&&((u14.p83==0)||(u8.p64==1))))
Read [invariant] property : DLCround-PT-04a-ReachabilityCardinality-15 with value :((((u33.p102>=3)||(u6.p39>=2))||(((u6.p45==0)||(u67.p136==1))||(u9.p75>=2)))||(u21.p90>=2))
built 121 ordering constraints for composite.
invariant :p94 + -1'p138 = 0
invariant :p115 + -1'p138 = 0
invariant :p104 + -1'p138 = 0
invariant :p118 + -1'p138 = 0
invariant :p133 + -1'p138 = 0
invariant :p84 + -1'p138 = 0
invariant :p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + -1'p138 = 0
invariant :p109 + -1'p138 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p138 = 0
invariant :p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + -1'p138 = 0
invariant :p131 + -1'p138 = 0
invariant :p105 + -1'p138 = 0
invariant :p136 + -1'p138 = 0
invariant :p92 + -1'p138 = 0
invariant :p114 + -1'p138 = 0
invariant :p91 + -1'p138 = 0
invariant :p102 + -1'p138 = 0
invariant :p128 + -1'p138 = 0
invariant :p117 + -1'p138 = 0
invariant :p137 + -1'p138 = 0
invariant :p93 + -1'p138 = 0
invariant :p106 + -1'p138 = 0
invariant :p83 + -1'p138 = 0
invariant :p107 + -1'p138 = 0
invariant :p110 + -1'p138 = 0
invariant :p127 + -1'p138 = 0
invariant :p81 + -1'p138 = 0
invariant :p126 + -1'p138 = 0
invariant :p96 + -1'p138 = 0
invariant :p119 + -1'p138 = 0
invariant :p99 + -1'p138 = 0
invariant :p113 + -1'p138 = 0
invariant :p101 + -1'p138 = 0
invariant :p135 + -1'p138 = 0
invariant :p98 + -1'p138 = 0
invariant :p124 + -1'p138 = 0
invariant :p82 + -1'p138 = 0
invariant :p112 + -1'p138 = 0
invariant :p95 + -1'p138 = 0
invariant :p134 + -1'p138 = 0
invariant :p90 + -1'p138 = 0
invariant :p89 + -1'p138 = 0
invariant :p100 + -1'p138 = 0
invariant :p85 + -1'p138 = 0
invariant :p86 + -1'p138 = 0
invariant :p87 + -1'p138 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p138 = 0
invariant :p111 + -1'p138 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + -1'p138 = 0
invariant :p121 + -1'p138 = 0
invariant :p49 + p50 + p51 + p52 + p53 + p54 + p55 + p56 + p57 + p58 + -1'p138 = 0
invariant :p122 + -1'p138 = 0
invariant :p108 + -1'p138 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p138 = 0
invariant :p132 + -1'p138 = 0
invariant :p103 + -1'p138 = 0
invariant :p69 + p70 + p71 + p72 + p73 + p74 + p75 + p76 + p77 + p78 + -1'p138 = 0
invariant :p0 + p138 = 1
invariant :p88 + -1'p138 = 0
invariant :p97 + -1'p138 = 0
invariant :p130 + -1'p138 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p138 = 0
invariant :p125 + -1'p138 = 0
invariant :p80 + -1'p138 = 0
invariant :p116 + -1'p138 = 0
invariant :p123 + -1'p138 = 0
invariant :p120 + -1'p138 = 0
invariant :p129 + -1'p138 = 0
invariant :p79 + -1'p138 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_04a\_flat\_flat\_flat\_flat\_mod,2.401e+08,0.176299,6516,146,21,1172,453,883,966,68,621,0
Total reachable state count : 240100001

Verifying 16 reachability properties.
Invariant property DLCround-PT-04a-ReachabilityCardinality-00 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-00,0,0.178208,6896,1,0,1172,453,908,966,75,621,180
Invariant property DLCround-PT-04a-ReachabilityCardinality-01 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-01,0,0.180133,6908,1,0,1172,453,941,966,87,621,350
Reachability property DLCround-PT-04a-ReachabilityCardinality-02 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-02,0,0.180423,6908,1,0,1172,453,943,966,88,621,350
Invariant property DLCround-PT-04a-ReachabilityCardinality-03 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-03,0,0.182224,6908,1,0,1172,453,957,966,91,621,644
Reachability property DLCround-PT-04a-ReachabilityCardinality-04 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-04

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-04,0,0.18273,6908,1,0,1172,453,964,966,92,621,644
Invariant property DLCround-PT-04a-ReachabilityCardinality-05 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-05,0,0.18513,6908,1,0,1172,453,991,966,97,621,850
Invariant property DLCround-PT-04a-ReachabilityCardinality-06 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-06 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-06,0,0.185899,6908,1,0,1172,453,998,966,97,621,868
Invariant property DLCround-PT-04a-ReachabilityCardinality-07 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-07 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-07,0,0.18614,6908,1,0,1172,453,1000,966,98,621,868
Reachability property DLCround-PT-04a-ReachabilityCardinality-08 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-08

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-08,0,0.186801,6908,1,0,1172,453,1007,966,99,621,928
Reachability property DLCround-PT-04a-ReachabilityCardinality-09 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-09,0,0.187103,6908,1,0,1172,453,1009,966,100,621,928
Reachability property DLCround-PT-04a-ReachabilityCardinality-10 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-10,0,0.188636,6908,1,0,1172,453,1020,966,101,621,1086
Invariant property DLCround-PT-04a-ReachabilityCardinality-11 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-11,0,0.190435,6908,1,0,1172,453,1037,966,105,621,1224
Reachability property DLCround-PT-04a-ReachabilityCardinality-12 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-12,0,0.191381,6908,1,0,1172,453,1047,966,105,621,1318
Reachability property DLCround-PT-04a-ReachabilityCardinality-13 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-13,0,0.193215,6908,1,0,1172,453,1065,966,108,621,1520
Reachability property DLCround-PT-04a-ReachabilityCardinality-14 does not hold.
FORMULA DLCround-PT-04a-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-04a-ReachabilityCardinality-14

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-14,0,0.195177,6908,1,0,1172,453,1085,966,110,621,1874
Invariant property DLCround-PT-04a-ReachabilityCardinality-15 is true.
FORMULA DLCround-PT-04a-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-04a-ReachabilityCardinality-15,0,0.196151,6908,1,0,1172,453,1103,966,113,621,2002
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527234542129

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 7:48:57 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 25, 2018 7:48:57 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 7:48:58 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 200 ms
May 25, 2018 7:48:58 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 139 places.
May 25, 2018 7:48:58 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 823 transitions.
May 25, 2018 7:48:58 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 25, 2018 7:48:58 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 45 ms
May 25, 2018 7:48:58 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 280 ms
May 25, 2018 7:48:58 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 25, 2018 7:48:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 408 ms
May 25, 2018 7:48:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 437 ms
May 25, 2018 7:48:59 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 823 transitions.
May 25, 2018 7:48:59 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 823 transitions.
May 25, 2018 7:48:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 389 ms
May 25, 2018 7:48:59 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 25, 2018 7:49:00 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 159 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 25, 2018 7:49:00 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 1216 redundant transitions.
May 25, 2018 7:49:00 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 10 ms
May 25, 2018 7:49:00 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1025 ms.
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-00(UNSAT) depth K=0 took 17 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-01(UNSAT) depth K=0 took 19 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 69 place invariants in 110 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-02(UNSAT) depth K=0 took 17 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-03(UNSAT) depth K=0 took 11 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-04(UNSAT) depth K=0 took 26 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-05(UNSAT) depth K=0 took 16 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 823 transitions.
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-06(UNSAT) depth K=0 took 13 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-07(UNSAT) depth K=0 took 19 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-08(UNSAT) depth K=0 took 11 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-09(UNSAT) depth K=0 took 23 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-10(UNSAT) depth K=0 took 36 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-11(UNSAT) depth K=0 took 22 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-12(UNSAT) depth K=0 took 11 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-13(UNSAT) depth K=0 took 11 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-14(UNSAT) depth K=0 took 15 ms
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-04a-ReachabilityCardinality-15(UNSAT) depth K=0 took 9 ms
Skipping mayMatrices nes/nds SMT assertion produced unexpected response (error "Failed to assert expression: java.io.IOException: Broken pipe (>= (select (select s 0) 23) 0)")
May 25, 2018 7:49:00 AM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (define-fun _enabledsrc__220 ((src (Array Int Int))) Bool (and (>= (select src 57) 1) (>= (select src 124) 1))) with error (error "Error writing to Z3 solver: java.io.IOException: Broken pipe")
java.lang.RuntimeException: SMT assertion produced unexpected response (error "Failed to assert expression: java.io.IOException: Broken pipe (>= (select (select s 0) 23) 0)")
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:102)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
Exception in thread "Thread-8" java.lang.RuntimeException: Error when declaring system variables to SMT solver.(error "Error writing to Z3 solver: java.io.IOException: Broken pipe")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.init(NextBMCSolver.java:93)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:59)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 7:49:00 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 16 properties. Interrupting other analysis methods.
May 25, 2018 7:49:00 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 1693ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-04a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-04a.tgz
mv DLCround-PT-04a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is DLCround-PT-04a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r069-smll-152649741700019"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;