About the Execution of ITS-Tools for DLCround-PT-10a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15752.450 | 10037.00 | 29178.00 | 319.80 | TTFTFTFFFTFFTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 824K
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 7.9K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 106 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 344 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 660K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DLCround-PT-10a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r068-smll-152649741100103
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-10a-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1526691210759
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
its-reach command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-00 with value :((u13.p110==0)||(u178.p301==1))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-01 with value :((u187.p310==0)||(u141.p264==1))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-02 with value :(!(((u98.p221>=1)||((u111.p234==0)||(u70.p193==1)))||(((u7.p55==0)||(u198.p321==1))||(u6.p40>=1))))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-03 with value :((u71.p194==0)||(u141.p264==1))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-04 with value :(((u9.p69>=2)&&((u9.p71>=1)&&(u124.p247>=1)))||(!((u11.p91==0)||(u173.p296==1))))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-05 with value :(!(u10.p82>=2))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-06 with value :((((u15.p136>=3)||((u5.p32==0)||(u10.p80==1)))&&((u8.p66==0)||(u22.p145==1)))||((!(u65.p188>=1))&&((u141.p264>=1)||(u103.p226>=3))))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-07 with value :(((u101.p224==0)||(u1.p5==1))&&((u146.p269>=3)&&(((u110.p233==0)||(u162.p285==1))&&((u178.p301==0)||(u3.p15==1)))))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-08 with value :((u12.p105>=1)&&(!((u1.p1>=2)||((u214.p0==0)||(u180.p303==1)))))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-09 with value :((u8.p59==0)||(u140.p263==1))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-10 with value :((!((u14.p123>=2)||((u51.p174==0)||(u76.p199==1))))&&((u2.p8==0)||(u10.p87==1)))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-11 with value :((!(((u163.p286==0)||(u1.p7==1))||((u57.p180==0)||(u81.p204==1))))&&(((u13.p116>=1)&&((u1.p5==0)||(u2.p12==1)))||((u161.p284>=3)&&(u159.p282>=3))))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-12 with value :((u11.p97==0)||(u146.p269==1))
Read [invariant] property : DLCround-PT-10a-ReachabilityCardinality-13 with value :((!((u9.p77>=1)&&((u8.p67==0)||(u102.p225==1))))||(!(((u8.p62==0)||(u2.p14==1))&&((u180.p303==0)||(u8.p63==1)))))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-14 with value :((u105.p228>=2)&&(!(((u49.p172==0)||(u76.p199==1))&&((u2.p11==0)||(u13.p111==1)))))
Read [reachable] property : DLCround-PT-10a-ReachabilityCardinality-15 with value :((u79.p202>=2)&&(u159.p282>=2))
built 397 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 218
// Phase 1: matrix 218 rows 337 cols
invariant :p230 + -1'p336 = 0
invariant :p246 + -1'p336 = 0
invariant :p265 + -1'p336 = 0
invariant :p259 + -1'p336 = 0
invariant :p204 + -1'p336 = 0
invariant :p263 + -1'p336 = 0
invariant :p216 + -1'p336 = 0
invariant :p159 + -1'p336 = 0
invariant :p236 + -1'p336 = 0
invariant :p288 + -1'p336 = 0
invariant :p317 + -1'p336 = 0
invariant :p199 + -1'p336 = 0
invariant :p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + -1'p336 = 0
invariant :p224 + -1'p336 = 0
invariant :p155 + -1'p336 = 0
invariant :p168 + -1'p336 = 0
invariant :p143 + -1'p336 = 0
invariant :p160 + -1'p336 = 0
invariant :p313 + -1'p336 = 0
invariant :p296 + -1'p336 = 0
invariant :p163 + -1'p336 = 0
invariant :p174 + -1'p336 = 0
invariant :p302 + -1'p336 = 0
invariant :p211 + -1'p336 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p336 = 0
invariant :p274 + -1'p336 = 0
invariant :p287 + -1'p336 = 0
invariant :p223 + -1'p336 = 0
invariant :p180 + -1'p336 = 0
invariant :p250 + -1'p336 = 0
invariant :p329 + -1'p336 = 0
invariant :p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + -1'p336 = 0
invariant :p272 + -1'p336 = 0
invariant :p154 + -1'p336 = 0
invariant :p208 + -1'p336 = 0
invariant :p284 + -1'p336 = 0
invariant :p151 + -1'p336 = 0
invariant :p283 + -1'p336 = 0
invariant :p290 + -1'p336 = 0
invariant :p240 + -1'p336 = 0
invariant :p214 + -1'p336 = 0
invariant :p262 + -1'p336 = 0
invariant :p266 + -1'p336 = 0
invariant :p156 + -1'p336 = 0
invariant :p335 + -1'p336 = 0
invariant :p186 + -1'p336 = 0
invariant :p301 + -1'p336 = 0
invariant :p129 + p130 + p131 + p132 + p133 + p134 + p135 + p136 + p137 + p138 + -1'p336 = 0
invariant :p181 + -1'p336 = 0
invariant :p196 + -1'p336 = 0
invariant :p227 + -1'p336 = 0
invariant :p304 + -1'p336 = 0
invariant :p176 + -1'p336 = 0
invariant :p165 + -1'p336 = 0
invariant :p229 + -1'p336 = 0
invariant :p279 + -1'p336 = 0
invariant :p264 + -1'p336 = 0
invariant :p248 + -1'p336 = 0
invariant :p215 + -1'p336 = 0
invariant :p242 + -1'p336 = 0
invariant :p99 + p100 + p101 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + -1'p336 = 0
invariant :p245 + -1'p336 = 0
invariant :p189 + -1'p336 = 0
invariant :p144 + -1'p336 = 0
invariant :p69 + p70 + p71 + p72 + p73 + p74 + p75 + p76 + p77 + p78 + -1'p336 = 0
invariant :p238 + -1'p336 = 0
invariant :p221 + -1'p336 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p336 = 0
invariant :p157 + -1'p336 = 0
invariant :p177 + -1'p336 = 0
invariant :p209 + -1'p336 = 0
invariant :p299 + -1'p336 = 0
invariant :p172 + -1'p336 = 0
invariant :p220 + -1'p336 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + -1'p336 = 0
invariant :p148 + -1'p336 = 0
invariant :p244 + -1'p336 = 0
invariant :p203 + -1'p336 = 0
invariant :p0 + p336 = 1
invariant :p330 + -1'p336 = 0
invariant :p178 + -1'p336 = 0
invariant :p241 + -1'p336 = 0
invariant :p145 + -1'p336 = 0
invariant :p333 + -1'p336 = 0
invariant :p253 + -1'p336 = 0
invariant :p322 + -1'p336 = 0
invariant :p140 + -1'p336 = 0
invariant :p316 + -1'p336 = 0
invariant :p331 + -1'p336 = 0
invariant :p166 + -1'p336 = 0
invariant :p169 + -1'p336 = 0
invariant :p167 + -1'p336 = 0
invariant :p310 + -1'p336 = 0
invariant :p307 + -1'p336 = 0
invariant :p217 + -1'p336 = 0
invariant :p271 + -1'p336 = 0
invariant :p153 + -1'p336 = 0
invariant :p293 + -1'p336 = 0
invariant :p233 + -1'p336 = 0
invariant :p251 + -1'p336 = 0
invariant :p273 + -1'p336 = 0
invariant :p298 + -1'p336 = 0
invariant :p207 + -1'p336 = 0
invariant :p285 + -1'p336 = 0
invariant :p164 + -1'p336 = 0
invariant :p309 + -1'p336 = 0
invariant :p179 + -1'p336 = 0
invariant :p252 + -1'p336 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p336 = 0
invariant :p281 + -1'p336 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p336 = 0
invariant :p162 + -1'p336 = 0
invariant :p325 + -1'p336 = 0
invariant :p231 + -1'p336 = 0
invariant :p305 + -1'p336 = 0
invariant :p332 + -1'p336 = 0
invariant :p228 + -1'p336 = 0
invariant :p146 + -1'p336 = 0
invariant :p218 + -1'p336 = 0
invariant :p192 + -1'p336 = 0
invariant :p147 + -1'p336 = 0
invariant :p232 + -1'p336 = 0
invariant :p195 + -1'p336 = 0
invariant :p295 + -1'p336 = 0
invariant :p182 + -1'p336 = 0
invariant :p294 + -1'p336 = 0
invariant :p297 + -1'p336 = 0
invariant :p323 + -1'p336 = 0
invariant :p267 + -1'p336 = 0
invariant :p173 + -1'p336 = 0
invariant :p205 + -1'p336 = 0
invariant :p256 + -1'p336 = 0
invariant :p193 + -1'p336 = 0
invariant :p194 + -1'p336 = 0
invariant :p202 + -1'p336 = 0
invariant :p212 + -1'p336 = 0
invariant :p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + -1'p336 = 0
invariant :p161 + -1'p336 = 0
invariant :p237 + -1'p336 = 0
invariant :p141 + -1'p336 = 0
invariant :p225 + -1'p336 = 0
invariant :p320 + -1'p336 = 0
invariant :p150 + -1'p336 = 0
invariant :p183 + -1'p336 = 0
invariant :p234 + -1'p336 = 0
invariant :p326 + -1'p336 = 0
invariant :p275 + -1'p336 = 0
invariant :p280 + -1'p336 = 0
invariant :p282 + -1'p336 = 0
invariant :p255 + -1'p336 = 0
invariant :p257 + -1'p336 = 0
invariant :p269 + -1'p336 = 0
invariant :p308 + -1'p336 = 0
invariant :p171 + -1'p336 = 0
invariant :p142 + -1'p336 = 0
invariant :p152 + -1'p336 = 0
invariant :p49 + p50 + p51 + p52 + p53 + p54 + p55 + p56 + p57 + p58 + -1'p336 = 0
invariant :p334 + -1'p336 = 0
invariant :p219 + -1'p336 = 0
invariant :p319 + -1'p336 = 0
invariant :p191 + -1'p336 = 0
invariant :p158 + -1'p336 = 0
invariant :p318 + -1'p336 = 0
invariant :p258 + -1'p336 = 0
invariant :p289 + -1'p336 = 0
invariant :p315 + -1'p336 = 0
invariant :p109 + p110 + p111 + p112 + p113 + p114 + p115 + p116 + p117 + p118 + -1'p336 = 0
invariant :p187 + -1'p336 = 0
invariant :p197 + -1'p336 = 0
invariant :p89 + p90 + p91 + p92 + p93 + p94 + p95 + p96 + p97 + p98 + -1'p336 = 0
invariant :p175 + -1'p336 = 0
invariant :p213 + -1'p336 = 0
invariant :p291 + -1'p336 = 0
invariant :p139 + -1'p336 = 0
invariant :p247 + -1'p336 = 0
invariant :p268 + -1'p336 = 0
invariant :p149 + -1'p336 = 0
invariant :p119 + p120 + p121 + p122 + p123 + p124 + p125 + p126 + p127 + p128 + -1'p336 = 0
invariant :p206 + -1'p336 = 0
invariant :p324 + -1'p336 = 0
invariant :p270 + -1'p336 = 0
invariant :p188 + -1'p336 = 0
invariant :p235 + -1'p336 = 0
invariant :p311 + -1'p336 = 0
invariant :p198 + -1'p336 = 0
invariant :p276 + -1'p336 = 0
invariant :p278 + -1'p336 = 0
invariant :p261 + -1'p336 = 0
invariant :p321 + -1'p336 = 0
invariant :p314 + -1'p336 = 0
invariant :p312 + -1'p336 = 0
invariant :p327 + -1'p336 = 0
invariant :p306 + -1'p336 = 0
invariant :p226 + -1'p336 = 0
invariant :p300 + -1'p336 = 0
invariant :p277 + -1'p336 = 0
invariant :p292 + -1'p336 = 0
invariant :p184 + -1'p336 = 0
invariant :p243 + -1'p336 = 0
invariant :p185 + -1'p336 = 0
invariant :p200 + -1'p336 = 0
invariant :p201 + -1'p336 = 0
invariant :p260 + -1'p336 = 0
invariant :p190 + -1'p336 = 0
invariant :p210 + -1'p336 = 0
invariant :p239 + -1'p336 = 0
invariant :p170 + -1'p336 = 0
invariant :p286 + -1'p336 = 0
invariant :p328 + -1'p336 = 0
invariant :p303 + -1'p336 = 0
invariant :p222 + -1'p336 = 0
invariant :p254 + -1'p336 = 0
invariant :p249 + -1'p336 = 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_10a\_flat\_flat\_mod,2.401e+14,1.98394,20436,434,21,8041,1017,2785,7381,68,1065,0
Total reachable state count : 240100000000001
Verifying 16 reachability properties.
Invariant property DLCround-PT-10a-ReachabilityCardinality-00 is true.
FORMULA DLCround-PT-10a-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-00,0,1.98617,20464,1,0,8041,1017,2791,7381,73,1065,118
Invariant property DLCround-PT-10a-ReachabilityCardinality-01 is true.
FORMULA DLCround-PT-10a-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-01,0,1.98682,20584,1,0,8041,1017,2796,7381,75,1065,220
Reachability property DLCround-PT-10a-ReachabilityCardinality-02 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-02
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-02,0,1.98864,20584,1,0,8041,1017,2812,7381,78,1065,544
Invariant property DLCround-PT-10a-ReachabilityCardinality-03 is true.
FORMULA DLCround-PT-10a-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-03,0,1.98956,20584,1,0,8041,1017,2815,7381,78,1065,706
Reachability property DLCround-PT-10a-ReachabilityCardinality-04 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-04
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-04,0,1.99077,20584,1,0,8041,1017,2830,7381,83,1065,861
Invariant property DLCround-PT-10a-ReachabilityCardinality-05 is true.
FORMULA DLCround-PT-10a-ReachabilityCardinality-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-05,0,1.99112,20584,1,0,8041,1017,2834,7381,85,1065,861
Invariant property DLCround-PT-10a-ReachabilityCardinality-06 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-06,2.1609e+13,1.99552,20584,221,36,8041,1017,2856,7381,91,1065,1618
Reachability property DLCround-PT-10a-ReachabilityCardinality-07 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-07
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-07,0,1.99754,20584,1,0,8041,1017,2875,7381,92,1065,2098
Reachability property DLCround-PT-10a-ReachabilityCardinality-08 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-08
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-08,0,1.9985,20584,1,0,8041,1017,2886,7381,92,1065,2516
Invariant property DLCround-PT-10a-ReachabilityCardinality-09 is true.
FORMULA DLCround-PT-10a-ReachabilityCardinality-09 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-09,0,1.9995,20584,1,0,8041,1017,2891,7381,94,1065,2662
Reachability property DLCround-PT-10a-ReachabilityCardinality-10 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-10
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-10,0,2.00152,20584,1,0,8041,1017,2903,7381,95,1065,2868
Reachability property DLCround-PT-10a-ReachabilityCardinality-11 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-11
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-11,0,2.00366,20584,1,0,8041,1017,2929,7381,98,1065,3216
Invariant property DLCround-PT-10a-ReachabilityCardinality-12 is true.
FORMULA DLCround-PT-10a-ReachabilityCardinality-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-12,0,2.00441,20584,1,0,8041,1017,2933,7381,99,1065,3306
Invariant property DLCround-PT-10a-ReachabilityCardinality-13 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-13,2.401e+12,2.00845,20584,221,34,8041,1017,2951,7381,102,1065,4167
Reachability property DLCround-PT-10a-ReachabilityCardinality-14 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-14
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-14,0,2.011,20584,1,0,8041,1017,2962,7381,102,1065,4694
Reachability property DLCround-PT-10a-ReachabilityCardinality-15 does not hold.
FORMULA DLCround-PT-10a-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-10a-ReachabilityCardinality-15
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-10a-ReachabilityCardinality-15,0,2.01135,20584,1,0,8041,1017,2966,7381,102,1065,4694
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1526691220796
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 19, 2018 12:53:33 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 19, 2018 12:53:33 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 19, 2018 12:53:33 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 332 ms
May 19, 2018 12:53:33 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 337 places.
May 19, 2018 12:53:34 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2605 transitions.
May 19, 2018 12:53:34 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 19, 2018 12:53:34 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 67 ms
May 19, 2018 12:53:34 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 750 ms
May 19, 2018 12:53:35 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 19, 2018 12:53:35 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 19, 2018 12:53:35 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 538 ms
May 19, 2018 12:53:35 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 455 ms
May 19, 2018 12:53:35 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 19, 2018 12:53:35 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2605 transitions.
May 19, 2018 12:53:35 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (2605) to apply POR reductions. Disabling POR matrices.
May 19, 2018 12:53:35 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2605 transitions.
May 19, 2018 12:53:36 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 902ms conformant to PINS in folder :/home/mcc/execution
May 19, 2018 12:53:36 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 4354 redundant transitions.
May 19, 2018 12:53:36 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 54 ms
May 19, 2018 12:53:36 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1998 ms.
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-00(UNSAT) depth K=0 took 38 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-01(UNSAT) depth K=0 took 17 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-02(UNSAT) depth K=0 took 11 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-03(UNSAT) depth K=0 took 16 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-04(UNSAT) depth K=0 took 15 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-05(UNSAT) depth K=0 took 147 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-06(UNSAT) depth K=0 took 16 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-07(UNSAT) depth K=0 took 15 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-08(UNSAT) depth K=0 took 21 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-09(UNSAT) depth K=0 took 13 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 2605 transitions.
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-10(UNSAT) depth K=0 took 15 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-11(UNSAT) depth K=0 took 16 ms
May 19, 2018 12:53:37 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-12(UNSAT) depth K=0 took 16 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-13(UNSAT) depth K=0 took 23 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-14(UNSAT) depth K=0 took 11 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-15(UNSAT) depth K=0 took 12 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-00(UNSAT) depth K=1 took 21 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-01(UNSAT) depth K=1 took 15 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-02(UNSAT) depth K=1 took 19 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-03(UNSAT) depth K=1 took 11 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-04(UNSAT) depth K=1 took 25 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-05(UNSAT) depth K=1 took 17 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-06(UNSAT) depth K=1 took 9 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-07(UNSAT) depth K=1 took 17 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-08(UNSAT) depth K=1 took 11 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-09(UNSAT) depth K=1 took 16 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-10(UNSAT) depth K=1 took 6 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-11(UNSAT) depth K=1 took 20 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-12(UNSAT) depth K=1 took 12 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-13(UNSAT) depth K=1 took 24 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-14(UNSAT) depth K=1 took 11 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-15(UNSAT) depth K=1 took 10 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-00(UNSAT) depth K=2 took 624 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-01(UNSAT) depth K=2 took 13 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-02(UNSAT) depth K=2 took 15 ms
May 19, 2018 12:53:38 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-03(UNSAT) depth K=2 took 13 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-04(UNSAT) depth K=2 took 30 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-05(UNSAT) depth K=2 took 15 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-06(UNSAT) depth K=2 took 40 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-07(UNSAT) depth K=2 took 30 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-08(UNSAT) depth K=2 took 43 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-09(UNSAT) depth K=2 took 13 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-10(UNSAT) depth K=2 took 11 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-11(UNSAT) depth K=2 took 12 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-12(UNSAT) depth K=2 took 14 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-13(UNSAT) depth K=2 took 14 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-14(UNSAT) depth K=2 took 11 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-10a-ReachabilityCardinality-15(UNSAT) depth K=2 took 12 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 213 place invariants in 176 ms
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Error adding positive variable constraint (error "Failed to assert expression: java.io.IOException: Broken pipe (>= (select (select s 0) 18) 0)")
Exception in thread "Thread-8" java.lang.RuntimeException: SMT assertion produced unexpected response success
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:145)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying DLCround-PT-10a-ReachabilityCardinality-00 SMT depth 3
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 3
May 19, 2018 12:53:39 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 3
May 19, 2018 12:53:39 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 16 properties. Interrupting other analysis methods.
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-10a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-10a.tgz
mv DLCround-PT-10a execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DLCround-PT-10a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r068-smll-152649741100103"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;