Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 560K
-rw-r--r-- 1 mcc users 2.9K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.2K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 2.9K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 106 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 344 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 398K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is DLCround-PT-07a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r068-smll-152649741100061
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-07a-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1526666845351

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-00 with value :(!(u6.p45>=2))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-01 with value :((u37.p133==0)||(u77.p173==1))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-02 with value :((u11.p96==0)||(u45.p141==1))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-03 with value :((u7.p55==0)||(u30.p126==1))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-04 with value :(!(u4.p26>=2))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-05 with value :(((!(u64.p160>=2))||(u7.p57>=1))||(((u115.p211>=2)||(u40.p136>=1))&&(u1.p1>=1)))
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-06 with value :(((!((u53.p149==0)||(u115.p211==1)))||(u70.p166>=2))&&((u94.p190==0)||(u12.p107==1)))
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-07 with value :(!((((u3.p16==0)||(u28.p124==1))&&(u64.p160>=1))||((u35.p131==0)||(u10.p84==1))))
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-08 with value :(u3.p18>=2)
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-09 with value :((!(((u47.p143==0)||(u10.p86==1))||((u28.p124==0)||(u88.p184==1))))&&((!((u7.p55==0)||(u33.p129==1)))||((u56.p152==0)||(u76.p172==1))))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-10 with value :((u12.p99==0)||(u12.p99==1))
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-11 with value :(u11.p97>=2)
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-12 with value :(((u1.p3==0)||(u14.p110==1))&&(((u97.p193==0)||(u61.p157==1))&&((u7.p55>=2)&&(u65.p161>=2))))
Read [reachable] property : DLCround-PT-07a-ReachabilityCardinality-13 with value :((u37.p133>=3)||((u51.p147>=2)||((u1.p7>=2)&&((u45.p141==0)||(u15.p111==1)))))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-14 with value :((u3.p20==0)||(u33.p129==1))
Read [invariant] property : DLCround-PT-07a-ReachabilityCardinality-15 with value :(!(u5.p35>=2))
built 241 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_07a\_flat\_flat\_mod,2.401e+11,0.777318,10844,272,21,3398,694,1708,3009,68,806,0
Total reachable state count : 240100000001

Verifying 16 reachability properties.
Invariant property DLCround-PT-07a-ReachabilityCardinality-00 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-00 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-00,0,0.778637,10872,1,0,3398,694,1712,3009,71,806,0
Invariant property DLCround-PT-07a-ReachabilityCardinality-01 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-01,0,0.779611,10992,1,0,3398,694,1718,3009,75,806,100
Invariant property DLCround-PT-07a-ReachabilityCardinality-02 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-02,0,0.78053,10992,1,0,3398,694,1723,3009,77,806,204
Invariant property DLCround-PT-07a-ReachabilityCardinality-03 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-03,0,0.781421,10992,1,0,3398,694,1728,3009,79,806,266
Invariant property DLCround-PT-07a-ReachabilityCardinality-04 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-04 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-04,0,0.78206,10992,1,0,3398,694,1732,3009,81,806,266
Invariant property DLCround-PT-07a-ReachabilityCardinality-05 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-05,0,0.784205,10992,1,0,3398,694,1743,3009,84,806,706
Reachability property DLCround-PT-07a-ReachabilityCardinality-06 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-06

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-06,0,0.785158,10992,1,0,3398,694,1755,3009,85,806,850
Reachability property DLCround-PT-07a-ReachabilityCardinality-07 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-07

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-07,0,0.78699,10992,1,0,3398,694,1770,3009,89,806,1027
Reachability property DLCround-PT-07a-ReachabilityCardinality-08 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-08

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-08,0,0.787389,10992,1,0,3398,694,1772,3009,90,806,1027
Reachability property DLCround-PT-07a-ReachabilityCardinality-09 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-09,0,0.788789,10992,1,0,3398,694,1792,3009,92,806,1179
Invariant property DLCround-PT-07a-ReachabilityCardinality-10 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-10,0,0.789151,10992,1,0,3398,694,1799,3009,98,806,1179
Reachability property DLCround-PT-07a-ReachabilityCardinality-11 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-11,0,0.789368,10992,1,0,3398,694,1800,3009,98,806,1179
Reachability property DLCround-PT-07a-ReachabilityCardinality-12 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-12,0,0.790386,10992,1,0,3398,694,1816,3009,99,806,1271
Reachability property DLCround-PT-07a-ReachabilityCardinality-13 does not hold.
FORMULA DLCround-PT-07a-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-07a-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-13,0,0.791519,10992,1,0,3398,694,1829,3009,101,806,1339
Invariant property DLCround-PT-07a-ReachabilityCardinality-14 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-14,0,0.792331,10992,1,0,3398,694,1833,3009,103,806,1393
Invariant property DLCround-PT-07a-ReachabilityCardinality-15 is true.
FORMULA DLCround-PT-07a-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-07a-ReachabilityCardinality-15,0,0.793383,10992,1,0,3398,694,1835,3009,103,806,1393
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 170
// Phase 1: matrix 170 rows 229 cols
invariant :p150 + -1'p228 = 0
invariant :p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + -1'p228 = 0
invariant :p119 + -1'p228 = 0
invariant :p200 + -1'p228 = 0
invariant :p139 + -1'p228 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p228 = 0
invariant :p130 + -1'p228 = 0
invariant :p153 + -1'p228 = 0
invariant :p203 + -1'p228 = 0
invariant :p206 + -1'p228 = 0
invariant :p191 + -1'p228 = 0
invariant :p154 + -1'p228 = 0
invariant :p198 + -1'p228 = 0
invariant :p118 + -1'p228 = 0
invariant :p219 + -1'p228 = 0
invariant :p169 + -1'p228 = 0
invariant :p133 + -1'p228 = 0
invariant :p208 + -1'p228 = 0
invariant :p223 + -1'p228 = 0
invariant :p109 + -1'p228 = 0
invariant :p131 + -1'p228 = 0
invariant :p202 + -1'p228 = 0
invariant :p199 + -1'p228 = 0
invariant :p125 + -1'p228 = 0
invariant :p0 + p228 = 1
invariant :p220 + -1'p228 = 0
invariant :p195 + -1'p228 = 0
invariant :p143 + -1'p228 = 0
invariant :p165 + -1'p228 = 0
invariant :p204 + -1'p228 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + -1'p228 = 0
invariant :p112 + -1'p228 = 0
invariant :p136 + -1'p228 = 0
invariant :p138 + -1'p228 = 0
invariant :p157 + -1'p228 = 0
invariant :p151 + -1'p228 = 0
invariant :p217 + -1'p228 = 0
invariant :p123 + -1'p228 = 0
invariant :p110 + -1'p228 = 0
invariant :p124 + -1'p228 = 0
invariant :p187 + -1'p228 = 0
invariant :p148 + -1'p228 = 0
invariant :p129 + -1'p228 = 0
invariant :p122 + -1'p228 = 0
invariant :p212 + -1'p228 = 0
invariant :p126 + -1'p228 = 0
invariant :p205 + -1'p228 = 0
invariant :p194 + -1'p228 = 0
invariant :p172 + -1'p228 = 0
invariant :p174 + -1'p228 = 0
invariant :p147 + -1'p228 = 0
invariant :p161 + -1'p228 = 0
invariant :p128 + -1'p228 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p228 = 0
invariant :p221 + -1'p228 = 0
invariant :p175 + -1'p228 = 0
invariant :p176 + -1'p228 = 0
invariant :p211 + -1'p228 = 0
invariant :p210 + -1'p228 = 0
invariant :p181 + -1'p228 = 0
invariant :p89 + p90 + p91 + p92 + p93 + p94 + p95 + p96 + p97 + p98 + -1'p228 = 0
invariant :p207 + -1'p228 = 0
invariant :p227 + -1'p228 = 0
invariant :p193 + -1'p228 = 0
invariant :p183 + -1'p228 = 0
invariant :p196 + -1'p228 = 0
invariant :p160 + -1'p228 = 0
invariant :p121 + -1'p228 = 0
invariant :p171 + -1'p228 = 0
invariant :p178 + -1'p228 = 0
invariant :p140 + -1'p228 = 0
invariant :p134 + -1'p228 = 0
invariant :p137 + -1'p228 = 0
invariant :p216 + -1'p228 = 0
invariant :p162 + -1'p228 = 0
invariant :p127 + -1'p228 = 0
invariant :p170 + -1'p228 = 0
invariant :p168 + -1'p228 = 0
invariant :p113 + -1'p228 = 0
invariant :p213 + -1'p228 = 0
invariant :p158 + -1'p228 = 0
invariant :p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + -1'p228 = 0
invariant :p192 + -1'p228 = 0
invariant :p222 + -1'p228 = 0
invariant :p135 + -1'p228 = 0
invariant :p225 + -1'p228 = 0
invariant :p145 + -1'p228 = 0
invariant :p184 + -1'p228 = 0
invariant :p214 + -1'p228 = 0
invariant :p163 + -1'p228 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p228 = 0
invariant :p185 + -1'p228 = 0
invariant :p156 + -1'p228 = 0
invariant :p190 + -1'p228 = 0
invariant :p141 + -1'p228 = 0
invariant :p114 + -1'p228 = 0
invariant :p146 + -1'p228 = 0
invariant :p177 + -1'p228 = 0
invariant :p201 + -1'p228 = 0
invariant :p99 + p100 + p101 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + -1'p228 = 0
invariant :p49 + p50 + p51 + p52 + p53 + p54 + p55 + p56 + p57 + p58 + -1'p228 = 0
invariant :p173 + -1'p228 = 0
invariant :p197 + -1'p228 = 0
invariant :p155 + -1'p228 = 0
invariant :p166 + -1'p228 = 0
invariant :p152 + -1'p228 = 0
invariant :p180 + -1'p228 = 0
invariant :p159 + -1'p228 = 0
invariant :p186 + -1'p228 = 0
invariant :p209 + -1'p228 = 0
invariant :p189 + -1'p228 = 0
invariant :p215 + -1'p228 = 0
invariant :p116 + -1'p228 = 0
invariant :p117 + -1'p228 = 0
invariant :p144 + -1'p228 = 0
invariant :p69 + p70 + p71 + p72 + p73 + p74 + p75 + p76 + p77 + p78 + -1'p228 = 0
invariant :p218 + -1'p228 = 0
invariant :p188 + -1'p228 = 0
invariant :p167 + -1'p228 = 0
invariant :p149 + -1'p228 = 0
invariant :p224 + -1'p228 = 0
invariant :p120 + -1'p228 = 0
invariant :p115 + -1'p228 = 0
invariant :p142 + -1'p228 = 0
invariant :p179 + -1'p228 = 0
invariant :p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + -1'p228 = 0
invariant :p226 + -1'p228 = 0
invariant :p164 + -1'p228 = 0
invariant :p182 + -1'p228 = 0
invariant :p111 + -1'p228 = 0
invariant :p132 + -1'p228 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p228 = 0

BK_STOP 1526666854244

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 18, 2018 6:07:27 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 18, 2018 6:07:27 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 18, 2018 6:07:27 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 215 ms
May 18, 2018 6:07:28 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 229 places.
May 18, 2018 6:07:28 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1597 transitions.
May 18, 2018 6:07:28 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 18, 2018 6:07:28 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 56 ms
May 18, 2018 6:07:28 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 467 ms
May 18, 2018 6:07:28 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 18, 2018 6:07:29 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 18, 2018 6:07:29 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 352 ms
May 18, 2018 6:07:29 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 18, 2018 6:07:29 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 454 ms
May 18, 2018 6:07:29 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1597 transitions.
May 18, 2018 6:07:29 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (1597) to apply POR reductions. Disabling POR matrices.
May 18, 2018 6:07:29 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1597 transitions.
May 18, 2018 6:07:29 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 639ms conformant to PINS in folder :/home/mcc/execution
May 18, 2018 6:07:29 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 2560 redundant transitions.
May 18, 2018 6:07:29 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 29 ms
May 18, 2018 6:07:29 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
May 18, 2018 6:07:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 1469 ms.
May 18, 2018 6:07:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-00(UNSAT) depth K=0 took 4 ms
May 18, 2018 6:07:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-01(UNSAT) depth K=0 took 2 ms
May 18, 2018 6:07:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-02(UNSAT) depth K=0 took 2 ms
May 18, 2018 6:07:30 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-03(UNSAT) depth K=0 took 28 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-04(UNSAT) depth K=0 took 15 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-05(UNSAT) depth K=0 took 12 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-06(UNSAT) depth K=0 took 20 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-07(UNSAT) depth K=0 took 16 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-08(UNSAT) depth K=0 took 18 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-09(UNSAT) depth K=0 took 15 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-10(UNSAT) depth K=0 took 9 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-11(UNSAT) depth K=0 took 11 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-12(UNSAT) depth K=0 took 12 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-13(UNSAT) depth K=0 took 12 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-14(UNSAT) depth K=0 took 16 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1597 transitions.
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-15(UNSAT) depth K=0 took 16 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-00(UNSAT) depth K=1 took 18 ms
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-07a-ReachabilityCardinality-01(UNSAT) depth K=1 took 14 ms
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying DLCround-PT-07a-ReachabilityCardinality-02 SMT depth 1
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 1
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 1
May 18, 2018 6:07:31 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 132 place invariants in 67 ms
May 18, 2018 6:07:32 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 229 variables to be positive in 845 ms
May 18, 2018 6:07:32 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 0/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07a.tgz
mv DLCround-PT-07a execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is DLCround-PT-07a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r068-smll-152649741100061"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;