About the Execution of Irma.full for DLCround-PT-12a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1035.070 | 21096.00 | 53535.00 | 736.00 | FTFFFFFFTFTTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:50 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:50 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.5K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 106 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 344 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:50 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:50 instance
-rw-r--r-- 1 mcc users 6 May 15 18:50 iscolored
-rw-r--r-- 1 mcc users 871K May 15 18:50 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool irma4mcc-full
Input is DLCround-PT-12a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r066-smll-152649737100131
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-12a-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1526644678015
BK_STOP 1526644699111
--------------------
content from stderr:
Prefix is 65b80f64.
Reading known information in /usr/share/mcc4mcc/65b80f64-known.json.
Reading learned information in /usr/share/mcc4mcc/65b80f64-learned.json.
Reading value translations in /usr/share/mcc4mcc/65b80f64-values.json.
Using directory /home/mcc/execution for input, as it contains a model.pnml file.
Using DLCround-PT-12a as instance name.
Using DLCround as model name.
Using algorithm or tool bmdt.
Model characteristics are: {'Examination': 'ReachabilityCardinality', 'Place/Transition': True, 'Colored': False, 'Relative-Time': 1, 'Relative-Memory': 1, 'Ordinary': True, 'Simple Free Choice': False, 'Extended Free Choice': False, 'State Machine': False, 'Marked Graph': False, 'Connected': True, 'Strongly Connected': False, 'Source Place': True, 'Sink Place': False, 'Source Transition': False, 'Sink Transition': False, 'Loop Free': None, 'Conservative': False, 'Sub-Conservative': False, 'Nested Units': True, 'Safe': True, 'Deadlock': None, 'Reversible': None, 'Quasi Live': None, 'Live': None}.
Known tools are: [{'Time': 7955, 'Memory': 573.74, 'Tool': 'itstools'}, {'Time': 8278, 'Memory': 192.6, 'Tool': 'lola'}].
Learned tools are: [{'Tool': 'lola'}].
Learned tool lola is 1.0406033940917663x far from the best tool itstools.
ReachabilityCardinality itstools DLCround-PT-12a...
May 18, 2018 11:58:08 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-z3path, /usr/bin/z3, -yices2path, /usr/bin/yices, -ltsminpath, /usr/bin, -smt, -its, -pnfolder, /mcc-data, -examination, ReachabilityCardinality]
May 18, 2018 11:58:08 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /mcc-data/model.pnml
May 18, 2018 11:58:08 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 324 ms
May 18, 2018 11:58:09 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 419 places.
May 18, 2018 11:58:09 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3407 transitions.
May 18, 2018 11:58:09 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 18, 2018 11:58:09 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /mcc-data/model.pnml.img.gal : 78 ms
May 18, 2018 11:58:10 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 897 ms
Using solver Z3 to compute partial order matrices.
Built C files in :
/mcc-data
May 18, 2018 11:58:10 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 18, 2018 11:58:10 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 18, 2018 11:58:11 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 501 ms
May 18, 2018 11:58:11 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 18, 2018 11:58:11 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 688 ms
May 18, 2018 11:58:11 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3407 transitions.
May 18, 2018 11:58:11 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3407 transitions.
May 18, 2018 11:58:12 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 5800 redundant transitions.
May 18, 2018 11:58:12 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /mcc-data/ReachabilityCardinality.pnml.gal : 45 ms
May 18, 2018 11:58:12 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /mcc-data/ReachabilityCardinality.prop : 1 ms
Invoking ITS tools like this :CommandLine [args=[/usr/share/itscl/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201804131302/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /mcc-data/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/mcc-data]
its-reach command run as :
/usr/share/itscl/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201804131302/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /mcc-data/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-00 with value :(!(((u235.p376==0)||(u41.p182==1))||(!(u3.p15>=3))))
Read [invariant] property : DLCround-PT-12a-ReachabilityCardinality-01 with value :(!(((u7.p58>=2)||((u96.p237==0)||(u25.p166==1)))&&((u152.p293>=2)&&((u110.p251==0)||(u193.p334==1)))))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-02 with value :(((((u37.p178==0)||(u140.p281==1))||((u115.p256==0)||(u243.p384==1)))&&((u270.p411>=2)||(u214.p355>=2)))||((u157.p298>=2)&&((u60.p201==0)||(u97.p238==1))))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-03 with value :((((u47.p188>=2)||(u2.p11>=1))&&((u17.p156>=2)&&((u224.p365==0)||(u231.p372==1))))&&((((u5.p38==0)||(u232.p373==1))&&((u220.p361==0)||(u151.p292==1)))&&(u173.p314>=2)))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-04 with value :(u148.p289>=2)
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-05 with value :(!((!(u144.p285>=3))&&(((u5.p35==0)||(u11.p93==1))||((u272.p413==0)||(u103.p244==1)))))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-06 with value :(((!((u10.p85==0)||(u272.p413==1)))&&(!(u166.p307>=3)))&&(!((u140.p281>=3)&&((u147.p288==0)||(u130.p271==1)))))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-07 with value :((!(((u180.p321==0)||(u137.p278==1))||(u9.p71>=2)))&&((u29.p170==0)||(u248.p389==1)))
Read [invariant] property : DLCround-PT-12a-ReachabilityCardinality-08 with value :((((u132.p273==0)||(u115.p256==1))||(!(u12.p104>=2)))||((!((u277.p418==0)||(u79.p220==1)))||(((u4.p22==0)||(u6.p39==1))||(u45.p186>=2))))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-09 with value :(u4.p27>=3)
Read [invariant] property : DLCround-PT-12a-ReachabilityCardinality-10 with value :((((u16.p143>=3)||(u253.p394>=1))&&(!(u88.p229>=3)))||(!(u77.p218>=1)))
Read [invariant] property : DLCround-PT-12a-ReachabilityCardinality-11 with value :(!(u6.p42>=2))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-12 with value :((u223.p364>=3)&&((u243.p384==0)||(u79.p220==1)))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-13 with value :((((u226.p367>=3)&&((u10.p84==0)||(u60.p201==1)))&&(((u260.p401==0)||(u101.p242==1))&&(u6.p47>=1)))||((!((u26.p167==0)||(u56.p197==1)))||((u77.p218>=3)&&(u40.p181>=2))))
Read [reachable] property : DLCround-PT-12a-ReachabilityCardinality-14 with value :(((u61.p202==0)||(u186.p327==1))&&(u218.p359>=2))
Read [invariant] property : DLCround-PT-12a-ReachabilityCardinality-15 with value :(((((u214.p355==0)||(u186.p327==1))&&((u2.p12==0)||(u59.p200==1)))&&(!(u69.p210>=3)))||(!(((u230.p371==0)||(u222.p363==1))&&(u72.p213>=3))))
built 521 ordering constraints for composite.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 250
// Phase 1: matrix 250 rows 419 cols
May 18, 2018 11:58:14 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 3354 ms.
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-00(UNSAT) depth K=0 took 13 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-01(UNSAT) depth K=0 took 1 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-02(UNSAT) depth K=0 took 2 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-03(UNSAT) depth K=0 took 1 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-04(UNSAT) depth K=0 took 0 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-05(UNSAT) depth K=0 took 6 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-06(UNSAT) depth K=0 took 1 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-07(UNSAT) depth K=0 took 4 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-08(UNSAT) depth K=0 took 1 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-09(UNSAT) depth K=0 took 1 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-10(UNSAT) depth K=0 took 2 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-11(UNSAT) depth K=0 took 6 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-12(UNSAT) depth K=0 took 1 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-13(UNSAT) depth K=0 took 3 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-14(UNSAT) depth K=0 took 0 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-15(UNSAT) depth K=0 took 10 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-00(UNSAT) depth K=1 took 15 ms
invariant :p353 + -1'p418 = 0
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-01(UNSAT) depth K=1 took 8 ms
invariant :p270 + -1'p418 = 0
invariant :p0 + p418 = 1
invariant :p226 + -1'p418 = 0
invariant :p358 + -1'p418 = 0
invariant :p232 + -1'p418 = 0
invariant :p408 + -1'p418 = 0
invariant :p208 + -1'p418 = 0
invariant :p269 + -1'p418 = 0
invariant :p263 + -1'p418 = 0
invariant :p178 + -1'p418 = 0
invariant :p221 + -1'p418 = 0
invariant :p247 + -1'p418 = 0
invariant :p361 + -1'p418 = 0
invariant :p262 + -1'p418 = 0
invariant :p354 + -1'p418 = 0
invariant :p379 + -1'p418 = 0
invariant :p172 + -1'p418 = 0
invariant :p225 + -1'p418 = 0
invariant :p245 + -1'p418 = 0
invariant :p386 + -1'p418 = 0
invariant :p258 + -1'p418 = 0
invariant :p244 + -1'p418 = 0
invariant :p206 + -1'p418 = 0
invariant :p350 + -1'p418 = 0
invariant :p375 + -1'p418 = 0
invariant :p235 + -1'p418 = 0
invariant :p318 + -1'p418 = 0
invariant :p274 + -1'p418 = 0
invariant :p197 + -1'p418 = 0
invariant :p264 + -1'p418 = 0
invariant :p355 + -1'p418 = 0
invariant :p376 + -1'p418 = 0
invariant :p338 + -1'p418 = 0
invariant :p202 + -1'p418 = 0
invariant :p273 + -1'p418 = 0
invariant :p391 + -1'p418 = 0
invariant :p119 + p120 + p121 + p122 + p123 + p124 + p125 + p126 + p127 + p128 + -1'p418 = 0
invariant :p401 + -1'p418 = 0
invariant :p193 + -1'p418 = 0
invariant :p402 + -1'p418 = 0
invariant :p412 + -1'p418 = 0
invariant :p163 + -1'p418 = 0
invariant :p363 + -1'p418 = 0
invariant :p89 + p90 + p91 + p92 + p93 + p94 + p95 + p96 + p97 + p98 + -1'p418 = 0
invariant :p377 + -1'p418 = 0
invariant :p380 + -1'p418 = 0
invariant :p271 + -1'p418 = 0
invariant :p246 + -1'p418 = 0
invariant :p188 + -1'p418 = 0
invariant :p237 + -1'p418 = 0
invariant :p291 + -1'p418 = 0
invariant :p227 + -1'p418 = 0
invariant :p335 + -1'p418 = 0
invariant :p268 + -1'p418 = 0
invariant :p218 + -1'p418 = 0
invariant :p207 + -1'p418 = 0
invariant :p189 + -1'p418 = 0
invariant :p413 + -1'p418 = 0
invariant :p249 + -1'p418 = 0
invariant :p251 + -1'p418 = 0
invariant :p389 + -1'p418 = 0
invariant :p321 + -1'p418 = 0
invariant :p333 + -1'p418 = 0
invariant :p320 + -1'p418 = 0
invariant :p39 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + -1'p418 = 0
invariant :p396 + -1'p418 = 0
invariant :p230 + -1'p418 = 0
invariant :p213 + -1'p418 = 0
invariant :p217 + -1'p418 = 0
invariant :p266 + -1'p418 = 0
invariant :p256 + -1'p418 = 0
invariant :p295 + -1'p418 = 0
invariant :p384 + -1'p418 = 0
invariant :p222 + -1'p418 = 0
invariant :p329 + -1'p418 = 0
invariant :p190 + -1'p418 = 0
invariant :p356 + -1'p418 = 0
invariant :p332 + -1'p418 = 0
invariant :p236 + -1'p418 = 0
invariant :p165 + -1'p418 = 0
invariant :p372 + -1'p418 = 0
invariant :p220 + -1'p418 = 0
invariant :p8 + p9 + p10 + p11 + p12 + p13 + p14 + -1'p418 = 0
invariant :p312 + -1'p418 = 0
invariant :p328 + -1'p418 = 0
invariant :p395 + -1'p418 = 0
invariant :p357 + -1'p418 = 0
invariant :p210 + -1'p418 = 0
invariant :p414 + -1'p418 = 0
invariant :p310 + -1'p418 = 0
invariant :p298 + -1'p418 = 0
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-02(UNSAT) depth K=1 took 11 ms
invariant :p228 + -1'p418 = 0
invariant :p300 + -1'p418 = 0
invariant :p164 + -1'p418 = 0
invariant :p253 + -1'p418 = 0
invariant :p369 + -1'p418 = 0
invariant :p167 + -1'p418 = 0
invariant :p233 + -1'p418 = 0
invariant :p192 + -1'p418 = 0
invariant :p219 + -1'p418 = 0
invariant :p276 + -1'p418 = 0
invariant :p301 + -1'p418 = 0
invariant :p294 + -1'p418 = 0
invariant :p1 + p2 + p3 + p4 + p5 + p6 + p7 + -1'p418 = 0
invariant :p347 + -1'p418 = 0
invariant :p198 + -1'p418 = 0
invariant :p378 + -1'p418 = 0
invariant :p345 + -1'p418 = 0
invariant :p139 + p140 + p141 + p142 + p143 + p144 + p145 + p146 + p147 + p148 + -1'p418 = 0
invariant :p342 + -1'p418 = 0
invariant :p272 + -1'p418 = 0
invariant :p292 + -1'p418 = 0
invariant :p241 + -1'p418 = 0
invariant :p129 + p130 + p131 + p132 + p133 + p134 + p135 + p136 + p137 + p138 + -1'p418 = 0
invariant :p410 + -1'p418 = 0
invariant :p215 + -1'p418 = 0
invariant :p304 + -1'p418 = 0
invariant :p405 + -1'p418 = 0
invariant :p343 + -1'p418 = 0
invariant :p403 + -1'p418 = 0
invariant :p400 + -1'p418 = 0
invariant :p325 + -1'p418 = 0
invariant :p181 + -1'p418 = 0
invariant :p161 + -1'p418 = 0
invariant :p149 + p150 + p151 + p152 + p153 + p154 + p155 + p156 + p157 + p158 + -1'p418 = 0
invariant :p267 + -1'p418 = 0
invariant :p346 + -1'p418 = 0
invariant :p351 + -1'p418 = 0
invariant :p191 + -1'p418 = 0
invariant :p330 + -1'p418 = 0
invariant :p324 + -1'p418 = 0
invariant :p288 + -1'p418 = 0
invariant :p406 + -1'p418 = 0
invariant :p352 + -1'p418 = 0
invariant :p184 + -1'p418 = 0
invariant :p289 + -1'p418 = 0
invariant :p49 + p50 + p51 + p52 + p53 + p54 + p55 + p56 + p57 + p58 + -1'p418 = 0
invariant :p280 + -1'p418 = 0
invariant :p360 + -1'p418 = 0
invariant :p179 + -1'p418 = 0
invariant :p371 + -1'p418 = 0
invariant :p166 + -1'p418 = 0
invariant :p382 + -1'p418 = 0
invariant :p316 + -1'p418 = 0
invariant :p397 + -1'p418 = 0
invariant :p182 + -1'p418 = 0
invariant :p417 + -1'p418 = 0
invariant :p22 + p23 + p24 + p25 + p26 + p27 + p28 + -1'p418 = 0
invariant :p374 + -1'p418 = 0
invariant :p383 + -1'p418 = 0
invariant :p373 + -1'p418 = 0
invariant :p159 + -1'p418 = 0
invariant :p364 + -1'p418 = 0
invariant :p311 + -1'p418 = 0
invariant :p297 + -1'p418 = 0
invariant :p212 + -1'p418 = 0
invariant :p224 + -1'p418 = 0
invariant :p180 + -1'p418 = 0
invariant :p171 + -1'p418 = 0
invariant :p416 + -1'p418 = 0
invariant :p290 + -1'p418 = 0
invariant :p317 + -1'p418 = 0
invariant :p366 + -1'p418 = 0
invariant :p287 + -1'p418 = 0
invariant :p255 + -1'p418 = 0
invariant :p275 + -1'p418 = 0
invariant :p322 + -1'p418 = 0
invariant :p15 + p16 + p17 + p18 + p19 + p20 + p21 + -1'p418 = 0
invariant :p319 + -1'p418 = 0
invariant :p307 + -1'p418 = 0
invariant :p173 + -1'p418 = 0
invariant :p243 + -1'p418 = 0
invariant :p223 + -1'p418 = 0
invariant :p176 + -1'p418 = 0
invariant :p185 + -1'p418 = 0
invariant :p211 + -1'p418 = 0
invariant :p339 + -1'p418 = 0
invariant :p293 + -1'p418 = 0
invariant :p314 + -1'p418 = 0
invariant :p195 + -1'p418 = 0
invariant :p315 + -1'p418 = 0
invariant :p196 + -1'p418 = 0
invariant :p162 + -1'p418 = 0
invariant :p367 + -1'p418 = 0
invariant :p365 + -1'p418 = 0
invariant :p99 + p100 + p101 + p102 + p103 + p104 + p105 + p106 + p107 + p108 + -1'p418 = 0
invariant :p175 + -1'p418 = 0
invariant :p214 + -1'p418 = 0
invariant :p260 + -1'p418 = 0
invariant :p341 + -1'p418 = 0
invariant :p404 + -1'p418 = 0
invariant :p187 + -1'p418 = 0
invariant :p109 + p110 + p111 + p112 + p113 + p114 + p115 + p116 + p117 + p118 + -1'p418 = 0
invariant :p248 + -1'p418 = 0
invariant :p362 + -1'p418 = 0
invariant :p387 + -1'p418 = 0
invariant :p392 + -1'p418 = 0
invariant :p313 + -1'p418 = 0
invariant :p160 + -1'p418 = 0
invariant :p327 + -1'p418 = 0
invariant :p201 + -1'p418 = 0
invariant :p170 + -1'p418 = 0
invariant :p194 + -1'p418 = 0
invariant :p239 + -1'p418 = 0
invariant :p303 + -1'p418 = 0
invariant :p259 + -1'p418 = 0
invariant :p199 + -1'p418 = 0
invariant :p296 + -1'p418 = 0
invariant :p285 + -1'p418 = 0
invariant :p344 + -1'p418 = 0
invariant :p348 + -1'p418 = 0
invariant :p415 + -1'p418 = 0
invariant :p323 + -1'p418 = 0
invariant :p183 + -1'p418 = 0
invariant :p286 + -1'p418 = 0
invariant :p209 + -1'p418 = 0
invariant :p299 + -1'p418 = 0
invariant :p411 + -1'p418 = 0
invariant :p385 + -1'p418 = 0
invariant :p169 + -1'p418 = 0
invariant :p261 + -1'p418 = 0
invariant :p254 + -1'p418 = 0
invariant :p302 + -1'p418 = 0
invariant :p326 + -1'p418 = 0
invariant :p279 + -1'p418 = 0
invariant :p257 + -1'p418 = 0
invariant :p309 + -1'p418 = 0
invariant :p398 + -1'p418 = 0
invariant :p186 + -1'p418 = 0
invariant :p282 + -1'p418 = 0
invariant :p177 + -1'p418 = 0
invariant :p234 + -1'p418 = 0
invariant :p216 + -1'p418 = 0
invariant :p399 + -1'p418 = 0
invariant :p393 + -1'p418 = 0
invariant :p381 + -1'p418 = 0
invariant :p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + -1'p418 = 0
invariant :p265 + -1'p418 = 0
invariant :p238 + -1'p418 = 0
invariant :p278 + -1'p418 = 0
invariant :p174 + -1'p418 = 0
invariant :p337 + -1'p418 = 0
invariant :p390 + -1'p418 = 0
invariant :p305 + -1'p418 = 0
invariant :p370 + -1'p418 = 0
invariant :p205 + -1'p418 = 0
invariant :p306 + -1'p418 = 0
invariant :p331 + -1'p418 = 0
invariant :p284 + -1'p418 = 0
invariant :p250 + -1'p418 = 0
invariant :p203 + -1'p418 = 0
invariant :p388 + -1'p418 = 0
invariant :p242 + -1'p418 = 0
invariant :p308 + -1'p418 = 0
invariant :p79 + p80 + p81 + p82 + p83 + p84 + p85 + p86 + p87 + p88 + -1'p418 = 0
invariant :p168 + -1'p418 = 0
invariant :p407 + -1'p418 = 0
invariant :p231 + -1'p418 = 0
invariant :p252 + -1'p418 = 0
invariant :p368 + -1'p418 = 0
invariant :p229 + -1'p418 = 0
invariant :p277 + -1'p418 = 0
invariant :p349 + -1'p418 = 0
invariant :p336 + -1'p418 = 0
invariant :p281 + -1'p418 = 0
invariant :p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + -1'p418 = 0
invariant :p204 + -1'p418 = 0
invariant :p69 + p70 + p71 + p72 + p73 + p74 + p75 + p76 + p77 + p78 + -1'p418 = 0
invariant :p394 + -1'p418 = 0
invariant :p240 + -1'p418 = 0
invariant :p334 + -1'p418 = 0
invariant :p409 + -1'p418 = 0
invariant :p340 + -1'p418 = 0
invariant :p359 + -1'p418 = 0
invariant :p200 + -1'p418 = 0
invariant :p283 + -1'p418 = 0
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 277 place invariants in 639 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-03(UNSAT) depth K=1 took 32 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-04(UNSAT) depth K=1 took 2 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-05(UNSAT) depth K=1 took 48 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-06(UNSAT) depth K=1 took 3 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-07(UNSAT) depth K=1 took 6 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-08(UNSAT) depth K=1 took 19 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-09(UNSAT) depth K=1 took 7 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-10(UNSAT) depth K=1 took 22 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-11(UNSAT) depth K=1 took 3 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-12(UNSAT) depth K=1 took 2 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-13(UNSAT) depth K=1 took 8 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-14(UNSAT) depth K=1 took 4 ms
May 18, 2018 11:58:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-15(UNSAT) depth K=1 took 3 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-00(UNSAT) depth K=2 took 911 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-01(UNSAT) depth K=2 took 22 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-02(UNSAT) depth K=2 took 76 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-03(UNSAT) depth K=2 took 25 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-04(UNSAT) depth K=2 took 16 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-05(UNSAT) depth K=2 took 63 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-06(UNSAT) depth K=2 took 20 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-07(UNSAT) depth K=2 took 16 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-08(UNSAT) depth K=2 took 29 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-09(UNSAT) depth K=2 took 18 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-10(UNSAT) depth K=2 took 40 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-11(UNSAT) depth K=2 took 19 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-12(UNSAT) depth K=2 took 24 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-13(UNSAT) depth K=2 took 56 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-14(UNSAT) depth K=2 took 10 ms
May 18, 2018 11:58:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property DLCround-PT-12a-ReachabilityCardinality-15(UNSAT) depth K=2 took 10 ms
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_12a\_flat\_flat\_mod,2.401e+16,3.81389,31444,562,21,12858,1264,3643,12108,68,1241,0
Total reachable state count : 24010000000000001
Verifying 16 reachability properties.
Reachability property DLCround-PT-12a-ReachabilityCardinality-00 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-00
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-00,0,3.81856,31444,1,0,12858,1264,3655,12108,75,1241,482
Invariant property DLCround-PT-12a-ReachabilityCardinality-01 is true.
FORMULA DLCround-PT-12a-ReachabilityCardinality-01 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-01,0,3.82046,31572,1,0,12858,1264,3672,12108,77,1241,676
Reachability property DLCround-PT-12a-ReachabilityCardinality-02 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-02
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-02,0,3.82208,31572,1,0,12858,1264,3691,12108,77,1241,676
Reachability property DLCround-PT-12a-ReachabilityCardinality-03 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-03 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-03
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-03,0,3.82631,31572,1,0,12858,1264,3719,12108,80,1241,1216
Reachability property DLCround-PT-12a-ReachabilityCardinality-04 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-04 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-04
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-04,0,3.82674,31572,1,0,12858,1264,3720,12108,80,1241,1216
Reachability property DLCround-PT-12a-ReachabilityCardinality-05 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-05
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-05,0,3.82981,31572,1,0,12858,1264,3736,12108,84,1241,1954
Reachability property DLCround-PT-12a-ReachabilityCardinality-06 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-06
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-06,0,3.83255,31572,1,0,12858,1264,3753,12108,84,1241,2300
Reachability property DLCround-PT-12a-ReachabilityCardinality-07 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-07
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-07,0,3.83458,31572,1,0,12858,1264,3766,12108,85,1241,2960
Invariant property DLCround-PT-12a-ReachabilityCardinality-08 is true.
FORMULA DLCround-PT-12a-ReachabilityCardinality-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-08,0,3.83744,31572,1,0,12858,1264,3791,12108,91,1241,3963
Reachability property DLCround-PT-12a-ReachabilityCardinality-09 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-09
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-09,0,3.83816,31572,1,0,12858,1264,3793,12108,92,1241,3963
Invariant property DLCround-PT-12a-ReachabilityCardinality-10 is true.
FORMULA DLCround-PT-12a-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-10,0,3.8399,31572,1,0,12858,1264,3804,12108,94,1241,4706
Invariant property DLCround-PT-12a-ReachabilityCardinality-11 is true.
FORMULA DLCround-PT-12a-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-11,0,3.84042,31572,1,0,12858,1264,3807,12108,95,1241,4706
Reachability property DLCround-PT-12a-ReachabilityCardinality-12 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-12
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-12,0,3.84126,31572,1,0,12858,1264,3812,12108,95,1241,4710
Reachability property DLCround-PT-12a-ReachabilityCardinality-13 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-13
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-13,0,3.84586,31572,1,0,12858,1264,3837,12108,96,1241,5122
Reachability property DLCround-PT-12a-ReachabilityCardinality-14 does not hold.
FORMULA DLCround-PT-12a-ReachabilityCardinality-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-12a-ReachabilityCardinality-14
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-14,0,3.84676,31572,1,0,12858,1264,3843,12108,96,1241,5122
Invariant property DLCround-PT-12a-ReachabilityCardinality-15 is true.
FORMULA DLCround-PT-12a-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-12a-ReachabilityCardinality-15,0,3.85034,31572,1,0,12858,1264,3865,12108,98,1241,6010
May 18, 2018 11:58:17 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-12a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="irma4mcc-full"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-12a.tgz
mv DLCround-PT-12a execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool irma4mcc-full"
echo " Input is DLCround-PT-12a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r066-smll-152649737100131"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;