Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
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/home/mcc/execution
total 828K
-rw-r--r-- 1 mcc users 4.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 10K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 118 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 356 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 660K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is CloudReconfiguration-PT-312, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r057-smll-152646384600083
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CloudReconfiguration-PT-312-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1527262349617

Flatten gal took : 607 ms
Constant places removed 1 places and 1 transitions.
Performed 1934 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 1935 rules applied. Total rules applied 1935 place count 2584 transition count 1160
Constant places removed 1935 places and 1 transitions.
Reduce isomorphic transitions removed 92 transitions.
Performed 57 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 2084 rules applied. Total rules applied 4019 place count 649 transition count 1010
Constant places removed 57 places and 0 transitions.
Reduce isomorphic transitions removed 15 transitions.
Performed 12 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 84 rules applied. Total rules applied 4103 place count 592 transition count 983
Constant places removed 12 places and 0 transitions.
Reduce isomorphic transitions removed 9 transitions.
Performed 9 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 30 rules applied. Total rules applied 4133 place count 580 transition count 965
Constant places removed 9 places and 0 transitions.
Reduce isomorphic transitions removed 9 transitions.
Performed 18 Post agglomeration using F-continuation condition.
Iterating post reduction 4 with 36 rules applied. Total rules applied 4169 place count 571 transition count 938
Constant places removed 18 places and 0 transitions.
Iterating post reduction 5 with 18 rules applied. Total rules applied 4187 place count 553 transition count 938
Performed 34 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 6 with 34 Pre rules applied. Total rules applied 4187 place count 553 transition count 904
Constant places removed 34 places and 0 transitions.
Iterating post reduction 6 with 34 rules applied. Total rules applied 4221 place count 519 transition count 904
Symmetric choice reduction at 7 with 75 rule applications. Total rules 4296 place count 519 transition count 904
Constant places removed 75 places and 87 transitions.
Reduce isomorphic transitions removed 18 transitions.
Performed 21 Post agglomeration using F-continuation condition.
Iterating post reduction 7 with 114 rules applied. Total rules applied 4410 place count 444 transition count 778
Constant places removed 21 places and 0 transitions.
Reduce isomorphic transitions removed 6 transitions.
Performed 6 Post agglomeration using F-continuation condition.
Iterating post reduction 8 with 33 rules applied. Total rules applied 4443 place count 423 transition count 766
Constant places removed 6 places and 0 transitions.
Iterating post reduction 9 with 6 rules applied. Total rules applied 4449 place count 417 transition count 766
Performed 1 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 4449 place count 417 transition count 765
Constant places removed 1 places and 0 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 4450 place count 416 transition count 765
Symmetric choice reduction at 11 with 15 rule applications. Total rules 4465 place count 416 transition count 765
Constant places removed 15 places and 27 transitions.
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 11 with 18 rules applied. Total rules applied 4483 place count 401 transition count 735
Symmetric choice reduction at 12 with 9 rule applications. Total rules 4492 place count 401 transition count 735
Constant places removed 9 places and 18 transitions.
Iterating post reduction 12 with 9 rules applied. Total rules applied 4501 place count 392 transition count 717
Symmetric choice reduction at 13 with 3 rule applications. Total rules 4504 place count 392 transition count 717
Constant places removed 3 places and 6 transitions.
Iterating post reduction 13 with 3 rules applied. Total rules applied 4507 place count 389 transition count 711
Performed 174 Post agglomeration using F-continuation condition.
Constant places removed 174 places and 0 transitions.
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 14 with 189 rules applied. Total rules applied 4696 place count 215 transition count 447
Performed 18 Post agglomeration using F-continuation condition.
Constant places removed 18 places and 0 transitions.
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 15 with 24 rules applied. Total rules applied 4720 place count 197 transition count 423
Performed 3 Post agglomeration using F-continuation condition.
Constant places removed 3 places and 0 transitions.
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 16 with 9 rules applied. Total rules applied 4729 place count 194 transition count 414
Performed 27 Post agglomeration using F-continuation condition.
Constant places removed 27 places and 0 transitions.
Reduce isomorphic transitions removed 42 transitions.
Iterating post reduction 17 with 69 rules applied. Total rules applied 4798 place count 167 transition count 849
Symmetric choice reduction at 18 with 3 rule applications. Total rules 4801 place count 167 transition count 849
Constant places removed 3 places and 30 transitions.
Iterating post reduction 18 with 3 rules applied. Total rules applied 4804 place count 164 transition count 819
Applied a total of 4804 rules in 1738 ms. Remains 164 /2585 variables (removed 2421) and now considering 819/3095 (removed 2276) transitions.
Normalized transition count is 674
// Phase 1: matrix 674 rows 164 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 674
// Phase 1: matrix 674 rows 164 cols
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
built 2 ordering constraints for composite.
built 563 ordering constraints for composite.
built 563 ordering constraints for composite.
built 376 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,3.65706e+06,0.646884,13496,124,642,3087,9378,1058,6393,349,50759,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,115340,0.763652,13932,64,575,3087,16690,3276,6393,1474,57000,942

System contains 115340 deadlocks (shown below if less than --print-limit option) !
FORMULA CloudReconfiguration-PT-312-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 115340 states ] showing 10 first states
[ u8={[ p2575=1 ]
} i0={[ u2={[ p13=1 ]
[ p18=1 ]
[ p24=1 ]
[ p30=1 ]
} i1={[ u7={[ p1916=1 ]
[ p1915=1 ]
[ p1924=1 ]
[ p1925=1 ]
[ p1941=1 ]
[ p1942=1 ]
[ p2063=1 ]
[ p2571=1 ]
[ p2122=1 ]
[ p2096=1 ]
} i0={[ u6={[ p1252=1 ]
[ p1253=1 ]
[ p1261=1 ]
[ p1262=1 ]
[ p1278=1 ]
[ p1279=1 ]
[ p1908=1 ]
[ p1400=1 ]
[ p1459=1 ]
[ p1433=1 ]
} u5={[ p590=1 ]
[ p589=1 ]
[ p598=1 ]
[ p599=1 ]
[ p615=1 ]
[ p616=1 ]
[ p737=1 ]
[ p1245=1 ]
[ p796=1 ]
[ p770=1 ]
} ]
} ]
} ]
} ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1527262359882

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 25, 2018 3:32:32 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 25, 2018 3:32:32 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 25, 2018 3:32:32 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 337 ms
May 25, 2018 3:32:32 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 2585 places.
May 25, 2018 3:32:32 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3095 transitions.
May 25, 2018 3:32:32 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 25, 2018 3:32:32 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 69 ms
May 25, 2018 3:32:33 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 600 ms
May 25, 2018 3:32:33 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 20 ms
May 25, 2018 3:32:34 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 3095 transitions.
May 25, 2018 3:32:36 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 25, 2018 3:32:36 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 819 transitions.
May 25, 2018 3:32:36 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 109 ms
May 25, 2018 3:32:36 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 88 ms
May 25, 2018 3:32:36 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 25, 2018 3:32:36 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 98 ms
May 25, 2018 3:32:36 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 25, 2018 3:32:36 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 0 place invariants in 19 ms
May 25, 2018 3:32:37 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 955 redundant transitions.
May 25, 2018 3:32:37 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 20 ms
May 25, 2018 3:32:38 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
Skipping mayMatrices nes/nds SMT solver raised an exception or timeout :(error "Failed to check-sat")
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:116)
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.init(NecessaryEnablingsolver.java:71)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:471)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 25, 2018 3:32:38 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 2447ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CloudReconfiguration-PT-312"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/CloudReconfiguration-PT-312.tgz
mv CloudReconfiguration-PT-312 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is CloudReconfiguration-PT-312, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r057-smll-152646384600083"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;