Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 4.2K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.2K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 118 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 356 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.7K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 4 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 912K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is CloudReconfiguration-PT-401, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r056-smll-152646383700146
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CloudReconfiguration-PT-401-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1526567305268

Flatten gal took : 812 ms
Constant places removed 1 places and 1 transitions.
Performed 2653 Post agglomeration using F-continuation condition.
Iterating post reduction 0 with 2654 rules applied. Total rules applied 2654 place count 3553 transition count 1609
Constant places removed 2654 places and 1 transitions.
Reduce isomorphic transitions removed 131 transitions.
Performed 80 Post agglomeration using F-continuation condition.
Iterating post reduction 1 with 2865 rules applied. Total rules applied 5519 place count 899 transition count 1397
Constant places removed 80 places and 0 transitions.
Reduce isomorphic transitions removed 24 transitions.
Performed 20 Post agglomeration using F-continuation condition.
Iterating post reduction 2 with 124 rules applied. Total rules applied 5643 place count 819 transition count 1353
Constant places removed 20 places and 0 transitions.
Reduce isomorphic transitions removed 16 transitions.
Performed 16 Post agglomeration using F-continuation condition.
Iterating post reduction 3 with 52 rules applied. Total rules applied 5695 place count 799 transition count 1321
Constant places removed 16 places and 0 transitions.
Reduce isomorphic transitions removed 16 transitions.
Performed 32 Post agglomeration using F-continuation condition.
Iterating post reduction 4 with 64 rules applied. Total rules applied 5759 place count 783 transition count 1273
Constant places removed 32 places and 0 transitions.
Iterating post reduction 5 with 32 rules applied. Total rules applied 5791 place count 751 transition count 1273
Performed 53 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 6 with 53 Pre rules applied. Total rules applied 5791 place count 751 transition count 1220
Constant places removed 53 places and 0 transitions.
Iterating post reduction 6 with 53 rules applied. Total rules applied 5844 place count 698 transition count 1220
Symmetric choice reduction at 7 with 104 rule applications. Total rules 5948 place count 698 transition count 1220
Constant places removed 104 places and 124 transitions.
Reduce isomorphic transitions removed 24 transitions.
Performed 28 Post agglomeration using F-continuation condition.
Iterating post reduction 7 with 156 rules applied. Total rules applied 6104 place count 594 transition count 1044
Constant places removed 28 places and 0 transitions.
Reduce isomorphic transitions removed 8 transitions.
Performed 8 Post agglomeration using F-continuation condition.
Iterating post reduction 8 with 44 rules applied. Total rules applied 6148 place count 566 transition count 1028
Constant places removed 8 places and 0 transitions.
Iterating post reduction 9 with 8 rules applied. Total rules applied 6156 place count 558 transition count 1028
Performed 1 Pre agglomeration using Quasi-Persistent + HF-interchangeable + Divergent Free condition.
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 6156 place count 558 transition count 1027
Constant places removed 1 places and 0 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 6157 place count 557 transition count 1027
Symmetric choice reduction at 11 with 20 rule applications. Total rules 6177 place count 557 transition count 1027
Constant places removed 20 places and 36 transitions.
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 11 with 24 rules applied. Total rules applied 6201 place count 537 transition count 987
Symmetric choice reduction at 12 with 12 rule applications. Total rules 6213 place count 537 transition count 987
Constant places removed 12 places and 24 transitions.
Iterating post reduction 12 with 12 rules applied. Total rules applied 6225 place count 525 transition count 963
Symmetric choice reduction at 13 with 4 rule applications. Total rules 6229 place count 525 transition count 963
Constant places removed 4 places and 8 transitions.
Iterating post reduction 13 with 4 rules applied. Total rules applied 6233 place count 521 transition count 955
Performed 232 Post agglomeration using F-continuation condition.
Constant places removed 232 places and 0 transitions.
Reduce isomorphic transitions removed 20 transitions.
Iterating post reduction 14 with 252 rules applied. Total rules applied 6485 place count 289 transition count 603
Performed 24 Post agglomeration using F-continuation condition.
Constant places removed 24 places and 0 transitions.
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 15 with 32 rules applied. Total rules applied 6517 place count 265 transition count 571
Performed 4 Post agglomeration using F-continuation condition.
Constant places removed 4 places and 0 transitions.
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 16 with 12 rules applied. Total rules applied 6529 place count 261 transition count 559
Performed 36 Post agglomeration using F-continuation condition.
Constant places removed 36 places and 0 transitions.
Reduce isomorphic transitions removed 56 transitions.
Iterating post reduction 17 with 92 rules applied. Total rules applied 6621 place count 225 transition count 1139
Symmetric choice reduction at 18 with 4 rule applications. Total rules 6625 place count 225 transition count 1139
Constant places removed 4 places and 40 transitions.
Iterating post reduction 18 with 4 rules applied. Total rules applied 6629 place count 221 transition count 1099
Applied a total of 6629 rules in 1967 ms. Remains 221 /3554 variables (removed 3333) and now considering 1099/4263 (removed 3164) transitions.
Normalized transition count is 901
// Phase 1: matrix 901 rows 221 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 901
// Phase 1: matrix 901 rows 221 cols
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,2.26791e+08,5.53125,104784,2,9833,5,270868,6,0,1877,228975,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,3.08729e+06,10.6152,149236,2,2356,7,682523,9,1,9237,228975,2

System contains 3.08729e+06 deadlocks (shown below if less than --print-limit option) !
FORMULA CloudReconfiguration-PT-401-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 3087290 states ] showing 10 first states
[ ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1099=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1040=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1173=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1236=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1073=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1205=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p902=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p20=1 p1548=1 ]
[ p2882=1 p3541=1 p2219=1 p1703=1 p893=1 p20=1 ]
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1526567324903

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 17, 2018 2:28:28 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 17, 2018 2:28:28 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 17, 2018 2:28:28 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 325 ms
May 17, 2018 2:28:28 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 3554 places.
May 17, 2018 2:28:28 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 4263 transitions.
May 17, 2018 2:28:28 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 17, 2018 2:28:29 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 83 ms
May 17, 2018 2:28:29 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 805 ms
May 17, 2018 2:28:29 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 22 ms
May 17, 2018 2:28:30 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 4263 transitions.
May 17, 2018 2:28:32 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 7 ms
May 17, 2018 2:28:32 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 1099 transitions.
May 17, 2018 2:28:33 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 0 place invariants in 32 ms
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 221 variables to be positive in 1626 ms
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 1099 transitions.
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/1099 took 2 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 172 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 1099 transitions.
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 83 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 17, 2018 2:28:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 1099 transitions.
May 17, 2018 2:28:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(57/1099) took 3000 ms. Total solver calls (SAT/UNSAT): 3511(3511/0)
May 17, 2018 2:28:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(327/1099) took 6366 ms. Total solver calls (SAT/UNSAT): 4834(4834/0)
May 17, 2018 2:28:43 PM org.smtlib.impl.Script execute
WARNING: Script execution failed on command (assert (and (>= (select s0 29) 1) (>= (select s0 117) 1))) with error (error "Failed to assert expression: java.io.IOException: Stream closed (and (>= (select s0 29) 1) (>= (select s0 117) 1))")
[(assert (and (>= (select s0 29) 1) (>= (select s0 117) 1)))]
Skipping mayMatrices nes/nds SMT solver raised an exception.
java.lang.RuntimeException: SMT solver raised an exception.
at fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver.computeCoEnablingMatrix(NecessaryEnablingsolver.java:475)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printLabels(Gal2PinsTransformerNext.java:530)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.printDependencyMatrix(Gal2PinsTransformerNext.java:209)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.buildBodyFile(Gal2PinsTransformerNext.java:85)
at fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext.transform(Gal2PinsTransformerNext.java:830)
at fr.lip6.move.gal.application.LTSminRunner$1.run(LTSminRunner.java:71)
at java.lang.Thread.run(Thread.java:748)
May 17, 2018 2:28:43 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 10851ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CloudReconfiguration-PT-401"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/CloudReconfiguration-PT-401.tgz
mv CloudReconfiguration-PT-401 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is CloudReconfiguration-PT-401, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r056-smll-152646383700146"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;