Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
....................
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 8.8K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 33K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 22K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 69K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 43K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 5.6K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 20K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 121 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 359 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 34K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 107K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.1K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 10 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 598K May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is BridgeAndVehicles-PT-V20P20N10, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r032-ebro-152646310300293
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-PT-V20P20N10-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1526925131749

Flatten gal took : 400 ms
Constant places removed 2 places and 0 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 66 transition count 548
Symmetric choice reduction at 1 with 1 rule applications. Total rules 3 place count 66 transition count 548
Constant places removed 1 places and 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 65 transition count 547
Performed 1 Post agglomeration using F-continuation condition.
Constant places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 6 place count 63 transition count 546
Performed 2 Post agglomeration using F-continuation condition.
Constant places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 8 place count 61 transition count 544
Applied a total of 8 rules in 110 ms. Remains 61 /68 variables (removed 7) and now considering 544/548 (removed 4) transitions.
Normalized transition count is 126
// Phase 1: matrix 126 rows 61 cols
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]

its-ctl command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 126
// Phase 1: matrix 126 rows 61 cols
invariant :NB_ATTENTE_A_0 + NB_ATTENTE_A_1 + NB_ATTENTE_A_2 + NB_ATTENTE_A_3 + NB_ATTENTE_A_4 + NB_ATTENTE_A_5 + NB_ATTENTE_A_6 + NB_ATTENTE_A_7 + NB_ATTENTE_A_8 + NB_ATTENTE_A_9 + NB_ATTENTE_A_10 + NB_ATTENTE_A_11 + NB_ATTENTE_A_12 + NB_ATTENTE_A_13 + NB_ATTENTE_A_14 + NB_ATTENTE_A_15 + NB_ATTENTE_A_16 + NB_ATTENTE_A_17 + NB_ATTENTE_A_18 + NB_ATTENTE_A_19 + NB_ATTENTE_A_20 = 1
invariant :COMPTEUR_0 + COMPTEUR_1 + COMPTEUR_2 + COMPTEUR_3 + COMPTEUR_4 + COMPTEUR_5 + COMPTEUR_6 + COMPTEUR_7 + COMPTEUR_8 + COMPTEUR_9 + COMPTEUR_10 = 1
invariant :NB_ATTENTE_B_0 + NB_ATTENTE_B_1 + NB_ATTENTE_B_2 + NB_ATTENTE_B_3 + NB_ATTENTE_B_4 + NB_ATTENTE_B_5 + NB_ATTENTE_B_6 + NB_ATTENTE_B_7 + NB_ATTENTE_B_8 + NB_ATTENTE_B_9 + NB_ATTENTE_B_10 + NB_ATTENTE_B_11 + NB_ATTENTE_B_12 + NB_ATTENTE_B_13 + NB_ATTENTE_B_14 + NB_ATTENTE_B_15 + NB_ATTENTE_B_16 + NB_ATTENTE_B_17 + NB_ATTENTE_B_18 + NB_ATTENTE_B_19 + NB_ATTENTE_B_20 = 1
invariant :CONTROLEUR_1 + CONTROLEUR_2 + CHOIX_1 + CHOIX_2 = 1
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Compilation finished in 11865 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 126 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=1, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1.28251e+06,130.864,2017532,2,641203,5,1.26889e+06,6,0,789,1.77662e+06,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,20,342.601,4070792,2,91,7,6.94185e+06,9,1,4005,3.72627e+06,2

System contains 20 deadlocks (shown below if less than --print-limit option) !
FORMULA BridgeAndVehicles-PT-V20P20N10-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
[ 20 states ] showing 10 first states
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 COMPTEUR_1=1 ]
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 COMPTEUR_2=1 ]
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 COMPTEUR_3=1 ]
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 COMPTEUR_4=1 ]
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 COMPTEUR_5=1 ]
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 COMPTEUR_6=1 NB_ATTENTE_B_0=1 ]
[ NB_ATTENTE_A_0=1 CONTROLEUR_2=1 COMPTEUR_7=1 NB_ATTENTE_B_0=1 ]
[ NB_ATTENTE_A_0=1 COMPTEUR_8=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 ]
[ NB_ATTENTE_A_0=1 COMPTEUR_9=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 ]
[ COMPTEUR_10=1 NB_ATTENTE_A_0=1 CONTROLEUR_2=1 NB_ATTENTE_B_0=1 ]
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1526925483359

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 21, 2018 5:52:14 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityDeadlock, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 21, 2018 5:52:14 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 21, 2018 5:52:14 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 186 ms
May 21, 2018 5:52:14 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 68 places.
May 21, 2018 5:52:15 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 548 transitions.
May 21, 2018 5:52:15 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 71 ms
May 21, 2018 5:52:15 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 394 ms
May 21, 2018 5:52:15 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.simple.gal : 12 ms
May 21, 2018 5:52:16 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 548 transitions.
May 21, 2018 5:52:16 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 9 ms
May 21, 2018 5:52:16 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 544 transitions.
May 21, 2018 5:52:17 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 4 place invariants in 34 ms
May 21, 2018 5:52:17 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 61 variables to be positive in 524 ms
May 21, 2018 5:52:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 544 transitions.
May 21, 2018 5:52:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/544 took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 5:52:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 141 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 5:52:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 544 transitions.
May 21, 2018 5:52:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 60 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 5:52:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 544 transitions.
May 21, 2018 5:52:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(2/544) took 3316 ms. Total solver calls (SAT/UNSAT): 1437(244/1193)
May 21, 2018 5:52:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(12/544) took 6356 ms. Total solver calls (SAT/UNSAT): 6162(364/5798)
May 21, 2018 5:52:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(22/544) took 9526 ms. Total solver calls (SAT/UNSAT): 10829(692/10137)
May 21, 2018 5:52:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(28/544) took 13289 ms. Total solver calls (SAT/UNSAT): 13682(764/12918)
May 21, 2018 5:52:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(34/544) took 16340 ms. Total solver calls (SAT/UNSAT): 16499(836/15663)
May 21, 2018 5:52:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(43/544) took 19836 ms. Total solver calls (SAT/UNSAT): 20741(920/19821)
May 21, 2018 5:52:41 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(51/544) took 22911 ms. Total solver calls (SAT/UNSAT): 24705(920/23785)
May 21, 2018 5:52:44 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(56/544) took 26370 ms. Total solver calls (SAT/UNSAT): 27150(920/26230)
May 21, 2018 5:52:47 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(66/544) took 29524 ms. Total solver calls (SAT/UNSAT): 31965(920/31045)
May 21, 2018 5:52:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(78/544) took 32799 ms. Total solver calls (SAT/UNSAT): 37611(920/36691)
May 21, 2018 5:52:54 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(89/544) took 35960 ms. Total solver calls (SAT/UNSAT): 42660(920/41740)
May 21, 2018 5:52:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(102/544) took 39148 ms. Total solver calls (SAT/UNSAT): 48471(920/47551)
May 21, 2018 5:53:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(115/544) took 42268 ms. Total solver calls (SAT/UNSAT): 54113(920/53193)
May 21, 2018 5:53:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(126/544) took 45276 ms. Total solver calls (SAT/UNSAT): 58755(920/57835)
May 21, 2018 5:53:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(136/544) took 48292 ms. Total solver calls (SAT/UNSAT): 62870(920/61950)
May 21, 2018 5:53:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(151/544) took 51455 ms. Total solver calls (SAT/UNSAT): 68855(920/67935)
May 21, 2018 5:53:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(166/544) took 54513 ms. Total solver calls (SAT/UNSAT): 74615(920/73695)
May 21, 2018 5:53:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(182/544) took 57522 ms. Total solver calls (SAT/UNSAT): 80511(920/79591)
May 21, 2018 5:53:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(198/544) took 60615 ms. Total solver calls (SAT/UNSAT): 86151(920/85231)
May 21, 2018 5:53:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(215/544) took 63721 ms. Total solver calls (SAT/UNSAT): 91863(920/90943)
May 21, 2018 5:53:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(232/544) took 66961 ms. Total solver calls (SAT/UNSAT): 97286(920/96366)
May 21, 2018 5:53:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(246/544) took 69965 ms. Total solver calls (SAT/UNSAT): 101535(920/100615)
May 21, 2018 5:53:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(266/544) took 73057 ms. Total solver calls (SAT/UNSAT): 107265(920/106345)
May 21, 2018 5:53:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(286/544) took 76117 ms. Total solver calls (SAT/UNSAT): 112595(920/111675)
May 21, 2018 5:53:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(307/544) took 79160 ms. Total solver calls (SAT/UNSAT): 117761(920/116841)
May 21, 2018 5:53:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(330/544) took 82173 ms. Total solver calls (SAT/UNSAT): 122913(920/121993)
May 21, 2018 5:53:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(358/544) took 85230 ms. Total solver calls (SAT/UNSAT): 128471(920/127551)
May 21, 2018 5:53:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(388/544) took 88294 ms. Total solver calls (SAT/UNSAT): 133556(920/132636)
May 21, 2018 5:53:49 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(426/544) took 91337 ms. Total solver calls (SAT/UNSAT): 138705(920/137785)
May 21, 2018 5:53:52 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(474/544) took 94343 ms. Total solver calls (SAT/UNSAT): 143145(920/142225)
May 21, 2018 5:53:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 96841 ms. Total solver calls (SAT/UNSAT): 145491(920/144571)
May 21, 2018 5:53:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 544 transitions.
May 21, 2018 5:53:55 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 77 ms. Total solver calls (SAT/UNSAT): 0(0/0)
May 21, 2018 5:53:55 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 98377ms conformant to PINS in folder :/home/mcc/execution

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-PT-V20P20N10"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-PT-V20P20N10.tgz
mv BridgeAndVehicles-PT-V20P20N10 execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-PT-V20P20N10, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r032-ebro-152646310300293"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;