About the Execution of ITS-Tools.L for ARMCacheCoherence-PT-none
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15749.290 | 132788.00 | 453701.00 | 992.10 | FFTFFTFFTFTTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
.........................
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.5K May 26 09:26 LTLCardinality.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 26 09:26 LTLFireability.txt
-rw-r--r-- 1 mcc users 11K May 26 09:26 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 5 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 14M May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstoolsl
Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r009-qhx2-152646139300007
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-15
=== Now, execution of the tool begins
BK_START 1527749858026
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityFireability.pnml.gal, -t, CGAL, -reachable-file, ReachabilityFireability.prop, --nowitness], workingDir=/home/mcc/execution]
its-reach command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805241334/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityFireability.pnml.gal -t CGAL -reachable-file ReachabilityFireability.prop --nowitness
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 500
// Phase 1: matrix 500 rows 87 cols
invariant :p0 + p83 + p84 + p85 + p86 = 1
invariant :p0 + p1 + p2 + p3 + p4 + p5 = 1
invariant :p0 + p75 + p76 + p77 + p78 = 1
invariant :p0 + p10 + p11 + p12 + p13 + p14 + p15 + p16 + p17 + p18 + p19 + p20 + p21 + p22 + p23 + p24 = 1
invariant :p0 + p8 + p9 = 1
invariant :p0 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + p39 = 1
invariant :p0 + p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 = 1
invariant :p0 + p79 + p80 + p81 + p82 = 1
invariant :p0 + p6 + p7 = 1
invariant :p0 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + p49 + p50 + p51 + p52 + p53 + p54 = 1
invariant :p0 + p70 + p71 = 1
invariant :p0 + p72 + p73 + p74 = 1
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-01 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-03 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-04 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-06 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-09 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-12 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-13 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-14 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-15 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Loading property file ReachabilityFireability.prop.
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityFireability-00 with value :(!(((u1.p3>=1)&&(u6.p52>=1))&&(u10.p76>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-01 with value :(((((u1.p1>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u11.p80>=1))&&(((!((((u1.p4>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1)))||((((u1.p2>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1)))&&(((((u1.p3>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1))&&((((u1.p2>=1)&&(u7.p67>=1))&&(u10.p76>=1))&&((((u1.p3>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u12.p84>=1))))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-02 with value :(((((u1.p2>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&(((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))||((!((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u12.p84>=1)))&&((((u1.p2>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u12.p84>=1)))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-03 with value :((((((u1.p2>=1)&&(u6.p52>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&(((u1.p4>=1)&&(u5.p37>=1))&&(u10.p76>=1)))&&((!((((u1.p4>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u12.p84>=1)))&&((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u11.p80>=1))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-04 with value :((((((u1.p5>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))&&((((u1.p2>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u12.p84>=1)))&&(((((u1.p4>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u12.p84>=1))||(!((((u1.p5>=1)&&(u3.p8>=1))&&(u10.p76>=1))&&(((u1.p1>=1)&&(u7.p67>=1))&&(u12.p84>=1))))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-05 with value :((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u11.p80>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-06 with value :(!((!(((u1.p2>=1)&&(u4.p22>=1))&&(u11.p80>=1)))||(!(((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&((((u1.p2>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1))))))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityFireability-07 with value :(!((((u1.p3>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u11.p80>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-08 with value :(((u1.p2>=1)&&(u5.p37>=1))&&(u10.p76>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-09 with value :((((!(((u1.p2>=1)&&(u7.p67>=1))&&(u10.p76>=1)))&&((((u1.p5>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u11.p80>=1)))&&(((((u1.p3>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u11.p80>=1))&&(((((u1.p1>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))||((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1)))))&&((((u1.p4>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u12.p84>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-10 with value :(((u1.p3>=1)&&(u6.p52>=1))&&(u12.p84>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-11 with value :((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p69>=1))&&(u12.p84>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-12 with value :(((((u1.p5>=1)&&(u7.p67>=1))&&(u10.p75>=1))||(((((u1.p2>=1)&&(u4.p22>=1))&&(u5.p39>=1))&&(u11.p80>=1))&&((((u1.p5>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u11.p80>=1))))&&(((u1.p3>=1)&&(u7.p67>=1))&&(u11.p79>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-13 with value :(((((u1.p5>=1)&&(u6.p52>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&(((!((((u1.p4>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u12.p84>=1)))&&((((u1.p4>=1)&&(u5.p37>=1))&&(u10.p76>=1))||((((u1.p2>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u11.p80>=1))))||((((((u1.p1>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u12.p84>=1))&&((((u1.p2>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u11.p80>=1)))||(((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u12.p84>=1))&&(((u1.p2>=1)&&(u7.p67>=1))&&(u10.p76>=1))))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-14 with value :(((((u1.p3>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))&&((((u1.p2>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u11.p80>=1)))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityFireability-15 with value :(!((((((u1.p5>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u12.p84>=1))||(((((u1.p4>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u12.p84>=1))||(((u1.p1>=1)&&(u3.p9>=1))&&(u10.p78>=1))))&&((((u1.p3>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u11.p80>=1))))
built 50 ordering constraints for composite.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence\_PT\_none\_flat\_flat\_flat\_flat\_mod,3.20568e+08,45.7167,100132,65,60,2653,1475,1379,4557,100,9148,0
Total reachable state count : 320567601
Verifying 16 reachability properties.
Invariant property ARMCacheCoherence-PT-none-ReachabilityFireability-00 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-00,648000,45.7186,100164,23,43,2653,1475,1388,4557,104,9148,4
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-01 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-01
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-01,0,45.7213,100260,1,0,2653,1475,1464,4557,121,9148,38
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-02 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-02,14400,45.7233,100260,22,39,2653,1475,1494,4557,122,9148,90
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-03 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-03
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-03,0,45.7249,100260,1,0,2653,1475,1531,4557,128,9148,107
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-04 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-04
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-04,0,45.7267,100260,1,0,2653,1475,1576,4557,133,9148,128
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-05 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-05,43200,45.7272,100260,23,43,2653,1475,1578,4557,133,9148,129
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-06 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-06
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-06,0,45.7288,100260,1,0,2653,1475,1597,4557,135,9148,189
Invariant property ARMCacheCoherence-PT-none-ReachabilityFireability-07 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-07,43200,45.7294,100260,23,42,2653,1475,1604,4557,135,9148,189
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-08 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-08,648000,45.7298,100260,23,41,2653,1475,1609,4557,135,9148,189
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-09 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-09
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-09,0,45.7321,100260,1,0,2653,1475,1657,4557,142,9148,221
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-10 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-10,864000,45.7325,100260,22,42,2653,1475,1659,4557,142,9148,221
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-11 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-11,57600,45.7329,100260,23,46,2653,1475,1663,4557,142,9148,221
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-12 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-12
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-12,0,45.7344,100260,1,0,2653,1475,1701,4557,146,9148,268
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-13 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-13
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-13,0,45.7376,100260,1,0,2653,1475,1758,4557,147,9148,351
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-14 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-14
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-14,0,45.7385,100260,1,0,2653,1475,1776,4557,149,9148,351
Invariant property ARMCacheCoherence-PT-none-ReachabilityFireability-15 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-15,0,45.7403,100260,1,0,2653,1475,1796,4557,149,9148,415
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1527749990814
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -louvain -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 31, 2018 6:57:43 AM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -louvain, -smt]
May 31, 2018 6:57:43 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2018 6:57:45 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 1766 ms
May 31, 2018 6:57:45 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 87 places.
May 31, 2018 6:57:48 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 33676 transitions.
May 31, 2018 6:57:48 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 31, 2018 6:57:59 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 10084 ms
May 31, 2018 6:58:05 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2018 6:58:15 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 31, 2018 6:58:15 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (33676) to apply POR reductions. Disabling POR matrices.
May 31, 2018 6:58:17 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 16035 ms
May 31, 2018 6:58:19 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 13743 ms
May 31, 2018 6:58:23 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 18544ms conformant to PINS in folder :/home/mcc/execution
May 31, 2018 6:58:26 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 31, 2018 6:58:27 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 8474 ms
May 31, 2018 6:58:29 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2018 6:58:46 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 17123 ms
May 31, 2018 6:58:46 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 37616 ms.
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=0 took 37 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=0 took 6 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=0 took 13 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=0 took 12 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=0 took 4 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=0 took 4 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=0 took 1 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=0 took 1 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=0 took 0 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=0 took 0 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=0 took 0 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=0 took 0 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=0 took 0 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=0 took 7 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=0 took 1 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=0 took 0 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=1 took 28 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=1 took 15 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=1 took 19 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=1 took 19 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=1 took 19 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=1 took 19 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=1 took 15 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=1 took 16 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=1 took 16 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=1 took 16 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=1 took 15 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=1 took 16 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=1 took 20 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=1 took 15 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=1 took 16 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=1 took 4 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=2 took 48 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=2 took 29 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=2 took 9 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=2 took 13 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=2 took 12 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=2 took 12 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=2 took 8 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=2 took 11 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=2 took 7 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=2 took 9 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=2 took 13 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=2 took 10 ms
May 31, 2018 6:58:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=2 took 8 ms
May 31, 2018 6:58:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=2 took 12 ms
May 31, 2018 6:58:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=2 took 8 ms
May 31, 2018 6:58:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=2 took 9 ms
May 31, 2018 6:58:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=3 took 578 ms
May 31, 2018 6:58:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=3 took 1243 ms
May 31, 2018 6:58:59 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=3 took 1475 ms
May 31, 2018 6:59:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=3 took 823 ms
May 31, 2018 6:59:00 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=3 took 666 ms
May 31, 2018 6:59:01 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 123217 redundant transitions.
May 31, 2018 6:59:01 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityFireability.pnml.gal : 450 ms
May 31, 2018 6:59:02 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityFireability.prop : 11 ms
May 31, 2018 6:59:02 AM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 31, 2018 6:59:02 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=3 took 2129 ms
May 31, 2018 6:59:03 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=3 took 1022 ms
May 31, 2018 6:59:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=3 took 1615 ms
May 31, 2018 6:59:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=3 took 968 ms
May 31, 2018 6:59:07 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=3 took 1340 ms
May 31, 2018 6:59:09 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=3 took 1254 ms
May 31, 2018 6:59:11 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=3 took 2269 ms
May 31, 2018 6:59:12 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=3 took 1060 ms
May 31, 2018 6:59:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=3 took 1186 ms
May 31, 2018 6:59:14 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=3 took 783 ms
May 31, 2018 6:59:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=3 took 1158 ms
May 31, 2018 6:59:16 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 12 place invariants in 186 ms
May 31, 2018 6:59:22 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 87 variables to be positive in 6868 ms
May 31, 2018 6:59:23 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-00
May 31, 2018 6:59:23 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(SAT) depth K=0 took 459 ms
May 31, 2018 6:59:23 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-01
May 31, 2018 6:59:23 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-01
May 31, 2018 6:59:23 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(FALSE) depth K=0 took 772 ms
May 31, 2018 6:59:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-02
May 31, 2018 6:59:24 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(SAT) depth K=0 took 958 ms
May 31, 2018 6:59:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=4 took 9783 ms
May 31, 2018 6:59:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-03
May 31, 2018 6:59:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-03
May 31, 2018 6:59:25 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(FALSE) depth K=0 took 972 ms
May 31, 2018 6:59:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-04
May 31, 2018 6:59:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-04
May 31, 2018 6:59:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(FALSE) depth K=0 took 732 ms
May 31, 2018 6:59:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-05
May 31, 2018 6:59:26 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(SAT) depth K=0 took 317 ms
May 31, 2018 6:59:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-06
May 31, 2018 6:59:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-06
May 31, 2018 6:59:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(FALSE) depth K=0 took 638 ms
May 31, 2018 6:59:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-07
May 31, 2018 6:59:27 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(SAT) depth K=0 took 260 ms
May 31, 2018 6:59:28 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-08
May 31, 2018 6:59:28 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(SAT) depth K=0 took 763 ms
May 31, 2018 6:59:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-09
May 31, 2018 6:59:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-09
May 31, 2018 6:59:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(FALSE) depth K=0 took 988 ms
May 31, 2018 6:59:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-10
May 31, 2018 6:59:29 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(SAT) depth K=0 took 329 ms
May 31, 2018 6:59:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-11
May 31, 2018 6:59:30 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(SAT) depth K=0 took 503 ms
May 31, 2018 6:59:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-12
May 31, 2018 6:59:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-12
May 31, 2018 6:59:31 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(FALSE) depth K=0 took 1098 ms
May 31, 2018 6:59:32 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=4 took 6652 ms
May 31, 2018 6:59:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-13
May 31, 2018 6:59:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-13
May 31, 2018 6:59:33 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(FALSE) depth K=0 took 1816 ms
May 31, 2018 6:59:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-14
May 31, 2018 6:59:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-14
May 31, 2018 6:59:34 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(FALSE) depth K=0 took 1325 ms
May 31, 2018 6:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant ARMCacheCoherence-PT-none-ReachabilityFireability-15
May 31, 2018 6:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-15
May 31, 2018 6:59:36 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(TRUE) depth K=0 took 1913 ms
May 31, 2018 6:59:40 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=4 took 8595 ms
May 31, 2018 6:59:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-00
May 31, 2018 6:59:41 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(SAT) depth K=1 took 4674 ms
May 31, 2018 6:59:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-02
May 31, 2018 6:59:42 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(SAT) depth K=1 took 1363 ms
May 31, 2018 6:59:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-05
May 31, 2018 6:59:45 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(SAT) depth K=1 took 3440 ms
May 31, 2018 6:59:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-07
May 31, 2018 6:59:47 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(SAT) depth K=1 took 2069 ms
May 31, 2018 6:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 31, 2018 6:59:49 AM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 31, 2018 6:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying ARMCacheCoherence-PT-none-ReachabilityFireability-08 K-induction depth 1
Exception in thread "Thread-6" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 31, 2018 6:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying ARMCacheCoherence-PT-none-ReachabilityFireability-03 SMT depth 4
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 31, 2018 6:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
May 31, 2018 6:59:49 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
May 31, 2018 6:59:49 AM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 9/ 16 properties. Interrupting other analysis methods.
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="itstoolsl"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstoolsl"
echo " Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r009-qhx2-152646139300007"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;