About the Execution of ITS-Tools for ARMCacheCoherence-PT-none
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15738.400 | 125102.00 | 386058.00 | 1689.80 | FFTFFTFFTFTTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
.........................................................
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.4K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 5 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 14M May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r008-qhx2-152646138400007
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-15
=== Now, execution of the tool begins
BK_START 1526683640859
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityFireability.pnml.gal, -t, CGAL, -reachable-file, ReachabilityFireability.prop, --nowitness], workingDir=/home/mcc/execution]
its-reach command run as :
/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityFireability.pnml.gal -t CGAL -reachable-file ReachabilityFireability.prop --nowitness
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 500
// Phase 1: matrix 500 rows 87 cols
invariant :p0 + p83 + p84 + p85 + p86 = 1
invariant :p0 + p1 + p2 + p3 + p4 + p5 = 1
invariant :p0 + p75 + p76 + p77 + p78 = 1
invariant :p0 + p10 + p11 + p12 + p13 + p14 + p15 + p16 + p17 + p18 + p19 + p20 + p21 + p22 + p23 + p24 = 1
invariant :p0 + p8 + p9 = 1
invariant :p0 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + p39 = 1
invariant :p0 + p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 = 1
invariant :p0 + p79 + p80 + p81 + p82 = 1
invariant :p0 + p6 + p7 = 1
invariant :p0 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + p49 + p50 + p51 + p52 + p53 + p54 = 1
invariant :p0 + p70 + p71 = 1
invariant :p0 + p72 + p73 + p74 = 1
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-01 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-03 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Loading property file ReachabilityFireability.prop.
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityFireability-00 with value :(!(((u1.p3>=1)&&(u6.p52>=1))&&(u10.p76>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-01 with value :(((((u1.p1>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u11.p80>=1))&&(((!((((u1.p4>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1)))||((((u1.p2>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1)))&&(((((u1.p3>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1))&&((((u1.p2>=1)&&(u7.p67>=1))&&(u10.p76>=1))&&((((u1.p3>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u12.p84>=1))))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-02 with value :(((((u1.p2>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&(((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))||((!((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u12.p84>=1)))&&((((u1.p2>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u12.p84>=1)))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-03 with value :((((((u1.p2>=1)&&(u6.p52>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&(((u1.p4>=1)&&(u5.p37>=1))&&(u10.p76>=1)))&&((!((((u1.p4>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u12.p84>=1)))&&((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u11.p80>=1))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-04 with value :((((((u1.p5>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))&&((((u1.p2>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u12.p84>=1)))&&(((((u1.p4>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u12.p84>=1))||(!((((u1.p5>=1)&&(u3.p8>=1))&&(u10.p76>=1))&&(((u1.p1>=1)&&(u7.p67>=1))&&(u12.p84>=1))))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-05 with value :((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u11.p80>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-06 with value :(!((!(((u1.p2>=1)&&(u4.p22>=1))&&(u11.p80>=1)))||(!(((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&((((u1.p2>=1)&&(u4.p22>=1))&&(u5.p37>=1))&&(u11.p80>=1))))))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityFireability-07 with value :(!((((u1.p3>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u11.p80>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-08 with value :(((u1.p2>=1)&&(u5.p37>=1))&&(u10.p76>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-09 with value :((((!(((u1.p2>=1)&&(u7.p67>=1))&&(u10.p76>=1)))&&((((u1.p5>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u11.p80>=1)))&&(((((u1.p3>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u11.p80>=1))&&(((((u1.p1>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))||((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1)))))&&((((u1.p4>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u12.p84>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-10 with value :(((u1.p3>=1)&&(u6.p52>=1))&&(u12.p84>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-11 with value :((((u1.p3>=1)&&(u6.p52>=1))&&(u7.p69>=1))&&(u12.p84>=1))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-12 with value :(((((u1.p5>=1)&&(u7.p67>=1))&&(u10.p75>=1))||(((((u1.p2>=1)&&(u4.p22>=1))&&(u5.p39>=1))&&(u11.p80>=1))&&((((u1.p5>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u11.p80>=1))))&&(((u1.p3>=1)&&(u7.p67>=1))&&(u11.p79>=1)))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-13 with value :(((((u1.p5>=1)&&(u6.p52>=1))&&(u7.p69>=1))&&(u11.p80>=1))&&(((!((((u1.p4>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u12.p84>=1)))&&((((u1.p4>=1)&&(u5.p37>=1))&&(u10.p76>=1))||((((u1.p2>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u11.p80>=1))))||((((((u1.p1>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u12.p84>=1))&&((((u1.p2>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u11.p80>=1)))||(((((u1.p4>=1)&&(u6.p54>=1))&&(u7.p69>=1))&&(u12.p84>=1))&&(((u1.p2>=1)&&(u7.p67>=1))&&(u10.p76>=1))))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityFireability-14 with value :(((((u1.p3>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u12.p84>=1))&&((((u1.p2>=1)&&(u4.p24>=1))&&(u5.p37>=1))&&(u11.p80>=1)))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityFireability-15 with value :(!((((((u1.p5>=1)&&(u4.p24>=1))&&(u5.p39>=1))&&(u12.p84>=1))||(((((u1.p4>=1)&&(u6.p52>=1))&&(u7.p67>=1))&&(u12.p84>=1))||(((u1.p1>=1)&&(u3.p9>=1))&&(u10.p78>=1))))&&((((u1.p3>=1)&&(u6.p54>=1))&&(u7.p67>=1))&&(u11.p80>=1))))
built 50 ordering constraints for composite.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-04 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence\_PT\_none\_flat\_flat\_mod,3.20568e+08,48.2472,100132,65,60,2714,1584,1379,4928,100,9785,0
Total reachable state count : 320567601
Verifying 16 reachability properties.
Invariant property ARMCacheCoherence-PT-none-ReachabilityFireability-00 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-00 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-00,162000,48.2516,100160,24,44,2714,1584,1388,4928,104,9785,4
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-01 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-01
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-01,0,48.2545,100280,1,0,2714,1584,1464,4928,121,9785,38
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-02 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-02 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-02,3600,48.2567,100280,23,40,2714,1584,1494,4928,122,9785,86
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-03 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-03
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-03,0,48.2584,100280,1,0,2714,1584,1531,4928,128,9785,105
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-04 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-04
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-04,0,48.2605,100280,1,0,2714,1584,1576,4928,133,9785,126
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-05 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-05 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-05,10800,48.2611,100280,24,44,2714,1584,1578,4928,133,9785,127
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-06 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-06 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-06
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-06,0,48.2628,100280,1,0,2714,1584,1597,4928,135,9785,187
Invariant property ARMCacheCoherence-PT-none-ReachabilityFireability-07 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-07 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-07,10800,48.2635,100280,24,43,2714,1584,1604,4928,135,9785,187
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-08 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-08 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-08,162000,48.264,100280,24,42,2714,1584,1609,4928,135,9785,187
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-09 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-09 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-09
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-09,0,48.2664,100280,1,0,2714,1584,1657,4928,142,9785,219
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-10 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-10,216000,48.2669,100280,23,43,2714,1584,1659,4928,142,9785,219
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-11 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-11,14400,48.2674,100280,24,47,2714,1584,1663,4928,142,9785,219
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-12 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-12
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-12,0,48.269,100280,1,0,2714,1584,1701,4928,146,9785,266
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-13 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-13
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-13,0,48.2725,100280,1,0,2714,1584,1758,4928,147,9785,349
Reachability property ARMCacheCoherence-PT-none-ReachabilityFireability-14 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-14 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityFireability-14
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-14,0,48.2735,100280,1,0,2714,1584,1776,4928,149,9785,349
Invariant property ARMCacheCoherence-PT-none-ReachabilityFireability-15 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityFireability-15,0,48.2754,100280,1,0,2714,1584,1796,4928,149,9785,413
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.
BK_STOP 1526683765961
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityFireability -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 18, 2018 10:47:35 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 18, 2018 10:47:35 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 18, 2018 10:47:37 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 1476 ms
May 18, 2018 10:47:37 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 87 places.
May 18, 2018 10:47:39 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 33676 transitions.
May 18, 2018 10:47:39 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 18, 2018 10:47:49 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 10109 ms
May 18, 2018 10:47:56 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 18, 2018 10:48:01 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 18, 2018 10:48:08 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 18, 2018 10:48:08 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (33676) to apply POR reductions. Disabling POR matrices.
May 18, 2018 10:48:08 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 16338 ms
May 18, 2018 10:48:12 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 11021 ms
May 18, 2018 10:48:12 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 18, 2018 10:48:17 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 21235ms conformant to PINS in folder :/home/mcc/execution
May 18, 2018 10:48:18 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 18, 2018 10:48:32 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 123217 redundant transitions.
May 18, 2018 10:48:33 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityFireability.pnml.gal : 259 ms
May 18, 2018 10:48:33 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityFireability.prop : 3 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 34121 ms.
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=0 took 44 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=0 took 11 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=0 took 7 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=0 took 14 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=0 took 7 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=0 took 12 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=0 took 7 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=0 took 15 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=0 took 11 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=0 took 17 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=0 took 7 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=0 took 11 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=0 took 7 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=1 took 12 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=1 took 14 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=1 took 16 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=1 took 10 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=1 took 11 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=1 took 15 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=1 took 10 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=1 took 11 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=1 took 8 ms
May 18, 2018 10:48:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=1 took 18 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=2 took 102 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=2 took 11 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=2 took 9 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=2 took 12 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=2 took 9 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=2 took 11 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=2 took 13 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=2 took 7 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=2 took 12 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=2 took 11 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=2 took 14 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=2 took 11 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=2 took 7 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=2 took 16 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=2 took 7 ms
May 18, 2018 10:48:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=2 took 12 ms
May 18, 2018 10:48:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=3 took 1018 ms
May 18, 2018 10:48:45 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(UNSAT) depth K=3 took 1082 ms
May 18, 2018 10:48:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(UNSAT) depth K=3 took 712 ms
May 18, 2018 10:48:47 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(UNSAT) depth K=3 took 1211 ms
May 18, 2018 10:48:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(UNSAT) depth K=3 took 1357 ms
May 18, 2018 10:48:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-05(UNSAT) depth K=3 took 1135 ms
May 18, 2018 10:48:50 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 18, 2018 10:48:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-06(UNSAT) depth K=3 took 2576 ms
May 18, 2018 10:48:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-07(UNSAT) depth K=3 took 708 ms
May 18, 2018 10:48:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-08(UNSAT) depth K=3 took 686 ms
May 18, 2018 10:48:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-09(UNSAT) depth K=3 took 2790 ms
May 18, 2018 10:48:57 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-10(UNSAT) depth K=3 took 926 ms
May 18, 2018 10:48:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-11(UNSAT) depth K=3 took 565 ms
May 18, 2018 10:49:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-12(UNSAT) depth K=3 took 7382 ms
May 18, 2018 10:49:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-13(UNSAT) depth K=3 took 1413 ms
May 18, 2018 10:49:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-14(UNSAT) depth K=3 took 824 ms
May 18, 2018 10:49:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-15(UNSAT) depth K=3 took 615 ms
May 18, 2018 10:49:09 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 12 place invariants in 355 ms
May 18, 2018 10:49:17 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 87 variables to be positive in 8238 ms
May 18, 2018 10:49:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-00
May 18, 2018 10:49:17 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(SAT) depth K=0 took 529 ms
May 18, 2018 10:49:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-01
May 18, 2018 10:49:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-01
May 18, 2018 10:49:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-01(FALSE) depth K=0 took 1154 ms
May 18, 2018 10:49:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-00(UNSAT) depth K=4 took 10837 ms
May 18, 2018 10:49:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityFireability-02
May 18, 2018 10:49:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-02(SAT) depth K=0 took 1816 ms
May 18, 2018 10:49:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-03
May 18, 2018 10:49:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-03
May 18, 2018 10:49:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-03(FALSE) depth K=0 took 1831 ms
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityFireability-04
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityFireability-04
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityFireability-04(FALSE) depth K=0 took 1681 ms
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying ARMCacheCoherence-PT-none-ReachabilityFireability-05 K-induction depth 0
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying ARMCacheCoherence-PT-none-ReachabilityFireability-01 SMT depth 4
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
May 18, 2018 10:49:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
May 18, 2018 10:49:24 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 3/ 16 properties. Interrupting other analysis methods.
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
pwd
ls -lh
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r008-qhx2-152646138400007"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;