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Model Checking Contest 2018
8th edition, Bratislava, Slovakia, June 26, 2018
Execution of r008-qhx2-152646138400005
Last Updated
June 26, 2018

About the Execution of ITS-Tools for ARMCacheCoherence-PT-none

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15746.800 135127.00 433902.00 3067.00 FTFTFFFTFFFFFTTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
........................................................
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 3.0K May 15 18:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 16K May 15 18:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 15 18:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 15 18:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K May 15 18:49 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K May 15 18:49 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K May 15 18:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 15 18:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 9.4K May 15 18:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 15 18:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 15K May 15 18:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 116 May 15 18:54 ReachabilityDeadlock.txt
-rw-r--r-- 1 mcc users 354 May 15 18:54 ReachabilityDeadlock.xml
-rw-r--r-- 1 mcc users 2.6K May 15 18:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 15 18:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K May 15 18:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 15 18:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 15 18:49 equiv_col
-rw-r--r-- 1 mcc users 5 May 15 18:49 instance
-rw-r--r-- 1 mcc users 6 May 15 18:49 iscolored
-rw-r--r-- 1 mcc users 14M May 15 18:49 model.pnml
=====================================================================
Generated by BenchKit 2-3637
Executing tool itstools
Input is ARMCacheCoherence-PT-none, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r008-qhx2-152646138400005
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-00
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-01
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-02
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-03
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-04
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-05
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-06
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-07
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-08
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-09
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-10
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-11
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-12
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-13
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-14
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1526683508894

Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201805151631/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 500
// Phase 1: matrix 500 rows 87 cols
invariant :p0 + p83 + p84 + p85 + p86 = 1
invariant :p0 + p1 + p2 + p3 + p4 + p5 = 1
invariant :p0 + p75 + p76 + p77 + p78 = 1
invariant :p0 + p10 + p11 + p12 + p13 + p14 + p15 + p16 + p17 + p18 + p19 + p20 + p21 + p22 + p23 + p24 = 1
invariant :p0 + p8 + p9 = 1
invariant :p0 + p25 + p26 + p27 + p28 + p29 + p30 + p31 + p32 + p33 + p34 + p35 + p36 + p37 + p38 + p39 = 1
invariant :p0 + p55 + p56 + p57 + p58 + p59 + p60 + p61 + p62 + p63 + p64 + p65 + p66 + p67 + p68 + p69 = 1
invariant :p0 + p79 + p80 + p81 + p82 = 1
invariant :p0 + p6 + p7 = 1
invariant :p0 + p40 + p41 + p42 + p43 + p44 + p45 + p46 + p47 + p48 + p49 + p50 + p51 + p52 + p53 + p54 = 1
invariant :p0 + p70 + p71 = 1
invariant :p0 + p72 + p73 + p74 = 1
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-00 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-01 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-02 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-04 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-06 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-07 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-09 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-10 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-11 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Loading property file ReachabilityCardinality.prop.
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-00 with value :(u4.p12>=3)
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-01 with value :(!((u4.p17>=3)&&((u6.p43==0)||(u7.p60==1))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-02 with value :(u10.p76>=3)
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-03 with value :(!((((u5.p27==0)||(u4.p17==1))&&((u2.p7==0)||(u7.p65==1)))||((u6.p44>=3)||(u11.p80>=2))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-04 with value :((u6.p52>=3)&&((((u5.p27==0)||(u4.p12==1))||((u4.p16==0)||(u8.p70==1)))||(!(u1.p5>=1))))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-05 with value :(((u5.p33==0)||(u6.p41==1))||((!(u10.p75>=1))&&(((u5.p30==0)||(u1.p2==1))||(u5.p29>=1))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-06 with value :(u5.p31>=2)
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-07 with value :(!(u7.p62>=3))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-08 with value :(((!(u1.p5>=1))||(((u6.p41==0)||(u6.p49==1))||((u4.p16==0)||(u6.p52==1))))||(!((u4.p15>=2)||((u8.p71==0)||(u7.p66==1)))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-09 with value :(u7.p65>=3)
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-10 with value :(u7.p57>=3)
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-11 with value :((!(u4.p16>=1))&&((!((u5.p38==0)||(u4.p11==1)))&&((u6.p50>=2)&&((u7.p61==0)||(u11.p81==1)))))
Read [reachable] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-12 with value :(u11.p82>=3)
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-13 with value :((u2.p7>=3)||(!((u13.p0>=2)&&(u4.p22>=3))))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-14 with value :(!(u4.p21>=3))
Read [invariant] property : ARMCacheCoherence-PT-none-ReachabilityCardinality-15 with value :(((((u6.p45==0)||(u5.p33==1))||((u5.p30==0)||(u4.p20==1)))||(!(u6.p51>=3)))||(((u6.p51==0)||(u5.p34==1))||((u7.p66==0)||(u5.p32==1))))
built 50 ordering constraints for composite.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-12 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence\_PT\_none\_flat\_flat\_mod,3.20568e+08,53.3597,100104,65,60,2634,1516,1379,4517,100,9443,0
Total reachable state count : 320567601

Verifying 16 reachability properties.
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-00 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-00

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-00,0,53.3622,100132,1,0,2634,1516,1381,4517,102,9443,0
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-01 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-01,0,53.3647,100252,1,0,2634,1516,1391,4517,107,9443,28
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-02 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-02,0,53.3651,100252,1,0,2634,1516,1393,4517,108,9443,28
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-03 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-03 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-03,9.71712e+07,53.3733,100252,35,57,2634,1516,1412,4517,118,9443,97
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-04 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-04

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-04,0,53.3752,100252,1,0,2634,1516,1432,4517,127,9443,170
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-05 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-05 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-05,3.024e+06,53.3773,100252,24,58,2634,1516,1455,4517,138,9443,213
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-06 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-06

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-06,0,53.3782,100252,1,0,2634,1516,1457,4517,139,9443,213
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-07 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-07,0,53.3785,100252,1,0,2634,1516,1460,4517,140,9443,213
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-08 does not hold.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-08 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-08,119664,53.3812,100252,46,81,2634,1516,1484,4517,149,9443,338
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-09 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-09

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-09,0,53.3818,100252,1,0,2634,1516,1486,4517,150,9443,338
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-10 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-10,0,53.3821,100252,1,0,2634,1516,1487,4517,150,9443,338
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-11 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-11,0,53.3839,100252,1,0,2634,1516,1507,4517,154,9443,369
Reachability property ARMCacheCoherence-PT-none-ReachabilityCardinality-12 does not hold.
No reachable states exhibit your property : ARMCacheCoherence-PT-none-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-12,0,53.3844,100252,1,0,2634,1516,1509,4517,155,9443,369
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-13 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-13,0,53.3854,100252,1,0,2634,1516,1518,4517,156,9443,405
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-14 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-14,0,53.3857,100252,1,0,2634,1516,1522,4517,158,9443,405
Invariant property ARMCacheCoherence-PT-none-ReachabilityCardinality-15 is true.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ARMCacheCoherence-PT-none-ReachabilityCardinality-15,0,53.3881,100252,1,0,2634,1516,1554,4517,169,9443,484
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1526683644021

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -consoleLog -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
May 18, 2018 10:45:24 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -smt]
May 18, 2018 10:45:24 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 18, 2018 10:45:26 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 1836 ms
May 18, 2018 10:45:26 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 87 places.
May 18, 2018 10:45:28 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 33676 transitions.
May 18, 2018 10:45:28 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
May 18, 2018 10:45:39 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 10395 ms
May 18, 2018 10:45:45 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 18, 2018 10:45:52 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 18, 2018 10:45:58 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 18, 2018 10:45:58 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Too many transitions (33676) to apply POR reductions. Disabling POR matrices.
May 18, 2018 10:45:59 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 17932 ms
May 18, 2018 10:46:04 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 12053 ms
May 18, 2018 10:46:04 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
May 18, 2018 10:46:07 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 22608ms conformant to PINS in folder :/home/mcc/execution
May 18, 2018 10:46:09 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 18, 2018 10:46:26 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 123217 redundant transitions.
May 18, 2018 10:46:26 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 251 ms
May 18, 2018 10:46:27 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 32411 ms.
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-00(UNSAT) depth K=0 took 25 ms
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-01(UNSAT) depth K=0 took 9 ms
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-02(UNSAT) depth K=0 took 11 ms
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-03(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-04(UNSAT) depth K=0 took 24 ms
May 18, 2018 10:46:31 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-05(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-06(UNSAT) depth K=0 took 14 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-07(UNSAT) depth K=0 took 7 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-08(UNSAT) depth K=0 took 14 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-09(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-10(UNSAT) depth K=0 took 161 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-11(UNSAT) depth K=0 took 5 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-12(UNSAT) depth K=0 took 6 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-13(UNSAT) depth K=0 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-14(UNSAT) depth K=0 took 8 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-15(UNSAT) depth K=0 took 12 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-00(UNSAT) depth K=1 took 16 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-01(UNSAT) depth K=1 took 16 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-02(UNSAT) depth K=1 took 1 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-03(UNSAT) depth K=1 took 3 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-04(UNSAT) depth K=1 took 11 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-05(UNSAT) depth K=1 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-06(UNSAT) depth K=1 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-07(UNSAT) depth K=1 took 14 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-08(UNSAT) depth K=1 took 25 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-09(UNSAT) depth K=1 took 12 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-10(UNSAT) depth K=1 took 15 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-11(UNSAT) depth K=1 took 14 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-12(UNSAT) depth K=1 took 15 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-13(UNSAT) depth K=1 took 14 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-14(UNSAT) depth K=1 took 12 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-15(UNSAT) depth K=1 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-00(UNSAT) depth K=2 took 132 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-01(UNSAT) depth K=2 took 9 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-02(UNSAT) depth K=2 took 12 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-03(UNSAT) depth K=2 took 17 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-04(UNSAT) depth K=2 took 22 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-05(UNSAT) depth K=2 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-06(UNSAT) depth K=2 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-07(UNSAT) depth K=2 took 8 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-08(UNSAT) depth K=2 took 14 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-09(UNSAT) depth K=2 took 10 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-10(UNSAT) depth K=2 took 18 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-11(UNSAT) depth K=2 took 12 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-12(UNSAT) depth K=2 took 9 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-13(UNSAT) depth K=2 took 22 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-14(UNSAT) depth K=2 took 11 ms
May 18, 2018 10:46:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-15(UNSAT) depth K=2 took 13 ms
May 18, 2018 10:46:34 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-00(UNSAT) depth K=3 took 1645 ms
May 18, 2018 10:46:36 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-01(UNSAT) depth K=3 took 2311 ms
May 18, 2018 10:46:37 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-02(UNSAT) depth K=3 took 1025 ms
May 18, 2018 10:46:39 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was already deterministic with 33676 transitions.
May 18, 2018 10:46:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-03(UNSAT) depth K=3 took 3560 ms
May 18, 2018 10:46:42 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-04(UNSAT) depth K=3 took 1133 ms
May 18, 2018 10:46:44 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-05(UNSAT) depth K=3 took 2196 ms
May 18, 2018 10:46:46 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-06(UNSAT) depth K=3 took 1576 ms
May 18, 2018 10:46:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-07(UNSAT) depth K=3 took 1790 ms
May 18, 2018 10:46:50 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-08(UNSAT) depth K=3 took 2574 ms
May 18, 2018 10:46:52 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-09(UNSAT) depth K=3 took 1926 ms
May 18, 2018 10:46:53 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 12 place invariants in 244 ms
May 18, 2018 10:46:54 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-10(UNSAT) depth K=3 took 2143 ms
May 18, 2018 10:46:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-11(UNSAT) depth K=3 took 1847 ms
May 18, 2018 10:46:58 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-12(UNSAT) depth K=3 took 1799 ms
May 18, 2018 10:46:59 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-13(UNSAT) depth K=3 took 1463 ms
May 18, 2018 10:47:00 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 87 variables to be positive in 8285 ms
May 18, 2018 10:47:01 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-14(UNSAT) depth K=3 took 1692 ms
May 18, 2018 10:47:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-00
May 18, 2018 10:47:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-00
May 18, 2018 10:47:02 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-00(FALSE) depth K=0 took 1817 ms
May 18, 2018 10:47:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-15(UNSAT) depth K=3 took 2473 ms
May 18, 2018 10:47:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant ARMCacheCoherence-PT-none-ReachabilityCardinality-01
May 18, 2018 10:47:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-01
May 18, 2018 10:47:04 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-01(TRUE) depth K=0 took 1987 ms
May 18, 2018 10:47:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-02
May 18, 2018 10:47:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-02
May 18, 2018 10:47:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-02(FALSE) depth K=0 took 1562 ms
May 18, 2018 10:47:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityCardinality-03
May 18, 2018 10:47:06 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-03(SAT) depth K=0 took 411 ms
May 18, 2018 10:47:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-04
May 18, 2018 10:47:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-04
May 18, 2018 10:47:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-04(FALSE) depth K=0 took 1594 ms
May 18, 2018 10:47:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityCardinality-05
May 18, 2018 10:47:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-05(SAT) depth K=0 took 522 ms
May 18, 2018 10:47:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-06
May 18, 2018 10:47:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-06
May 18, 2018 10:47:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-06(FALSE) depth K=0 took 2160 ms
May 18, 2018 10:47:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant ARMCacheCoherence-PT-none-ReachabilityCardinality-07
May 18, 2018 10:47:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-07
May 18, 2018 10:47:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-07(TRUE) depth K=0 took 2153 ms
May 18, 2018 10:47:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesARMCacheCoherence-PT-none-ReachabilityCardinality-08
May 18, 2018 10:47:13 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-08(SAT) depth K=0 took 677 ms
May 18, 2018 10:47:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-09
May 18, 2018 10:47:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-09
May 18, 2018 10:47:16 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-09(FALSE) depth K=0 took 2197 ms
May 18, 2018 10:47:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-10
May 18, 2018 10:47:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-10
May 18, 2018 10:47:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-10(FALSE) depth K=0 took 2188 ms
May 18, 2018 10:47:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-11
May 18, 2018 10:47:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-11
May 18, 2018 10:47:20 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-11(FALSE) depth K=0 took 2627 ms
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ARMCacheCoherence-PT-none-ReachabilityCardinality-12
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ARMCacheCoherence-PT-none-ReachabilityCardinality-12
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ARMCacheCoherence-PT-none-ReachabilityCardinality-12(FALSE) depth K=0 took 1143 ms
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver checkSat
WARNING: SMT solver unexpectedly returned 'unknown' answer, retrying.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying ARMCacheCoherence-PT-none-ReachabilityCardinality-01 SMT depth 4
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
WARNING: Unexpected error occurred while running SMT. Was verifying ARMCacheCoherence-PT-none-ReachabilityCardinality-13 K-induction depth 0
Exception in thread "Thread-8" java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:336)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an error :unknown
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:318)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.verify(KInductionSolver.java:573)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:301)
... 3 more
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Failed to check-sat")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:305)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 4
May 18, 2018 10:47:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 4
May 18, 2018 10:47:22 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 10/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
pwd
ls -lh

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3637"
echo " Executing tool itstools"
echo " Input is ARMCacheCoherence-PT-none, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r008-qhx2-152646138400005"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;