Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_SharedMemory-PT-000005, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r150-csrt-149443435000322
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-0
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-1
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-10
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-11
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-12
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-13
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-14
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-15
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-2
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-3
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-4
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-5
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-6
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-7
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-8
FORMULA_NAME SharedMemory-COL-000005-ReachabilityCardinality-9

=== Now, execution of the tool begins

BK_START 1496664296391

FORMULA SharedMemory-COL-000005-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-9 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-1 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE

Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-reach command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory\_PT\_000005\_flat\_flat,1863,0.035748,5772,2,593,5,1830,6,0,222,1126,0
Total reachable state count : 1863

Verifying 12 reachability properties.
Invariant property SharedMemory-COL-000005-ReachabilityCardinality-0 is true.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-0,0,0.038215,5852,1,0,5,1830,7,0,244,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-2 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-2 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-2

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-2,0,0.041862,5932,1,0,5,1830,8,0,288,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-3 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-3 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-3

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-3,0,0.050738,6152,1,0,5,1830,9,0,427,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-4 is true.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-4 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-4,1,0.052894,6152,2,42,6,1830,10,0,463,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-5 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-5 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-5

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-5,0,0.055724,6152,1,0,6,1830,11,0,514,1126,0
Invariant property SharedMemory-COL-000005-ReachabilityCardinality-6 is true.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-6 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-6,0,0.062891,6152,1,0,6,1830,12,0,630,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-7 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-7 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-7

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-7,0,0.066819,6152,1,0,6,1830,13,0,697,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-8 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-8 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-8

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-8,0,0.073691,6152,1,0,6,1830,14,0,806,1126,0
Invariant property SharedMemory-COL-000005-ReachabilityCardinality-10 is true.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-10,0,0.078731,6188,1,0,6,1830,15,0,873,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-12 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-12,0,0.084174,6288,1,0,6,2009,16,0,946,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-13 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-13

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-13,0,0.085346,6452,1,0,6,2033,17,0,961,1126,0
Reachability property SharedMemory-COL-000005-ReachabilityCardinality-15 does not hold.
FORMULA SharedMemory-COL-000005-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : SharedMemory-COL-000005-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
SharedMemory-COL-000005-ReachabilityCardinality-15,0,0.105217,6744,1,0,6,3757,18,0,1320,1126,0
Exit code :0

BK_STOP 1496664299075

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityCardinality -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 05, 2017 12:04:57 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 05, 2017 12:04:57 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 57 ms
Jun 05, 2017 12:04:58 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 41 places.
Jun 05, 2017 12:04:58 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 55 transitions.
Jun 05, 2017 12:04:58 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 52 ms
Jun 05, 2017 12:04:58 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 21 ms
Jun 05, 2017 12:04:58 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 9 ms
Jun 05, 2017 12:04:58 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
Jun 05, 2017 12:04:58 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 27 ms
Jun 05, 2017 12:04:58 PM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
Read property : SharedMemory-COL-000005-ReachabilityCardinality-0 with value :((((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)>=1)&&(((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)>=3))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-2 with value :(!((!(((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)<=Ext_Bus))||((((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)<=(((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5))||(Ext_Bus>=1))))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-3 with value :((((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)<=(((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5))&&(((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)>=1)||(((((Queue_1+Queue_2)+Queue_5)+Queue_3)+Queue_4)>=3)))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-4 with value :(!((((((Queue_1+Queue_2)+Queue_5)+Queue_3)+Queue_4)<=((((Active_1+Active_3)+Active_2)+Active_4)+Active_5))||((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)<=((((Active_1+Active_3)+Active_2)+Active_4)+Active_5))))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-5 with value :(((((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)<=((((Queue_1+Queue_2)+Queue_5)+Queue_3)+Queue_4))||(Ext_Bus>=3))||(((((Queue_1+Queue_2)+Queue_5)+Queue_3)+Queue_4)>=3))&&(Ext_Bus>=2))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-6 with value :((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)<=((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-7 with value :((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)>=3)
Read property : SharedMemory-COL-000005-ReachabilityCardinality-8 with value :((((((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)<=Ext_Bus)&&(((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)>=3))&&((((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)<=((((OwnMemAcc_1+OwnMemAcc_4)+OwnMemAcc_5)+OwnMemAcc_2)+OwnMemAcc_3))||(((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)<=((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5))))||(((((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)>=2)||(((((OwnMemAcc_1+OwnMemAcc_4)+OwnMemAcc_5)+OwnMemAcc_2)+OwnMemAcc_3)>=2))&&(!(((((Memory_2+Memory_1)+Memory_4)+Memory_3)+Memory_5)>=2))))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-10 with value :(!((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)>=2))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-12 with value :((((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)>=3)&&(!(((((OwnMemAcc_1+OwnMemAcc_4)+OwnMemAcc_5)+OwnMemAcc_2)+OwnMemAcc_3)<=((((Active_1+Active_3)+Active_2)+Active_4)+Active_5))))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-13 with value :((((((OwnMemAcc_1+OwnMemAcc_4)+OwnMemAcc_5)+OwnMemAcc_2)+OwnMemAcc_3)<=((((Active_1+Active_3)+Active_2)+Active_4)+Active_5))&&((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)>=2))
Read property : SharedMemory-COL-000005-ReachabilityCardinality-15 with value :((((((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)>=3)||(Ext_Bus>=2))||(((((Queue_1+Queue_2)+Queue_5)+Queue_3)+Queue_4)>=1))&&(!(((((((((((((((((((((Ext_Mem_Acc_2_1+Ext_Mem_Acc_3_1)+Ext_Mem_Acc_4_1)+Ext_Mem_Acc_5_1)+Ext_Mem_Acc_1_2)+Ext_Mem_Acc_3_2)+Ext_Mem_Acc_4_2)+Ext_Mem_Acc_5_2)+Ext_Mem_Acc_1_3)+Ext_Mem_Acc_2_3)+Ext_Mem_Acc_4_3)+Ext_Mem_Acc_5_3)+Ext_Mem_Acc_1_4)+Ext_Mem_Acc_3_4)+Ext_Mem_Acc_2_4)+Ext_Mem_Acc_1_5)+Ext_Mem_Acc_5_4)+Ext_Mem_Acc_3_5)+Ext_Mem_Acc_2_5)+Ext_Mem_Acc_4_5)<=((((Active_1+Active_3)+Active_2)+Active_4)+Active_5))||(((((Active_1+Active_3)+Active_2)+Active_4)+Active_5)<=((((Queue_1+Queue_2)+Queue_5)+Queue_3)+Queue_4)))))

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_SharedMemory-PT-000005"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_SharedMemory-PT-000005.tgz
mv S_SharedMemory-PT-000005 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_SharedMemory-PT-000005, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r150-csrt-149443435000322"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;