Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_ResAllocation-PT-R003C020, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r150-csrt-149443434700098
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1496651995452


Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-ctl command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 80 rows 120 cols
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + 1'p_16_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + 1'p_13_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + -1'r_16_2 + 1'r_17_2 + 1'p_18_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + 1'p_8_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + 1'p_15_2= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + -1'r_15_2 + 1'r_16_2 + -1'r_17_2 + 1'r_18_2 + 1'p_19_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + 1'p_11_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + 1'p_11_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + 1'p_10_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + 1'p_7_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + 1'p_12_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + 1'p_15_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + -1'r_16_1 + 1'r_17_1 + -1'r_18_1 + 1'r_19_1= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + 1'p_4_1= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + 1'p_12_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + 1'p_10_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + -1'r_15_0 + 1'r_16_0 + 1'p_17_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + -1'r_16_2 + 1'r_17_2 + -1'r_18_2 + 1'r_19_2= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + 1'p_3_2= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + 1'p_7_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + 1'p_7_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + 1'p_4_0= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + 1'p_6_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + 1'p_2_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + 1'p_6_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + 1'p_1_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + 1'p_13_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + 1'p_16_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + -1'r_16_0 + 1'r_17_0 + -1'r_18_0 + 1'r_19_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + 1'p_14_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + 1'p_5_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + 1'p_2_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + 1'p_3_1= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + -1'r_15_1 + 1'r_16_1 + 1'p_17_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + -1'r_15_0 + 1'r_16_0 + -1'r_17_0 + 1'r_18_0 + 1'p_19_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + 1'p_6_2= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + -1'r_16_1 + 1'r_17_1 + 1'p_18_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + 1'p_5_2= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + -1'r_15_2 + 1'r_16_2 + 1'p_17_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + 1'p_8_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + 1'p_12_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + 1'p_3_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + 1'p_9_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + 1'p_1_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + -1'r_15_1 + 1'r_16_1 + -1'r_17_1 + 1'r_18_1 + 1'p_19_1= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + 1'p_2_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + 1'p_1_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + 1'p_9_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + 1'p_10_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + 1'p_13_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + -1'r_16_0 + 1'r_17_0 + 1'p_18_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + 1'p_5_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + 1'p_11_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + 1'p_14_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + 1'p_8_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + 1'p_9_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + 1'p_16_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + 1'p_15_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + 1'p_14_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + 1'p_4_2= 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
Exit code :0
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Exit code :0
Exit code :1
FORMULA ResAllocation-PT-R003C020-ReachabilityDeadlock-0 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Detected timeout of ITS tools.

BK_STOP 1496652002336

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityDeadlock = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 71 ms
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 120 places.
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 80 transitions.
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.logic.togal.ToGalTransformer toGal
WARNING: Unknown predicate type in boolean expression fr.lip6.move.gal.logic.impl.DeadlockImpl
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property ResAllocation-PT-R003C020-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 89 ms
Jun 05, 2017 8:39:57 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 14 ms
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 60 place invariants in 23 ms
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 120 variables to be positive in 552 ms
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 80 transitions.
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/80 took 3 ms. Total solver calls (SAT/UNSAT): 4(2/2)
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 207 ms. Total solver calls (SAT/UNSAT): 428(194/234)
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 80 transitions.
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 219 ms. Total solver calls (SAT/UNSAT): 428(158/270)
Jun 05, 2017 8:39:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 80 transitions.
Jun 05, 2017 8:39:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of enabling matrix(52/80) took 1004 ms. Total solver calls (SAT/UNSAT): 2862(2676/186)
Jun 05, 2017 8:40:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished enabling matrix. took 1128 ms. Total solver calls (SAT/UNSAT): 3240(2967/273)
Jun 05, 2017 8:40:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 80 transitions.
Jun 05, 2017 8:40:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 05, 2017 8:40:00 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 2398ms conformant to PINS in folder :/home/mcc/execution
Jun 05, 2017 8:40:02 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-seq, ./gal.so, -p, --pins-guards, --when, -d], workingDir=/home/mcc/execution]
pins2lts-seq, 0.000: Registering PINS so language module
pins2lts-seq, 0.001: Loading model from ./gal.so
pins2lts-seq, 0.001: library has no initializer
pins2lts-seq, 0.001: loading model GAL
pins2lts-seq, 0.002: completed loading model GAL
pins2lts-seq, 0.002: Initializing POR dependencies: labels 81, guards 80
pins2lts-seq, 0.013: There are 81 state labels and 1 edge labels
pins2lts-seq, 0.013: State length is 120, there are 80 groups
pins2lts-seq, 0.013: Running dfs search strategy
pins2lts-seq, 0.013: Using a tree for state storage
pins2lts-seq, 0.013: Visible groups: 0 / 80, labels: 0 / 81
pins2lts-seq, 0.013: POR cycle proviso: none
pins2lts-seq, 0.019:
pins2lts-seq, 0.019: deadlock () found at depth 41!
pins2lts-seq, 0.019:
pins2lts-seq, 0.019: exiting now

Jun 05, 2017 8:40:02 AM fr.lip6.move.gal.itstools.ProcessController$1 run
WARNING: null
Jun 05, 2017 8:40:02 AM fr.lip6.move.gal.itstools.ProcessController forwardStream
WARNING: Stream closed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_ResAllocation-PT-R003C020"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_ResAllocation-PT-R003C020.tgz
mv S_ResAllocation-PT-R003C020 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_ResAllocation-PT-R003C020, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r150-csrt-149443434700098"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;