Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.............................................................
=====================================================================
Generated by BenchKit 2-3254
Executing tool lola
Input is S_Peterson-PT-4, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r128-smll-149441681100061
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-0
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-1
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-10
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-11
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-12
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-13
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-14
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-15
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-2
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-3
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-4
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-5
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-6
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-7
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-8
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-9

=== Now, execution of the tool begins

BK_START 1496271706805


Time: 3600 - MCC
----- Start make prepare stdout -----
===========================================================================================
S_Peterson-PT-4: translating PT Petri net model.pnml into LoLA format
===========================================================================================
translating PT Petri net complete


checking for too many tokens
===========================================================================================
S_Peterson-PT-4: translating PT formula ReachabilityCardinality into LoLA format
===========================================================================================
translating formula complete
touch formulae;
----- Start make result stdout -----
ReachabilityCardinality @ S_Peterson-PT-4 @ 3540 seconds
----- Start make result stdout -----
lola: LoLA will run for 3540 seconds at most (--timelimit)
lola: NET
lola: reading net from model.pnml.lola
lola: finished parsing
lola: closed net file model.pnml.lola
lola: 1170/65536 symbol table entries, 0 collisions
lola: preprocessing...
lola: finding significant places
lola: 480 places, 690 transitions, 461 significant places
lola: computing forward-conflicting sets
lola: computing back-conflicting sets
lola: 1055 transition conflict sets
lola: TASK
lola: reading formula from Peterson-COL-4-ReachabilityCardinality.task
lola: A (G (TRUE)) : E (F (((2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3) AND (1 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) AND (TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 <= 0) AND ((Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4 <= 2) OR (BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0 <= 2))))) : A (G (((2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3)))) : A (G ((CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4))) : A (G (((AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR ((1 <= WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F) AND (Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4)) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2)))) : A (G (TRUE)) : A (G (((EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3 <= 1) OR (WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 0) OR (TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4)))) : E (F (((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 0) AND ((2 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4) OR (IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3)) AND ((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) OR (2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3) OR (TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4))))) : E (F ((((2 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) OR ((3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) AND (AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4))) AND (Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4)))) : E (F (((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + 1 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4) AND (WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4)))) : E (F (())) : A (G ((((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= 2) OR (IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 <= 1)) AND ((TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4) OR (TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 <= BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0) OR ((AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F) AND (3 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3)))))) : E (F (((BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0 + 1 <= AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2) AND (AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 + 1 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) AND (2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3)))) : A (G ((((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0) AND (2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3)) OR (TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3 + 1 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4)))) : E (F ((3 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4))) : E (F (((((1 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4) AND (3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3)) OR (Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4)) AND (AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F))))
lola: computing a collection of formulas
lola: RUNNING
lola: subprocess 0 will run for 221 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (TRUE))
lola: ========================================
lola: SUBTASK
lola: checking initial satisfaction
lola: processed formula: TRUE
lola: processed formula length: 4
lola: 3 rewrites
lola: formula mentions 0 of 480 places; total mentions: 0
lola: closed formula file Peterson-COL-4-ReachabilityCardinality.task
lola: processed formula with 0 atomic propositions
lola: RUNNING
lola: SUBRESULT
lola: result: yes
lola: produced by: preprocessing
lola: The net satisfies the property already in its initial state.
lola: ========================================
lola: subprocess 1 will run for 236 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3) AND (1 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlon... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 8 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality.sara
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 2 will run for 252 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (((2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + T... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 2 literals and 1 conjunctive subformulas
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is invariant.
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-2.sara
lola: ========================================
lola: subprocess 3 will run for 272 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G ((CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + ... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 1 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-3.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-3.sara.
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 4 will run for 294 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (((AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSectio... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 8 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-4.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-4.sara.
sara: place or transition ordering is non-deterministic

lola: state equation: solution impossible
lola: SUBRESULT
lola: result: yes
lola: produced by: state equation
lola: The predicate is invariant.
lola: ========================================
lola: subprocess 5 will run for 321 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (TRUE))
lola: ========================================
lola: SUBTASK
lola: checking initial satisfaction
lola: processed formula: TRUE
lola: processed formula length: 4
lola: 3 rewrites
lola: formula mentions 0 of 480 places; total mentions: 0
lola: closed formula file Peterson-COL-4-ReachabilityCardinality.task
lola: processed formula with 0 atomic propositions
lola: RUNNING
lola: SUBRESULT
lola: result: yes
lola: produced by: preprocessing
lola: The net satisfies the property already in its initial state.
lola: ========================================
lola: subprocess 6 will run for 353 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (((EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3 <= 1) OR (WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 3 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-6.sara
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 7 will run for 393 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 0) AND ((2 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 +... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 18 literals and 6 conjunctive subformulas
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is unreachable.
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-7.sara
lola: subprocess 8 will run for 442 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ========================================
lola: ...considering subproblem: E (F ((((2 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlon... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 5 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-8.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-8.sara.
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 9 will run for 505 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + 1 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + Tes... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 2 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-9.sara
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 10 will run for 589 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (()))
lola: ========================================
lola: SUBTASK
lola: checking initial satisfaction
lola: processed formula: FALSE
lola: processed formula length: 5
lola: 3 rewrites
lola: formula mentions 0 of 480 places; total mentions: 0
lola: closed formula file Peterson-COL-4-ReachabilityCardinality.task
lola: processed formula with 0 atomic propositions
lola: RUNNING
lola: SUBRESULT
lola: result: no
lola: produced by: preprocessing
lola: The net violates the given property already in its initial state.
lola: ========================================
lola: subprocess 11 will run for 707 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G ((((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= 2) OR (IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 8 literals and 3 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-11.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-11.sara.
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 12 will run for 884 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 3 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-12.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-12.sara.
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 13 will run for 1179 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G ((((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 6 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-13.sara
lola: lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 14 will run for 1769 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F ((3 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4)))
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 1 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-14.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-14.sara.
sara: place or transition ordering is non-deterministic
lola: sara is running 0 secs || 175915 markings, 629555 edges, 35183 markings/sec, 0 secs
lola: sara is running 5 secs || 342132 markings, 1291250 edges, 33243 markings/sec, 5 secs
lola: sara is running 10 secs || 509621 markings, 1926647 edges, 33498 markings/sec, 10 secs
sara: warning, failure of lp_solve (at job 1894)
lola: sara is running 15 secs || 677426 markings, 2553519 edges, 33561 markings/sec, 15 secs
lola: sara is running 20 secs || 839014 markings, 3194446 edges, 32318 markings/sec, 20 secs
lola: sara is running 25 secs || 1004013 markings, 3815877 edges, 33000 markings/sec, 25 secs
lola: sara is running 30 secs || 1168260 markings, 4442451 edges, 32849 markings/sec, 30 secs
lola: sara is running 35 secs || 1327590 markings, 5072746 edges, 31866 markings/sec, 35 secs
lola: sara is running 40 secs || 1490114 markings, 5700023 edges, 32505 markings/sec, 40 secs
lola: sara is running 45 secs || 1651038 markings, 6303427 edges, 32185 markings/sec, 45 secs
lola: sara is running 50 secs || 1810627 markings, 6923530 edges, 31918 markings/sec, 50 secs
lola: sara is running 55 secs || 1969375 markings, 7537545 edges, 31750 markings/sec, 55 secs
lola: sara is running 60 secs || 2126381 markings, 8174128 edges, 31401 markings/sec, 60 secs
lola: sara is running 65 secs || 2282143 markings, 8763242 edges, 31152 markings/sec, 65 secs
lola: sara is running 70 secs || 2439927 markings, 9364129 edges, 31557 markings/sec, 70 secs
lola: sara is running 75 secs || 2595211 markings, 10030666 edges, 31057 markings/sec, 75 secs
lola: sara is running 80 secs || 2753109 markings, 10626609 edges, 31580 markings/sec, 80 secs
lola: sara is running 85 secs || 2908322 markings, 11223680 edges, 31043 markings/sec, 85 secs
lola: sara is running 90 secs || 3066340 markings, 11797326 edges, 31604 markings/sec, 90 secs
lola: sara is running 95 secs || 3222196 markings, 12396470 edges, 31171 markings/sec, 95 secs
lola: sara is running 100 secs || 3378147 markings, 13024126 edges, 31190 markings/sec, 100 secs
lola: sara is running 105 secs || 3534625 markings, 13640877 edges, 31296 markings/sec, 105 secs
lola: sara is running 110 secs || 3687965 markings, 14269454 edges, 30668 markings/sec, 110 secs
lola: sara is running 115 secs || 3845295 markings, 14905192 edges, 31466 markings/sec, 115 secs
lola: sara is running 120 secs || 3997993 markings, 15521156 edges, 30540 markings/sec, 120 secs
lola: sara is running 125 secs || 4150507 markings, 16141860 edges, 30503 markings/sec, 125 secs
lola: sara is running 130 secs || 4306687 markings, 16782969 edges, 31236 markings/sec, 130 secs
lola: sara is running 135 secs || 4462153 markings, 17376642 edges, 31093 markings/sec, 135 secs
lola: sara is running 140 secs || 4600500 markings, 17927765 edges, 27669 markings/sec, 140 secs
lola: sara is running 145 secs || 4744578 markings, 18486323 edges, 28816 markings/sec, 145 secs
lola: sara is running 150 secs || 4889400 markings, 19067092 edges, 28964 markings/sec, 150 secs
lola: sara is running 155 secs || 5046033 markings, 19726844 edges, 31327 markings/sec, 155 secs
lola: sara is running 160 secs || 5204387 markings, 20385307 edges, 31671 markings/sec, 160 secs
lola: sara is running 165 secs || 5365995 markings, 21031076 edges, 32322 markings/sec, 165 secs
lola: sara is running 170 secs || 5517657 markings, 21638978 edges, 30332 markings/sec, 170 secs
lola: sara is running 175 secs || 5669216 markings, 22257942 edges, 30312 markings/sec, 175 secs
lola: sara is running 180 secs || 5815220 markings, 22884571 edges, 29201 markings/sec, 180 secs
lola: sara is running 185 secs || 5966326 markings, 23517740 edges, 30221 markings/sec, 185 secs
lola: sara is running 190 secs || 6122878 markings, 24130226 edges, 31310 markings/sec, 190 secs
lola: sara is running 195 secs || 6275801 markings, 24759318 edges, 30585 markings/sec, 195 secs
lola: sara is running 200 secs || 6436894 markings, 25368431 edges, 32219 markings/sec, 200 secs
lola: sara is running 205 secs || 6598911 markings, 25985560 edges, 32403 markings/sec, 205 secs
lola: sara is running 210 secs || 6756585 markings, 26586462 edges, 31535 markings/sec, 210 secs
lola: sara is running 215 secs || 6911203 markings, 27182796 edges, 30924 markings/sec, 215 secs
lola: sara is running 220 secs || 7066987 markings, 27812311 edges, 31157 markings/sec, 220 secs
lola: sara is running 225 secs || 7219519 markings, 28419545 edges, 30506 markings/sec, 225 secs
lola: sara is running 230 secs || 7367099 markings, 29008841 edges, 29516 markings/sec, 230 secs
lola: sara is running 235 secs || 7519771 markings, 29611359 edges, 30534 markings/sec, 235 secs
lola: sara is running 240 secs || 7667991 markings, 30213852 edges, 29644 markings/sec, 240 secs
lola: sara is running 245 secs || 7817946 markings, 30804830 edges, 29991 markings/sec, 245 secs
lola: sara is running 250 secs || 7970321 markings, 31434423 edges, 30475 markings/sec, 250 secs
lola: sara is running 255 secs || 8119413 markings, 32047270 edges, 29818 markings/sec, 255 secs
lola: sara is running 260 secs || 8271395 markings, 32675540 edges, 30396 markings/sec, 260 secs
lola: sara is running 265 secs || 8424063 markings, 33282288 edges, 30534 markings/sec, 265 secs
lola: sara is running 270 secs || 8569687 markings, 33872891 edges, 29125 markings/sec, 270 secs
lola: sara is running 275 secs || 8707972 markings, 34453966 edges, 27657 markings/sec, 275 secs
lola: sara is running 280 secs || 8851075 markings, 35019142 edges, 28621 markings/sec, 280 secs
lola: sara is running 285 secs || 8995107 markings, 35612590 edges, 28806 markings/sec, 285 secs
lola: sara is running 290 secs || 9139366 markings, 36216101 edges, 28852 markings/sec, 290 secs
lola: sara is running 295 secs || 9290573 markings, 36797662 edges, 30241 markings/sec, 295 secs
lola: sara is running 300 secs || 9439350 markings, 37363231 edges, 29755 markings/sec, 300 secs
lola: sara is running 305 secs || 9583218 markings, 37932702 edges, 28774 markings/sec, 305 secs
lola: sara is running 310 secs || 9730892 markings, 38475984 edges, 29535 markings/sec, 310 secs
lola: sara is running 315 secs || 9876223 markings, 39052901 edges, 29066 markings/sec, 315 secs
lola: sara is running 320 secs || 10026892 markings, 39647568 edges, 30134 markings/sec, 320 secs
lola: sara is running 325 secs || 10174398 markings, 40237741 edges, 29501 markings/sec, 325 secs
lola: sara is running 330 secs || 10321165 markings, 40833272 edges, 29353 markings/sec, 330 secs
lola: sara is running 335 secs || 10466297 markings, 41441619 edges, 29026 markings/sec, 335 secs
lola: sara is running 340 secs || 10606573 markings, 42056434 edges, 28055 markings/sec, 340 secs
lola: sara is running 345 secs || 10740740 markings, 42676094 edges, 26833 markings/sec, 345 secs
lola: sara is running 350 secs || 10889962 markings, 43281472 edges, 29844 markings/sec, 350 secs
lola: sara is running 355 secs || 11034728 markings, 43873790 edges, 28953 markings/sec, 355 secs
lola: sara is running 360 secs || 11175495 markings, 44463466 edges, 28153 markings/sec, 360 secs
lola: sara is running 365 secs || 11315042 markings, 45067708 edges, 27909 markings/sec, 365 secs
lola: sara is running 370 secs || 11458495 markings, 45690356 edges, 28691 markings/sec, 370 secs
lola: sara is running 375 secs || 11604591 markings, 46253415 edges, 29219 markings/sec, 375 secs
lola: sara is running 380 secs || 11745488 markings, 46804260 edges, 28179 markings/sec, 380 secs
lola: sara is running 385 secs || 11887748 markings, 47357056 edges, 28452 markings/sec, 385 secs
lola: sara is running 390 secs || 12027866 markings, 47918077 edges, 28024 markings/sec, 390 secs
lola: sara is running 395 secs || 12166748 markings, 48522102 edges, 27776 markings/sec, 395 secs
lola: sara is running 400 secs || 12308758 markings, 49107217 edges, 28402 markings/sec, 400 secs
lola: sara is running 405 secs || 12451698 markings, 49670041 edges, 28588 markings/sec, 405 secs
lola: sara is running 410 secs || 12594574 markings, 50223886 edges, 28575 markings/sec, 410 secs
lola: sara is running 415 secs || 12740627 markings, 50771620 edges, 29211 markings/sec, 415 secs
lola: sara is running 420 secs || 12881726 markings, 51347847 edges, 28220 markings/sec, 420 secs
lola: sara is running 425 secs || 13022572 markings, 51944470 edges, 28169 markings/sec, 425 secs
lola: sara is running 430 secs || 13163977 markings, 52517032 edges, 28281 markings/sec, 430 secs
lola: sara is running 435 secs || 13304847 markings, 53106427 edges, 28174 markings/sec, 435 secs
lola: sara is running 440 secs || 13442284 markings, 53697353 edges, 27487 markings/sec, 440 secs
lola: sara is running 445 secs || 13575970 markings, 54298190 edges, 26737 markings/sec, 445 secs
lola: sara is running 450 secs || 13705628 markings, 54896934 edges, 25932 markings/sec, 450 secs
lola: sara is running 455 secs || 13837628 markings, 55507948 edges, 26400 markings/sec, 455 secs
lola: sara is running 460 secs || 13979723 markings, 56061910 edges, 28419 markings/sec, 460 secs
lola: sara is running 465 secs || 14117598 markings, 56613118 edges, 27575 markings/sec, 465 secs
lola: sara is running 470 secs || 14253995 markings, 57169452 edges, 27279 markings/sec, 470 secs
lola: sara is running 475 secs || 14393049 markings, 57741803 edges, 27811 markings/sec, 475 secs
lola: sara is running 480 secs || 14536318 markings, 58300565 edges, 28654 markings/sec, 480 secs
lola: sara is running 485 secs || 14675603 markings, 58856208 edges, 27857 markings/sec, 485 secs
lola: sara is running 490 secs || 14817820 markings, 59408111 edges, 28443 markings/sec, 490 secs
lola: sara is running 495 secs || 14956713 markings, 59996465 edges, 27779 markings/sec, 495 secs
lola: sara is running 500 secs || 15093741 markings, 60617971 edges, 27406 markings/sec, 500 secs
lola: sara is running 505 secs || 15230461 markings, 61187000 edges, 27344 markings/sec, 505 secs
lola: sara is running 510 secs || 15370120 markings, 61753267 edges, 27932 markings/sec, 510 secs
lola: sara is running 515 secs || 15513728 markings, 62328739 edges, 28722 markings/sec, 515 secs
lola: sara is running 520 secs || 15653644 markings, 62897876 edges, 27983 markings/sec, 520 secs
lola: sara is running 525 secs || 15792031 markings, 63452727 edges, 27677 markings/sec, 525 secs
lola: sara is running 530 secs || 15931470 markings, 63988154 edges, 27888 markings/sec, 530 secs
lola: sara is running 535 secs || 16076187 markings, 64542175 edges, 28943 markings/sec, 535 secs
lola: sara is running 540 secs || 16213520 markings, 65105073 edges, 27467 markings/sec, 540 secs
lola: sara is running 545 secs || 16351450 markings, 65673114 edges, 27586 markings/sec, 545 secs
lola: sara is running 550 secs || 16485219 markings, 66253530 edges, 26754 markings/sec, 550 secs
lola: sara is running 555 secs || 16618721 markings, 66847640 edges, 26700 markings/sec, 555 secs
lola: sara is running 560 secs || 16751180 markings, 67446766 edges, 26492 markings/sec, 560 secs
lola: sara is running 565 secs || 16894822 markings, 68040118 edges, 28728 markings/sec, 565 secs
lola: sara is running 570 secs || 17027263 markings, 68648726 edges, 26488 markings/sec, 570 secs
lola: sara is running 575 secs || 17165504 markings, 69204355 edges, 27648 markings/sec, 575 secs
lola: sara is running 580 secs || 17309352 markings, 69754123 edges, 28770 markings/sec, 580 secs
lola: sara is running 585 secs || 17446649 markings, 70299938 edges, 27459 markings/sec, 585 secs
lola: sara is running 590 secs || 17582849 markings, 70830783 edges, 27240 markings/sec, 590 secs
lola: sara is running 595 secs || 17712217 markings, 71382294 edges, 25874 markings/sec, 595 secs
lola: sara is running 600 secs || 17850766 markings, 71928221 edges, 27710 markings/sec, 600 secs
lola: sara is running 605 secs || 17990974 markings, 72471390 edges, 28042 markings/sec, 605 secs
lola: sara is running 610 secs || 18129990 markings, 73011081 edges, 27803 markings/sec, 610 secs
lola: sara is running 615 secs || 18262226 markings, 73549700 edges, 26447 markings/sec, 615 secs
lola: sara is running 620 secs || 18388083 markings, 74112766 edges, 25171 markings/sec, 620 secs
lola: sara is running 625 secs || 18524224 markings, 74658807 edges, 27228 markings/sec, 625 secs
lola: sara is running 630 secs || 18659972 markings, 75199008 edges, 27150 markings/sec, 630 secs
lola: sara is running 635 secs || 18790317 markings, 75741990 edges, 26069 markings/sec, 635 secs
lola: sara is running 640 secs || 18927910 markings, 76287481 edges, 27519 markings/sec, 640 secs
lola: sara is running 645 secs || 19062053 markings, 76828696 edges, 26829 markings/sec, 645 secs
lola: sara is running 650 secs || 19198711 markings, 77379061 edges, 27332 markings/sec, 650 secs
lola: sara is running 655 secs || 19336562 markings, 77925551 edges, 27570 markings/sec, 655 secs
lola: sara is running 660 secs || 19485741 markings, 78477796 edges, 29836 markings/sec, 660 secs
lola: sara is running 665 secs || 19631952 markings, 79039362 edges, 29242 markings/sec, 665 secs
lola: sara is running 670 secs || 19771924 markings, 79604311 edges, 27994 markings/sec, 670 secs
lola: sara is running 675 secs || 19911250 markings, 80138486 edges, 27865 markings/sec, 675 secs
lola: sara is running 680 secs || 20050428 markings, 80652932 edges, 27836 markings/sec, 680 secs
lola: sara is running 685 secs || 20176929 markings, 81172277 edges, 25300 markings/sec, 685 secs
lola: sara is running 690 secs || 20315208 markings, 81681706 edges, 27656 markings/sec, 690 secs
lola: sara is running 695 secs || 20448033 markings, 82223342 edges, 26565 markings/sec, 695 secs
lola: sara is running 700 secs || 20583427 markings, 82796238 edges, 27079 markings/sec, 700 secs
lola: sara is running 705 secs || 20718612 markings, 83341579 edges, 27037 markings/sec, 705 secs
lola: sara is running 710 secs || 20856460 markings, 83892121 edges, 27570 markings/sec, 710 secs
lola: sara is running 715 secs || 20990112 markings, 84424642 edges, 26730 markings/sec, 715 secs
lola: sara is running 720 secs || 21116677 markings, 84958461 edges, 25313 markings/sec, 720 secs
lola: sara is running 725 secs || 21248604 markings, 85469255 edges, 26385 markings/sec, 725 secs
lola: sara is running 730 secs || 21380656 markings, 85999612 edges, 26410 markings/sec, 730 secs
lola: sara is running 735 secs || 21510552 markings, 86545655 edges, 25979 markings/sec, 735 secs
lola: sara is running 740 secs || 21640283 markings, 87062236 edges, 25946 markings/sec, 740 secs
lola: sara is running 745 secs || 21762460 markings, 87577522 edges, 24435 markings/sec, 745 secs
lola: sara is running 750 secs || 21901285 markings, 88120697 edges, 27765 markings/sec, 750 secs
lola: sara is running 755 secs || 22047735 markings, 88668368 edges, 29290 markings/sec, 755 secs
lola: sara is running 760 secs || 22189865 markings, 89224186 edges, 28426 markings/sec, 760 secs
lola: sara is running 765 secs || 22329703 markings, 89776371 edges, 27968 markings/sec, 765 secs
lola: sara is running 770 secs || 22461982 markings, 90323176 edges, 26456 markings/sec, 770 secs
lola: sara is running 775 secs || 22592818 markings, 90882193 edges, 26167 markings/sec, 775 secs
lola: sara is running 780 secs || 22726481 markings, 91379284 edges, 26733 markings/sec, 780 secs
lola: sara is running 785 secs || 22859421 markings, 91880481 edges, 26588 markings/sec, 785 secs
lola: sara is running 790 secs || 22987717 markings, 92383542 edges, 25659 markings/sec, 790 secs
lola: sara is running 795 secs || 23110730 markings, 92884110 edges, 24603 markings/sec, 795 secs
lola: sara is running 800 secs || 23221680 markings, 93361721 edges, 22190 markings/sec, 800 secs
lola: sara is running 805 secs || 23225944 markings, 93379788 edges, 853 markings/sec, 805 secs
lola: sara is running 810 secs || 23229408 markings, 93394339 edges, 693 markings/sec, 810 secs
lola: sara is running 815 secs || 23232440 markings, 93407211 edges, 606 markings/sec, 815 secs
lola: sara is running 820 secs || 23232548 markings, 93407635 edges, 22 markings/sec, 820 secs
lola: sara is running 825 secs || 23232597 markings, 93407837 edges, 10 markings/sec, 825 secs
lola: sara is running 830 secs || 23233360 markings, 93411103 edges, 153 markings/sec, 830 secs
lola: sara is running 835 secs || 23233607 markings, 93412141 edges, 49 markings/sec, 835 secs
lola: sara is running 840 secs || 23233901 markings, 93413415 edges, 59 markings/sec, 840 secs
lola: sara is running 845 secs || 23233937 markings, 93413564 edges, 7 markings/sec, 845 secs
lola: sara is running 850 secs || 23235546 markings, 93420144 edges, 322 markings/sec, 850 secs
lola: sara is running 855 secs || 23241806 markings, 93444371 edges, 1252 markings/sec, 855 secs
lola: sara is running 860 secs || 23241905 markings, 93444816 edges, 20 markings/sec, 860 secs
lola: sara is running 865 secs || 23244022 markings, 93452868 edges, 423 markings/sec, 865 secs
lola: sara is running 870 secs || 23278958 markings, 93587496 edges, 6987 markings/sec, 870 secs
lola: sara is running 875 secs || 23414834 markings, 94169737 edges, 27175 markings/sec, 875 secs
lola: sara is running 880 secs || 23567594 markings, 94764807 edges, 30552 markings/sec, 880 secs
lola: sara is running 885 secs || 23704431 markings, 95341126 edges, 27367 markings/sec, 885 secs
lola: sara is running 890 secs || 23837517 markings, 95867834 edges, 26617 markings/sec, 890 secs
lola: sara is running 895 secs || 23963116 markings, 96392871 edges, 25120 markings/sec, 895 secs
lola: sara is running 900 secs || 24100425 markings, 96965858 edges, 27462 markings/sec, 900 secs
lola: sara is running 905 secs || 24240547 markings, 97540529 edges, 28024 markings/sec, 905 secs
lola: sara is running 910 secs || 24376795 markings, 98143697 edges, 27250 markings/sec, 910 secs
lola: sara is running 915 secs || 24509457 markings, 98730337 edges, 26532 markings/sec, 915 secs
lola: sara is running 920 secs || 24635582 markings, 99291128 edges, 25225 markings/sec, 920 secs
lola: sara is running 925 secs || 24767142 markings, 99847811 edges, 26312 markings/sec, 925 secs
lola: sara is running 930 secs || 24892964 markings, 100355117 edges, 25164 markings/sec, 930 secs
lola: sara is running 935 secs || 25019425 markings, 100862834 edges, 25292 markings/sec, 935 secs
lola: sara is running 940 secs || 25145316 markings, 101391795 edges, 25178 markings/sec, 940 secs
lola: sara is running 945 secs || 25269773 markings, 101923019 edges, 24891 markings/sec, 945 secs
lola: sara is running 950 secs || 25388562 markings, 102430341 edges, 23758 markings/sec, 950 secs
lola: sara is running 955 secs || 25509088 markings, 102902372 edges, 24105 markings/sec, 955 secs
lola: sara is running 960 secs || 25640320 markings, 103403735 edges, 26246 markings/sec, 960 secs
lola: sara is running 965 secs || 25769337 markings, 103898638 edges, 25803 markings/sec, 965 secs
lola: sara is running 970 secs || 25891819 markings, 104392764 edges, 24496 markings/sec, 970 secs
lola: sara is running 975 secs || 26015109 markings, 104909856 edges, 24658 markings/sec, 975 secs
lola: sara is running 980 secs || 26135778 markings, 105409206 edges, 24134 markings/sec, 980 secs
lola: sara is running 985 secs || 26257551 markings, 105926084 edges, 24355 markings/sec, 985 secs
lola: sara is running 990 secs || 26385644 markings, 106465072 edges, 25619 markings/sec, 990 secs
lola: sara is running 995 secs || 26545401 markings, 107124118 edges, 31951 markings/sec, 995 secs
lola: sara is running 1000 secs || 26681933 markings, 107708246 edges, 27306 markings/sec, 1000 secs
lola: sara is running 1005 secs || 26825397 markings, 108267618 edges, 28693 markings/sec, 1005 secs
lola: sara is running 1010 secs || 26974721 markings, 108849423 edges, 29865 markings/sec, 1010 secs
lola: sara is running 1015 secs || 27126684 markings, 109439809 edges, 30393 markings/sec, 1015 secs
lola: sara is running 1020 secs || 27278045 markings, 110028455 edges, 30272 markings/sec, 1020 secs
lola: sara is running 1025 secs || 27431745 markings, 110642660 edges, 30740 markings/sec, 1025 secs
lola: sara is running 1030 secs || 27586102 markings, 111264205 edges, 30871 markings/sec, 1030 secs
lola: sara is running 1035 secs || 27732680 markings, 111880815 edges, 29316 markings/sec, 1035 secs
lola: sara is running 1040 secs || 27881275 markings, 112490240 edges, 29719 markings/sec, 1040 secs
lola: sara is running 1045 secs || 28025721 markings, 113132708 edges, 28889 markings/sec, 1045 secs
lola: sara is running 1050 secs || 28168763 markings, 113741111 edges, 28608 markings/sec, 1050 secs
lola: sara is running 1055 secs || 28313285 markings, 114332494 edges, 28904 markings/sec, 1055 secs
lola: sara is running 1060 secs || 28451245 markings, 114940018 edges, 27592 markings/sec, 1060 secs
lola: sara is running 1065 secs || 28582978 markings, 115498743 edges, 26347 markings/sec, 1065 secs
lola: sara is running 1070 secs || 28713923 markings, 116078599 edges, 26189 markings/sec, 1070 secs
lola: sara is running 1075 secs || 28847963 markings, 116636846 edges, 26808 markings/sec, 1075 secs
lola: sara is running 1080 secs || 28984804 markings, 117192235 edges, 27368 markings/sec, 1080 secs
lola: sara is running 1085 secs || 29128291 markings, 117746764 edges, 28697 markings/sec, 1085 secs
lola: sara is running 1090 secs || 29271733 markings, 118292513 edges, 28688 markings/sec, 1090 secs
lola: sara is running 1095 secs || 29413414 markings, 118858031 edges, 28336 markings/sec, 1095 secs
lola: sara is running 1100 secs || 29551694 markings, 119429151 edges, 27656 markings/sec, 1100 secs
lola: sara is running 1105 secs || 29687745 markings, 120013127 edges, 27210 markings/sec, 1105 secs
lola: sara is running 1110 secs || 29822466 markings, 120578520 edges, 26944 markings/sec, 1110 secs
lola: sara is running 1115 secs || 29957062 markings, 121117823 edges, 26919 markings/sec, 1115 secs
lola: sara is running 1120 secs || 30098861 markings, 121661148 edges, 28360 markings/sec, 1120 secs
lola: sara is running 1125 secs || 30239949 markings, 122202587 edges, 28218 markings/sec, 1125 secs
lola: sara is running 1130 secs || 30375324 markings, 122749411 edges, 27075 markings/sec, 1130 secs
lola: sara is running 1135 secs || 30520150 markings, 123353403 edges, 28965 markings/sec, 1135 secs
lola: sara is running 1140 secs || 30664898 markings, 123963607 edges, 28950 markings/sec, 1140 secs
lola: sara is running 1145 secs || 30809110 markings, 124567354 edges, 28842 markings/sec, 1145 secs
lola: sara is running 1150 secs || 30968729 markings, 125211453 edges, 31924 markings/sec, 1150 secs
lola: sara is running 1155 secs || 31130166 markings, 125842110 edges, 32287 markings/sec, 1155 secs
lola: sara is running 1160 secs || 31282689 markings, 126485814 edges, 30505 markings/sec, 1160 secs
lola: sara is running 1165 secs || 31429243 markings, 127121318 edges, 29311 markings/sec, 1165 secs
lola: sara is running 1170 secs || 31584061 markings, 127750932 edges, 30964 markings/sec, 1170 secs
lola: sara is running 1175 secs || 31736134 markings, 128370913 edges, 30415 markings/sec, 1175 secs
lola: sara is running 1180 secs || 31882251 markings, 128995128 edges, 29223 markings/sec, 1180 secs
lola: sara is running 1185 secs || 32035797 markings, 129640032 edges, 30709 markings/sec, 1185 secs
lola: sara is running 1190 secs || 32190716 markings, 130230884 edges, 30984 markings/sec, 1190 secs
lola: sara is running 1195 secs || 32339708 markings, 130813556 edges, 29798 markings/sec, 1195 secs
lola: sara is running 1200 secs || 32490129 markings, 131391090 edges, 30084 markings/sec, 1200 secs
lola: sara is running 1205 secs || 32639777 markings, 131996754 edges, 29930 markings/sec, 1205 secs
lola: sara is running 1210 secs || 32788740 markings, 132638941 edges, 29793 markings/sec, 1210 secs
lola: sara is running 1215 secs || 32939262 markings, 133240029 edges, 30104 markings/sec, 1215 secs
lola: sara is running 1220 secs || 33087904 markings, 133844593 edges, 29728 markings/sec, 1220 secs
lola: sara is running 1225 secs || 33232619 markings, 134443405 edges, 28943 markings/sec, 1225 secs
lola: sara is running 1230 secs || 33377734 markings, 135004749 edges, 29023 markings/sec, 1230 secs
lola: sara is running 1235 secs || 33520804 markings, 135613551 edges, 28614 markings/sec, 1235 secs
lola: sara is running 1240 secs || 33672711 markings, 136233250 edges, 30381 markings/sec, 1240 secs
lola: sara is running 1245 secs || 33823434 markings, 136880827 edges, 30145 markings/sec, 1245 secs
lola: sara is running 1250 secs || 33973486 markings, 137514048 edges, 30010 markings/sec, 1250 secs
lola: sara is running 1255 secs || 34123971 markings, 138151763 edges, 30097 markings/sec, 1255 secs
lola: sara is running 1260 secs || 34270757 markings, 138765575 edges, 29357 markings/sec, 1260 secs
lola: sara is running 1265 secs || 34422594 markings, 139346056 edges, 30367 markings/sec, 1265 secs
lola: sara is running 1270 secs || 34573248 markings, 139928091 edges, 30131 markings/sec, 1270 secs
lola: sara is running 1275 secs || 34714324 markings, 140513207 edges, 28215 markings/sec, 1275 secs
lola: sara is running 1280 secs || 34853952 markings, 141092363 edges, 27926 markings/sec, 1280 secs
lola: sara is running 1285 secs || 34992562 markings, 141685434 edges, 27722 markings/sec, 1285 secs
lola: sara is running 1290 secs || 35131153 markings, 142277852 edges, 27718 markings/sec, 1290 secs
lola: sara is running 1295 secs || 35279861 markings, 142869157 edges, 29742 markings/sec, 1295 secs
lola: sara is running 1300 secs || 35431229 markings, 143458677 edges, 30274 markings/sec, 1300 secs
lola: sara is running 1305 secs || 35575565 markings, 144020153 edges, 28867 markings/sec, 1305 secs
lola: sara is running 1310 secs || 35730636 markings, 144656031 edges, 31014 markings/sec, 1310 secs
lola: sara is running 1315 secs || 35881784 markings, 145299157 edges, 30230 markings/sec, 1315 secs
lola: sara is running 1320 secs || 36032967 markings, 145911817 edges, 30237 markings/sec, 1320 secs
lola: sara is running 1325 secs || 36179693 markings, 146524434 edges, 29345 markings/sec, 1325 secs
lola: sara is running 1330 secs || 36324244 markings, 147125799 edges, 28910 markings/sec, 1330 secs
lola: sara is running 1335 secs || 36478698 markings, 147762181 edges, 30891 markings/sec, 1335 secs
lola: sara is running 1340 secs || 36626471 markings, 148393762 edges, 29555 markings/sec, 1340 secs
lola: sara is running 1345 secs || 36773188 markings, 148997945 edges, 29343 markings/sec, 1345 secs
lola: sara is running 1350 secs || 36922152 markings, 149624157 edges, 29793 markings/sec, 1350 secs
lola: sara is running 1355 secs || 37066326 markings, 150237583 edges, 28835 markings/sec, 1355 secs
lola: sara is running 1360 secs || 37210288 markings, 150879681 edges, 28792 markings/sec, 1360 secs
lola: sara is running 1365 secs || 37351471 markings, 151501059 edges, 28237 markings/sec, 1365 secs
lola: sara is running 1370 secs || 37494348 markings, 152115906 edges, 28575 markings/sec, 1370 secs
lola: sara is running 1375 secs || 37629544 markings, 152686334 edges, 27039 markings/sec, 1375 secs
lola: sara is running 1380 secs || 37778275 markings, 153315880 edges, 29746 markings/sec, 1380 secs
lola: sara is running 1385 secs || 37929520 markings, 153938504 edges, 30249 markings/sec, 1385 secs
lola: sara is running 1390 secs || 38070554 markings, 154544628 edges, 28207 markings/sec, 1390 secs
lola: sara is running 1395 secs || 38203931 markings, 155131110 edges, 26675 markings/sec, 1395 secs
lola: sara is running 1400 secs || 38331048 markings, 155673890 edges, 25423 markings/sec, 1400 secs
lola: sara is running 1405 secs || 38473248 markings, 156279867 edges, 28440 markings/sec, 1405 secs
lola: sara is running 1410 secs || 38602386 markings, 156825112 edges, 25828 markings/sec, 1410 secs
lola: sara is running 1415 secs || 38730204 markings, 157366871 edges, 25564 markings/sec, 1415 secs
lola: sara is running 1420 secs || 38868982 markings, 157949744 edges, 27756 markings/sec, 1420 secs
lola: sara is running 1425 secs || 38989429 markings, 158459856 edges, 24089 markings/sec, 1425 secs
lola: sara is running 1430 secs || 39124121 markings, 159043682 edges, 26938 markings/sec, 1430 secs
lola: sara is running 1435 secs || 39236100 markings, 159559981 edges, 22396 markings/sec, 1435 secs
lola: sara is running 1440 secs || 39373658 markings, 160147154 edges, 27512 markings/sec, 1440 secs
lola: sara is running 1445 secs || 39519173 markings, 160758630 edges, 29103 markings/sec, 1445 secs
lola: sara is running 1450 secs || 39661414 markings, 161353008 edges, 28448 markings/sec, 1450 secs
lola: sara is running 1455 secs || 39799554 markings, 161923891 edges, 27628 markings/sec, 1455 secs
lola: sara is running 1460 secs || 39936702 markings, 162482557 edges, 27430 markings/sec, 1460 secs
lola: sara is running 1465 secs || 40072230 markings, 163048111 edges, 27106 markings/sec, 1465 secs
lola: sara is running 1470 secs || 40203841 markings, 163600577 edges, 26322 markings/sec, 1470 secs
lola: sara is running 1475 secs || 40334742 markings, 164171088 edges, 26180 markings/sec, 1475 secs
lola: sara is running 1480 secs || 40480633 markings, 164725689 edges, 29178 markings/sec, 1480 secs
lola: sara is running 1485 secs || 40625159 markings, 165279385 edges, 28905 markings/sec, 1485 secs
lola: sara is running 1490 secs || 40766017 markings, 165850854 edges, 28172 markings/sec, 1490 secs
lola: sara is running 1495 secs || 40905668 markings, 166427738 edges, 27930 markings/sec, 1495 secs
lola: sara is running 1500 secs || 41048671 markings, 166992335 edges, 28601 markings/sec, 1500 secs
lola: sara is running 1505 secs || 41188143 markings, 167553079 edges, 27894 markings/sec, 1505 secs
lola: sara is running 1510 secs || 41325846 markings, 168136972 edges, 27541 markings/sec, 1510 secs
lola: sara is running 1515 secs || 41461600 markings, 168698307 edges, 27151 markings/sec, 1515 secs
lola: sara is running 1520 secs || 41599019 markings, 169253117 edges, 27484 markings/sec, 1520 secs
lola: sara is running 1525 secs || 41741986 markings, 169788068 edges, 28593 markings/sec, 1525 secs
lola: sara is running 1530 secs || 41878939 markings, 170340708 edges, 27391 markings/sec, 1530 secs
lola: sara is running 1535 secs || 42018111 markings, 170893813 edges, 27834 markings/sec, 1535 secs
lola: sara is running 1540 secs || 42146950 markings, 171411199 edges, 25768 markings/sec, 1540 secs
lola: sara is running 1545 secs || 42281557 markings, 171976924 edges, 26921 markings/sec, 1545 secs
lola: sara is running 1550 secs || 42401578 markings, 172404854 edges, 24004 markings/sec, 1550 secs
lola: sara is running 1555 secs || 42402498 markings, 172408000 edges, 184 markings/sec, 1555 secs
lola: Child process aborted or communication problem between parent and child process
lola: subprocess 15 will run for 1965 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((((1 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4) AND (3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 +... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 1844 bytes per marking, with 0 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 5 literals and 2 conjunctive subformulas
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: RESULT
lola:
SUMMARY: yes yes yes no yes yes no no yes yes no no yes no unknown yes
lola: ========================================
FORMULA Peterson-COL-4-ReachabilityCardinality-0 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-1 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-2 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-3 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-4 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-5 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-6 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-7 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-8 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-9 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-14 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
----- Kill lola and sara stdout -----
----- Finished stdout -----

BK_STOP 1496273281726

--------------------
content from stderr:

----- Start make prepare stderr -----
----- Start make result stderr -----
----- Start make result stderr -----
----- Kill lola and sara stderr -----
----- Finished stderr -----

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_Peterson-PT-4"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_Peterson-PT-4.tgz
mv S_Peterson-PT-4 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool lola"
echo " Input is S_Peterson-PT-4, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r128-smll-149441681100061"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;