Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_PermAdmissibility-PT-01, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r120-blw7-149441652100403
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-0
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-1
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-10
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-11
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-12
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-13
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-14
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-15
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-2
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-3
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-4
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-5
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-6
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-7
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-8
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityCardinality-9

=== Now, execution of the tool begins

BK_START 1496471770197


Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-reach command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 592 rows 168 cols
invariant : -1'aux8_7 + 1'c12 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + 2'c11 + 2'c110 + 2'c9= 0
invariant : 2'c20 + 2'out7_1 + 2'out7_0 + 2'out7_3 + 2'out7_2 + 2'out7_5 + 2'out7_4 + 2'out7_7 + 2'out7_6 + 2'c19 + 1'aux13_2 + 1'aux13_1 + 1'aux13_0 + 1'aux13_7 + 1'c18 + 1'aux13_3 + 1'aux13_4 + 1'aux13_5 + 1'aux13_6 + 1'aux6_0 + 1'c12 + 1'aux6_5 + 1'aux6_1 + 1'aux6_4 + 2'c13 + 1'in3_5 + 1'in3_4 + 1'c6= 2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out3_0 + 1'out3_1 + 1'out3_6 + 1'out3_7 + 1'out3_2 + 1'out3_3 + 1'out3_4 + 1'out3_5= 0
invariant : -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out8_1 + 1'out8_0 + 1'out8_3 + 1'out8_2 + 1'out8_6 + 1'out8_7 + 1'out8_4 + 1'out8_5= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + 2'c14= 0
invariant : -2'c20 + -2'out7_1 + -2'out7_0 + -2'out7_3 + -2'out7_2 + -2'out7_5 + -2'out7_4 + -2'out7_7 + -2'out7_6 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux6_0 + -1'c12 + -1'aux6_5 + -1'aux6_1 + -1'aux6_4 + -2'c13 + -2'in3_5 + -2'in3_4 + 2'c5= -2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out4_0 + 1'out4_1 + 1'out4_7 + 1'out4_6 + 1'out4_3 + 1'out4_2 + 1'out4_5 + 1'out4_4= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_4 + 1'aux16_5 + -1'c20 + -1'out7_3 + -1'out7_2 + -1'out7_7 + -1'out7_6 + 1'out5_1 + -1'c19 + 1'out5_0 + 1'out5_5 + 1'out5_4 + 1'aux15_1 + 1'aux15_0 + 1'aux15_5 + 1'aux15_4 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -1'out3_7 + -1'out3_2 + -1'out3_3 + 1'out1_0 + 1'out1_5 + 1'out1_1 + 1'out1_4 + -1'c12 + 1'aux12_5 + 1'aux12_4 + 1'aux12_1 + 1'aux12_0 + -2'c13 + -1'c11 + 1'aux10_0 + 1'aux10_1 + 1'aux10_4 + 1'aux10_5= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + -1'aux15_2 + -1'aux15_1 + -1'aux15_0 + -1'aux15_6 + -1'aux15_5 + -1'aux15_4 + -1'aux15_3 + -1'aux15_7 + -1'c18 + 2'c16= 0
invariant : -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_6 + -1'aux14_5 + 1'c20 + -1'aux14_7 + 2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'c15= 0
invariant : 1'aux8_7 + -1'c12 + 1'aux8_3 + 1'aux8_6 + 1'aux8_2 + -2'c11 + -1'aux7_7 + -1'aux7_6 + -1'c110 + -1'aux7_3 + -1'aux7_2 + 2'c8= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out5_1 + 1'out5_2 + 1'out5_0 + 1'out5_5 + 1'out5_6 + 1'out5_3 + 1'out5_4 + 1'out5_7= 0
invariant : -1'aux16_0 + -1'aux16_1 + 1'aux16_2 + 1'aux16_3 + -1'aux16_4 + -1'aux16_5 + 1'aux16_6 + 1'aux16_7 + 1'c20 + 2'out7_3 + 2'out7_2 + 2'out7_7 + 2'out7_6 + -2'out5_1 + -2'out5_0 + -2'out5_5 + -2'out5_4 + 1'aux15_2 + -1'aux15_1 + -1'aux15_0 + 1'aux15_6 + -1'aux15_5 + -1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'out3_6 + 2'out3_7 + 2'out3_2 + 2'out3_3 + -2'out1_0 + -2'out1_5 + -2'out1_1 + -2'out1_4 + -2'c12 + -2'aux12_5 + -2'aux12_4 + -2'aux12_1 + -2'aux12_0 + -2'c11 + 2'aux10_2 + 2'aux10_3 + 2'aux10_6 + 2'aux10_7= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + -2'aux13_2 + -2'aux13_1 + -2'aux13_0 + 1'aux15_7 + -2'aux13_7 + -1'c18 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + 2'aux12_6 + 2'aux12_5 + 2'aux12_4 + 2'aux12_3 + 2'aux12_2 + 2'aux12_1 + 2'aux12_0 + -4'c13 + 2'aux12_7= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out6_1 + 1'out6_2 + 1'out6_0 + 1'out6_6 + 1'out6_5 + 1'out6_4 + 1'out6_3 + 1'out6_7= 0
invariant : -1'in3_5 + -1'in3_4 + 1'in1_1 + 1'in1_0= 0
invariant : -1'aux16_0 + -1'aux16_1 + -1'aux16_2 + -1'aux16_3 + -1'aux16_4 + -1'aux16_5 + -1'aux16_6 + -1'aux16_7 + 1'c20 + 2'c19 + 2'c18 + 2'c17= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out2_0 + 1'out2_7 + 1'out2_5 + 1'out2_6 + 1'out2_3 + 1'out2_4 + 1'out2_1 + 1'out2_2= 0
invariant : = 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out1_0 + 1'out1_6 + 1'out1_5 + 1'out1_7 + 1'out1_2 + 1'out1_1 + 1'out1_4 + 1'out1_3= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -4'c12 + -4'c13 + 2'aux11_5 + 2'aux11_4 + 2'aux11_3 + 2'aux11_2 + 2'aux11_1 + 2'aux11_0 + 2'aux11_7 + 2'aux11_6= 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 592 rows 168 cols
invariant : -1'aux8_7 + 1'c12 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + 2'c11 + 2'c110 + 2'c9= 0
invariant : 2'c20 + 2'out7_1 + 2'out7_0 + 2'out7_3 + 2'out7_2 + 2'out7_5 + 2'out7_4 + 2'out7_7 + 2'out7_6 + 2'c19 + 1'aux13_2 + 1'aux13_1 + 1'aux13_0 + 1'aux13_7 + 1'c18 + 1'aux13_3 + 1'aux13_4 + 1'aux13_5 + 1'aux13_6 + 1'aux6_0 + 1'c12 + 1'aux6_5 + 1'aux6_1 + 1'aux6_4 + 2'c13 + 1'in3_5 + 1'in3_4 + 1'c6= 2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out3_0 + 1'out3_1 + 1'out3_6 + 1'out3_7 + 1'out3_2 + 1'out3_3 + 1'out3_4 + 1'out3_5= 0
invariant : -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out8_1 + 1'out8_0 + 1'out8_3 + 1'out8_2 + 1'out8_6 + 1'out8_7 + 1'out8_4 + 1'out8_5= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + 2'c14= 0
invariant : -2'c20 + -2'out7_1 + -2'out7_0 + -2'out7_3 + -2'out7_2 + -2'out7_5 + -2'out7_4 + -2'out7_7 + -2'out7_6 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux6_0 + -1'c12 + -1'aux6_5 + -1'aux6_1 + -1'aux6_4 + -2'c13 + -2'in3_5 + -2'in3_4 + 2'c5= -2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out4_0 + 1'out4_1 + 1'out4_7 + 1'out4_6 + 1'out4_3 + 1'out4_2 + 1'out4_5 + 1'out4_4= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_4 + 1'aux16_5 + -1'c20 + -1'out7_3 + -1'out7_2 + -1'out7_7 + -1'out7_6 + 1'out5_1 + -1'c19 + 1'out5_0 + 1'out5_5 + 1'out5_4 + 1'aux15_1 + 1'aux15_0 + 1'aux15_5 + 1'aux15_4 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -1'out3_7 + -1'out3_2 + -1'out3_3 + 1'out1_0 + 1'out1_5 + 1'out1_1 + 1'out1_4 + -1'c12 + 1'aux12_5 + 1'aux12_4 + 1'aux12_1 + 1'aux12_0 + -2'c13 + -1'c11 + 1'aux10_0 + 1'aux10_1 + 1'aux10_4 + 1'aux10_5= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + -1'aux15_2 + -1'aux15_1 + -1'aux15_0 + -1'aux15_6 + -1'aux15_5 + -1'aux15_4 + -1'aux15_3 + -1'aux15_7 + -1'c18 + 2'c16= 0
invariant : -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_6 + -1'aux14_5 + 1'c20 + -1'aux14_7 + 2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'c15= 0
invariant : 1'aux8_7 + -1'c12 + 1'aux8_3 + 1'aux8_6 + 1'aux8_2 + -2'c11 + -1'aux7_7 + -1'aux7_6 + -1'c110 + -1'aux7_3 + -1'aux7_2 + 2'c8= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out5_1 + 1'out5_2 + 1'out5_0 + 1'out5_5 + 1'out5_6 + 1'out5_3 + 1'out5_4 + 1'out5_7= 0
invariant : -1'aux16_0 + -1'aux16_1 + 1'aux16_2 + 1'aux16_3 + -1'aux16_4 + -1'aux16_5 + 1'aux16_6 + 1'aux16_7 + 1'c20 + 2'out7_3 + 2'out7_2 + 2'out7_7 + 2'out7_6 + -2'out5_1 + -2'out5_0 + -2'out5_5 + -2'out5_4 + 1'aux15_2 + -1'aux15_1 + -1'aux15_0 + 1'aux15_6 + -1'aux15_5 + -1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'out3_6 + 2'out3_7 + 2'out3_2 + 2'out3_3 + -2'out1_0 + -2'out1_5 + -2'out1_1 + -2'out1_4 + -2'c12 + -2'aux12_5 + -2'aux12_4 + -2'aux12_1 + -2'aux12_0 + -2'c11 + 2'aux10_2 + 2'aux10_3 + 2'aux10_6 + 2'aux10_7= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + -2'aux13_2 + -2'aux13_1 + -2'aux13_0 + 1'aux15_7 + -2'aux13_7 + -1'c18 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + 2'aux12_6 + 2'aux12_5 + 2'aux12_4 + 2'aux12_3 + 2'aux12_2 + 2'aux12_1 + 2'aux12_0 + -4'c13 + 2'aux12_7= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out6_1 + 1'out6_2 + 1'out6_0 + 1'out6_6 + 1'out6_5 + 1'out6_4 + 1'out6_3 + 1'out6_7= 0
invariant : -1'in3_5 + -1'in3_4 + 1'in1_1 + 1'in1_0= 0
invariant : -1'aux16_0 + -1'aux16_1 + -1'aux16_2 + -1'aux16_3 + -1'aux16_4 + -1'aux16_5 + -1'aux16_6 + -1'aux16_7 + 1'c20 + 2'c19 + 2'c18 + 2'c17= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out2_0 + 1'out2_7 + 1'out2_5 + 1'out2_6 + 1'out2_3 + 1'out2_4 + 1'out2_1 + 1'out2_2= 0
invariant : = 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out1_0 + 1'out1_6 + 1'out1_5 + 1'out1_7 + 1'out1_2 + 1'out1_1 + 1'out1_4 + 1'out1_3= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -4'c12 + -4'c13 + 2'aux11_5 + 2'aux11_4 + 2'aux11_3 + 2'aux11_2 + 2'aux11_1 + 2'aux11_0 + 2'aux11_7 + 2'aux11_6= 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility\_PT\_01\_flat\_flat,52537,9.26216,233084,2,49937,5,147174,6,0,1098,59698,0
Total reachable state count : 52537

Verifying 16 reachability properties.
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-0 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-0,0,9.30838,233104,1,0,5,147174,7,0,1179,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-1 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-1 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-1,4,9.3103,233172,2,270,6,147174,8,0,1180,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-2 does not hold.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-2 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : PermAdmissibility-COL-01-ReachabilityCardinality-2

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-2,0,9.3433,233172,1,0,6,147174,9,0,1181,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-3 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-3 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-3,4672,9.34767,233172,2,9289,7,147174,10,0,1192,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-4 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-4 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-4,0,9.36864,233172,1,0,7,147174,11,0,1210,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-5 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-5 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-5,0,9.4283,233172,1,0,7,147174,12,0,1252,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-6 does not hold.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-6 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-6,1,9.44773,233172,2,169,8,147174,13,0,1290,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-7 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-7 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-7,0,9.44964,233172,1,0,8,147174,14,0,1315,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-8 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-8 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-8,0,9.47825,233172,1,0,8,147174,15,0,1349,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-9 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-9 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-9,0,9.51143,233172,1,0,8,147174,16,0,1403,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-10 does not hold.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : PermAdmissibility-COL-01-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-10,0,9.5383,233172,1,0,8,147174,17,0,1426,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-11 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-11,0,9.57088,233172,1,0,8,147174,18,0,1476,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-12 does not hold.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : PermAdmissibility-COL-01-ReachabilityCardinality-12

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-12,0,9.62866,233172,1,0,8,147174,19,0,1554,59698,0
Invariant property PermAdmissibility-COL-01-ReachabilityCardinality-13 does not hold.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-13 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-13,1168,9.63369,233172,2,6953,9,147174,20,0,1586,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-14 is true.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-14,1,9.65568,233172,2,169,10,147174,21,0,1629,59698,0
Reachability property PermAdmissibility-COL-01-ReachabilityCardinality-15 does not hold.
FORMULA PermAdmissibility-COL-01-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : PermAdmissibility-COL-01-ReachabilityCardinality-15

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
PermAdmissibility-COL-01-ReachabilityCardinality-15,0,9.6932,233172,1,0,10,147174,22,0,1631,59698,0
Exit code :0

BK_STOP 1496471783365

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityCardinality -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 03, 2017 6:36:11 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 03, 2017 6:36:11 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 116 ms
Jun 03, 2017 6:36:11 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
Jun 03, 2017 6:36:11 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 592 transitions.
Jun 03, 2017 6:36:12 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 227 ms
Jun 03, 2017 6:36:12 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 130 ms
Jun 03, 2017 6:36:12 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 27 ms
Jun 03, 2017 6:36:12 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
Jun 03, 2017 6:36:12 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 306 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 411 ms.
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-0(UNSAT) depth K=0 took 3 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-1(UNSAT) depth K=0 took 6 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-2(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-3(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-4(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-5(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-6(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-7(UNSAT) depth K=0 took 0 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-8(UNSAT) depth K=0 took 0 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-9(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-10(UNSAT) depth K=0 took 0 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-11(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-12(UNSAT) depth K=0 took 4 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-13(UNSAT) depth K=0 took 0 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-14(UNSAT) depth K=0 took 0 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-15(UNSAT) depth K=0 took 1 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 21 place invariants in 166 ms
Jun 03, 2017 6:36:13 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 21 place invariants in 120 ms
Jun 03, 2017 6:36:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-0(UNSAT) depth K=1 took 2262 ms
Jun 03, 2017 6:36:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-1(UNSAT) depth K=1 took 167 ms
Jun 03, 2017 6:36:15 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-2(UNSAT) depth K=1 took 96 ms
Jun 03, 2017 6:36:16 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-3(UNSAT) depth K=1 took 1131 ms
Jun 03, 2017 6:36:17 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-4(UNSAT) depth K=1 took 192 ms
Jun 03, 2017 6:36:18 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-5(UNSAT) depth K=1 took 1112 ms
Jun 03, 2017 6:36:20 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-6(UNSAT) depth K=1 took 2567 ms
Jun 03, 2017 6:36:20 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-7(UNSAT) depth K=1 took 166 ms
Jun 03, 2017 6:36:21 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-8(UNSAT) depth K=1 took 265 ms
Jun 03, 2017 6:36:21 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-9(UNSAT) depth K=1 took 276 ms
Jun 03, 2017 6:36:21 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 168 variables to be positive in 8519 ms
Jun 03, 2017 6:36:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-10(UNSAT) depth K=1 took 950 ms
Jun 03, 2017 6:36:22 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property PermAdmissibility-COL-01-ReachabilityCardinality-11(UNSAT) depth K=1 took 301 ms
Jun 03, 2017 6:36:22 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 168 variables to be positive in 9782 ms
Jun 03, 2017 6:36:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 592 transitions.
Jun 03, 2017 6:36:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/592 took 48 ms. Total solver calls (SAT/UNSAT): 136(8/128)
Jun 03, 2017 6:36:23 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-0 with value :((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)<=(((((((aux14_0+aux14_1)+aux14_2)+aux14_3)+aux14_4)+aux14_6)+aux14_5)+aux14_7))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-1 with value :(c19>=1)
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-2 with value :(c5>=3)
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-3 with value :(!(c18<=(((((((out4_0+out4_1)+out4_7)+out4_6)+out4_3)+out4_2)+out4_5)+out4_4)))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-4 with value :(!((((in4_6+in4_7)>=1)||((((((((out2_0+out2_7)+out2_5)+out2_6)+out2_3)+out2_4)+out2_1)+out2_2)>=1))&&(c19>=2)))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-5 with value :(!((((((((((aux11_5+aux11_4)+aux11_3)+aux11_2)+aux11_1)+aux11_0)+aux11_7)+aux11_6)<=(((((((aux12_6+aux12_5)+aux12_4)+aux12_3)+aux12_2)+aux12_1)+aux12_0)+aux12_7))&&(c20<=(((((((out6_1+out6_2)+out6_0)+out6_6)+out6_5)+out6_4)+out6_3)+out6_7)))&&((((((((out5_1+out5_2)+out5_0)+out5_5)+out5_6)+out5_3)+out5_4)+out5_7)>=3)))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-6 with value :((((((((out4_0+out4_1)+out4_7)+out4_6)+out4_3)+out4_2)+out4_5)+out4_4)<=(((((((aux10_0+aux10_2)+aux10_1)+aux10_4)+aux10_3)+aux10_5)+aux10_6)+aux10_7))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-7 with value :(!(((c18<=c15)&&(c19>=2))&&(((((((((aux9_4+aux9_5)+aux9_6)+aux9_7)+aux9_0)+aux9_1)+aux9_2)+aux9_3)<=c11)&&((((((((out4_0+out4_1)+out4_7)+out4_6)+out4_3)+out4_2)+out4_5)+out4_4)>=1))))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-8 with value :(!(((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)<=(((((((out2_0+out2_7)+out2_5)+out2_6)+out2_3)+out2_4)+out2_1)+out2_2))&&(((in1_1+in1_0)<=(((((((aux10_0+aux10_2)+aux10_1)+aux10_4)+aux10_3)+aux10_5)+aux10_6)+aux10_7))&&((in1_1+in1_0)>=2))))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-9 with value :(((c9<=c17)||((c11<=(((((((aux11_5+aux11_4)+aux11_3)+aux11_2)+aux11_1)+aux11_0)+aux11_7)+aux11_6))||((((((((out5_1+out5_2)+out5_0)+out5_5)+out5_6)+out5_3)+out5_4)+out5_7)>=2)))||(c5>=3))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-10 with value :(!(((c16>=3)&&((((((((aux13_2+aux13_1)+aux13_0)+aux13_7)+aux13_3)+aux13_4)+aux13_5)+aux13_6)>=2))||(!((((((((out1_0+out1_6)+out1_5)+out1_7)+out1_2)+out1_1)+out1_4)+out1_3)>=2))))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-11 with value :(((((((((((aux9_4+aux9_5)+aux9_6)+aux9_7)+aux9_0)+aux9_1)+aux9_2)+aux9_3)>=2)||(c14<=(((((((aux12_6+aux12_5)+aux12_4)+aux12_3)+aux12_2)+aux12_1)+aux12_0)+aux12_7)))||((((aux7_7+aux7_6)+aux7_3)+aux7_2)>=3))||((((((((((out1_0+out1_6)+out1_5)+out1_7)+out1_2)+out1_1)+out1_4)+out1_3)<=(((aux8_7+aux8_3)+aux8_6)+aux8_2))||((((((((aux12_6+aux12_5)+aux12_4)+aux12_3)+aux12_2)+aux12_1)+aux12_0)+aux12_7)<=c11))||((c8<=(((((((out7_1+out7_0)+out7_3)+out7_2)+out7_5)+out7_4)+out7_7)+out7_6))&&(c9>=1))))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-12 with value :(((!((((((((out8_1+out8_0)+out8_3)+out8_2)+out8_6)+out8_7)+out8_4)+out8_5)<=(((((((aux9_4+aux9_5)+aux9_6)+aux9_7)+aux9_0)+aux9_1)+aux9_2)+aux9_3)))||(!((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)>=1)))&&((!((in1_1+in1_0)<=c11))&&((c15>=3)||((in2_2+in2_3)<=(((((((aux14_0+aux14_1)+aux14_2)+aux14_3)+aux14_4)+aux14_6)+aux14_5)+aux14_7)))))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-13 with value :(((!((((((((out4_0+out4_1)+out4_7)+out4_6)+out4_3)+out4_2)+out4_5)+out4_4)>=2))||((((((((aux16_0+aux16_1)+aux16_2)+aux16_3)+aux16_4)+aux16_5)+aux16_6)+aux16_7)>=1))&&(c17<=(((((((out4_0+out4_1)+out4_7)+out4_6)+out4_3)+out4_2)+out4_5)+out4_4)))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-14 with value :(((((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)<=(((((((aux13_2+aux13_1)+aux13_0)+aux13_7)+aux13_3)+aux13_4)+aux13_5)+aux13_6))||(c12<=(((aux8_7+aux8_3)+aux8_6)+aux8_2)))&&(!((((((((aux15_2+aux15_1)+aux15_0)+aux15_6)+aux15_5)+aux15_4)+aux15_3)+aux15_7)>=2)))&&(c20>=1))
Read property : PermAdmissibility-COL-01-ReachabilityCardinality-15 with value :((c8>=3)&&(c13>=1))

Jun 03, 2017 6:36:23 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_PermAdmissibility-PT-01"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_PermAdmissibility-PT-01.tgz
mv S_PermAdmissibility-PT-01 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_PermAdmissibility-PT-01, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r120-blw7-149441652100403"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;