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Model Checking Contest @ Petri Nets 2017
7th edition, Zaragoza, Spain, June 27, 2017
Execution of r031-blw7-149440474000345
Last Updated
June 27, 2017

About the Execution of MARCIE for PermAdmissibility-COL-01

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
10131.010 318598.00 318020.00 20.20 FTFFTTFFTTFFTFTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool marcie
Input is PermAdmissibility-COL-01, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r031-blw7-149440474000345
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-0
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-1
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-10
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-11
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-12
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-13
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-14
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-15
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-2
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-3
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-4
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-5
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-6
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-7
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-8
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-9

=== Now, execution of the tool begins

BK_START 1494463277616

timeout --kill-after=10s --signal=SIGINT 1m for testing only

Marcie rev. 8852M (built: crohr on 2017-05-03)
A model checker for Generalized Stochastic Petri nets

authors: Alex Tovchigrechko (IDD package and CTL model checking)

Martin Schwarick (Symbolic numerical analysis and CSL model checking)

Christian Rohr (Simulative and approximative numerical model checking)

marcie@informatik.tu-cottbus.de

called as: marcie --net-file=model.pnml --mcc-file=CTLCardinality.xml --memory=6

parse successfull
net created successfully

Unfolding complete |P|=208|T|=1024|A|=6080
Time for unfolding: 0m 2.533sec

Net: PermAdmissibility_COL_01
(NrP: 208 NrTr: 1024 NrArc: 5984)

parse formulas
formulas created successfully
place and transition orderings generation:0m 0.029sec

net check time: 0m 0.001sec

init dd package: 0m 1.192sec

parse successfull
net created successfully

Unfolding complete |P|=208|T|=1024|A|=6080
Time for unfolding: 0m 2.658sec

Net: PermAdmissibility_COL_01
(NrP: 208 NrTr: 1024 NrArc: 5984)

parse formulas
formulas created successfully
place and transition orderings generation:0m 0.025sec

net check time: 0m 0.001sec

init dd package: 0m 3.597sec


RS generation: 0m42.568sec


-> reachability set: #nodes 53950 (5.4e+04) #states 52,537 (4)



starting MCC model checker
--------------------------

checking: EF [EG [~ [1<=c5_dot]]]
normalized: E [true U EG [~ [1<=c5_dot]]]

abstracting: (1<=c5_dot)
states: 1
.
EG iterations: 1
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-2 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m49.865sec

checking: A [~ [3<=c18_dot] U AF [2<=c12_dot]]
normalized: [~ [EG [EG [~ [2<=c12_dot]]]] & ~ [E [EG [~ [2<=c12_dot]] U [3<=c18_dot & EG [~ [2<=c12_dot]]]]]]

abstracting: (2<=c12_dot)
states: 0

EG iterations: 0
abstracting: (3<=c18_dot)
states: 0
abstracting: (2<=c12_dot)
states: 0

EG iterations: 0
abstracting: (2<=c12_dot)
states: 0

EG iterations: 0

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-10 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.050sec

checking: ~ [[[EG [1<=c15_dot] | AF [3<=c19_dot]] | 2<=c17_dot]]
normalized: ~ [[2<=c17_dot | [~ [EG [~ [3<=c19_dot]]] | EG [1<=c15_dot]]]]

abstracting: (1<=c15_dot)
states: 736
..
EG iterations: 2
abstracting: (3<=c19_dot)
states: 0

EG iterations: 0
abstracting: (2<=c17_dot)
states: 0
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-3 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.439sec

checking: EG [[EX [c5_dot<=c19_dot] | 1<=c11_dot]]
normalized: EG [[1<=c11_dot | EX [c5_dot<=c19_dot]]]

abstracting: (c5_dot<=c19_dot)
states: 52,536 (4)
.abstracting: (1<=c11_dot)
states: 64
.................
EG iterations: 17
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-4 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m11.513sec

checking: AF [1<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0)]
normalized: ~ [EG [~ [1<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0)]]]

abstracting: (1<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0))
states: 37,376 (4)
................
EG iterations: 16
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-6 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.043sec

checking: EG [AG [~ [3<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)]]]
normalized: EG [~ [E [true U 3<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)]]]

abstracting: (3<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0))
states: 0

EG iterations: 0
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-13 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.063sec

checking: E [EF [sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)<=c19_dot] U 2<=c7_dot]
normalized: E [E [true U sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)<=c19_dot] U 2<=c7_dot]

abstracting: (2<=c7_dot)
states: 0
abstracting: (sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)<=c19_dot)
states: 42,729 (4)
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-0 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m33.943sec

checking: AF [~ [[[c17_dot<=c19_dot | c6_dot<=sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)] & c18_dot<=c7_dot]]]
normalized: ~ [EG [[c18_dot<=c7_dot & [c17_dot<=c19_dot | c6_dot<=sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)]]]]

abstracting: (c6_dot<=sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0))
states: 52,533 (4)
abstracting: (c17_dot<=c19_dot)
states: 51,369 (4)
abstracting: (c18_dot<=c7_dot)
states: 47,865 (4)
..............
EG iterations: 14
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-12 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 2.160sec

checking: AG [~ [EG [sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]]]
normalized: ~ [E [true U EG [sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]]]

abstracting: (sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0))
states: 52,137 (4)
.....
EG iterations: 5
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-5 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 1.537sec

checking: EG [E [sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0)<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0) U 3<=c15_dot]]
normalized: EG [E [sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0)<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0) U 3<=c15_dot]]

abstracting: (3<=c15_dot)
states: 0
abstracting: (sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0)<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0))
states: 52,537 (4)
.
EG iterations: 1
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-7 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.162sec

checking: ~ [[AX [[sum(aux9_input7, aux9_input6, aux9_input5, aux9_input4, aux9_input3, aux9_input2, aux9_input1, aux9_input0)<=c15_dot & c13_dot<=c20_dot]] & [AG [sum(in3_input7, in3_input6, in3_input5, in3_input4, in3_input3, in3_input2, in3_input1, in3_input0)<=c6_dot] | AF [3<=c19_dot]]]]
normalized: ~ [[[~ [EG [~ [3<=c19_dot]]] | ~ [E [true U ~ [sum(in3_input7, in3_input6, in3_input5, in3_input4, in3_input3, in3_input2, in3_input1, in3_input0)<=c6_dot]]]] & ~ [EX [~ [[sum(aux9_input7, aux9_input6, aux9_input5, aux9_input4, aux9_input3, aux9_input2, aux9_input1, aux9_input0)<=c15_dot & c13_dot<=c20_dot]]]]]]

abstracting: (c13_dot<=c20_dot)
states: 52,281 (4)
abstracting: (sum(aux9_input7, aux9_input6, aux9_input5, aux9_input4, aux9_input3, aux9_input2, aux9_input1, aux9_input0)<=c15_dot)
states: 51,001 (4)
.abstracting: (sum(in3_input7, in3_input6, in3_input5, in3_input4, in3_input3, in3_input2, in3_input1, in3_input0)<=c6_dot)
states: 52,536 (4)
abstracting: (3<=c19_dot)
states: 0

EG iterations: 0
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-8 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.455sec

checking: AF [[[[c5_dot<=c7_dot | 2<=c17_dot] & ~ [3<=c14_dot]] & [[3<=c6_dot & sum(aux10_input7, aux10_input6, aux10_input5, aux10_input4, aux10_input3, aux10_input2, aux10_input1, aux10_input0)<=c14_dot] & 1<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0)]]]
normalized: ~ [EG [~ [[[1<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0) & [3<=c6_dot & sum(aux10_input7, aux10_input6, aux10_input5, aux10_input4, aux10_input3, aux10_input2, aux10_input1, aux10_input0)<=c14_dot]] & [~ [3<=c14_dot] & [c5_dot<=c7_dot | 2<=c17_dot]]]]]]

abstracting: (2<=c17_dot)
states: 0
abstracting: (c5_dot<=c7_dot)
states: 52,536 (4)
abstracting: (3<=c14_dot)
states: 0
abstracting: (sum(aux10_input7, aux10_input6, aux10_input5, aux10_input4, aux10_input3, aux10_input2, aux10_input1, aux10_input0)<=c14_dot)
states: 47,993 (4)
abstracting: (3<=c6_dot)
states: 0
abstracting: (1<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0))
states: 18,688 (4)

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-15 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.287sec

checking: A [[~ [1<=c17_dot] | [1<=sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0) | 2<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)]] U 3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)]
normalized: [~ [EG [~ [3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)]]] & ~ [E [~ [3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)] U [~ [[[1<=sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0) | 2<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)] | ~ [1<=c17_dot]]] & ~ [3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)]]]]]

abstracting: (3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0))
states: 0
abstracting: (1<=c17_dot)
states: 1,168 (3)
abstracting: (2<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0))
states: 40
abstracting: (1<=sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0))
states: 400
abstracting: (3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0))
states: 0
abstracting: (3<=sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0))
states: 0

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-9 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m21.720sec

checking: [[~ [EF [1<=sum(out6_input7, out6_input6, out6_input5, out6_input4, out6_input3, out6_input2, out6_input1, out6_input0)]] | 3<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)] | [3<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0) & 1<=sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)]]
normalized: [[3<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0) & 1<=sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)] | [3<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0) | ~ [E [true U 1<=sum(out6_input7, out6_input6, out6_input5, out6_input4, out6_input3, out6_input2, out6_input1, out6_input0)]]]]

abstracting: (1<=sum(out6_input7, out6_input6, out6_input5, out6_input4, out6_input3, out6_input2, out6_input1, out6_input0))
states: 37,376 (4)
abstracting: (3<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0))
states: 0
abstracting: (1<=sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0))
states: 32,272 (4)
abstracting: (3<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0))
states: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-14 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 1m28.739sec

checking: A [[[sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0) | sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)] & [sum(out3_input7, out3_input6, out3_input5, out3_input4, out3_input3, out3_input2, out3_input1, out3_input0)<=sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0) & c19_dot<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)]] U AG [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]]
normalized: [~ [E [E [true U ~ [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]] U [~ [[[sum(out3_input7, out3_input6, out3_input5, out3_input4, out3_input3, out3_input2, out3_input1, out3_input0)<=sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0) & c19_dot<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)] & [sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0) | sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)]]] & E [true U ~ [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]]]]] & ~ [EG [E [true U ~ [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]]]]]

abstracting: (sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0))
states: 20,265 (4)
.................
EG iterations: 17
abstracting: (sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0))
states: 20,265 (4)
abstracting: (sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)<=sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0))
states: 51,129 (4)
abstracting: (sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0))
states: 52,441 (4)
abstracting: (c19_dot<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0))
states: 47,865 (4)
abstracting: (sum(out3_input7, out3_input6, out3_input5, out3_input4, out3_input3, out3_input2, out3_input1, out3_input0)<=sum(aux8_input7, aux8_input6, aux8_input5, aux8_input4, aux8_input3, aux8_input2, aux8_input1, aux8_input0))
states: 10,489 (4)
abstracting: (sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0))
states: 20,265 (4)
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-11 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m47.432sec

checking: [[E [3<=sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0) U sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)] & [AF [sum(in3_input7, in3_input6, in3_input5, in3_input4, in3_input3, in3_input2, in3_input1, in3_input0)<=c13_dot] | ~ [[c16_dot<=c9_dot & 1<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)]]]] & [~ [AG [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(out4_input7, out4_input6, out4_input5, out4_input4, out4_input3, out4_input2, out4_input1, out4_input0)]] | [[[sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0) & 1<=c8_dot] & ~ [sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)<=c7_dot]] | [2<=c12_dot & ~ [c16_dot<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)]]]]]
normalized: [[E [true U ~ [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(out4_input7, out4_input6, out4_input5, out4_input4, out4_input3, out4_input2, out4_input1, out4_input0)]] | [[2<=c12_dot & ~ [c16_dot<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)]] | [~ [sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)<=c7_dot] & [sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0) & 1<=c8_dot]]]] & [[~ [[c16_dot<=c9_dot & 1<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)]] | ~ [EG [~ [sum(in3_input7, in3_input6, in3_input5, in3_input4, in3_input3, in3_input2, in3_input1, in3_input0)<=c13_dot]]]] & E [3<=sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0) U sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)]]]

abstracting: (sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0))
states: 33,849 (4)
abstracting: (3<=sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0))
states: 0
abstracting: (sum(in3_input7, in3_input6, in3_input5, in3_input4, in3_input3, in3_input2, in3_input1, in3_input0)<=c13_dot)
states: 52,532 (4)
...
EG iterations: 3
abstracting: (1<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0))
states: 46,720 (4)
abstracting: (c16_dot<=c9_dot)
states: 50,201 (4)
abstracting: (1<=c8_dot)
states: 16
abstracting: (sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0))
states: 52,532 (4)
abstracting: (sum(aux5_input7, aux5_input6, aux5_input5, aux5_input4, aux5_input3, aux5_input2, aux5_input1, aux5_input0)<=c7_dot)
states: 52,433 (4)
abstracting: (c16_dot<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0))
states: 50,201 (4)
abstracting: (2<=c12_dot)
states: 0
abstracting: (sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=sum(out4_input7, out4_input6, out4_input5, out4_input4, out4_input3, out4_input2, out4_input1, out4_input0))
states: 38,953 (4)
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-1 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 1.753sec

totally nodes used: 38919176 (3.9e+07)
number of garbage collections: 0
fire ops cache: hits/miss/sum: 86580964 390306761 476887725
used/not used/entry size/cache size: 66822389 286475 16 1024MB
basic ops cache: hits/miss/sum: 8472401 42426224 50898625
used/not used/entry size/cache size: 16609053 168163 12 192MB
unary ops cache: hits/miss/sum: 0 0 0
used/not used/entry size/cache size: 0 16777216 8 128MB
abstract ops cache: hits/miss/sum: 0 277786 277786
used/not used/entry size/cache size: 1 16777215 12 192MB
state nr cache: hits/miss/sum: 9966 58278 68244
used/not used/entry size/cache size: 58160 8330448 32 256MB
max state cache: hits/miss/sum: 0 0 0
used/not used/entry size/cache size: 0 8388608 32 256MB
uniqueHash elements/entry size/size: 67108864 4 256MB
0 39133593
1 19461754
2 6521472
3 1619748
4 314947
5 49867
6 6605
7 772
8 102
9 3
>= 10 1

Total processing time: 5m18.408sec


BK_STOP 1494463596214

--------------------
content from stderr:

check for maximal unmarked siphon
found
The net has a maximal unmarked siphon:
aux5_input7
aux5_input6
in3_input3
aux5_input3
aux5_input2
in1_input2
aux7_input5
in3_input1
in3_input2
aux7_input4
aux6_input7
aux6_input6
aux8_input5
aux8_input1
aux8_input4
aux8_input0
aux6_input3
aux7_input1
aux6_input2
aux7_input0
in3_input6
in3_input7
in4_input0
in4_input1
in4_input2
in4_input3
in4_input4
in4_input5
in1_input3
in1_input4
in1_input5
in1_input6
in1_input7
in2_input0
in2_input1
in2_input4
in2_input5
in2_input6
in2_input7
in3_input0

The net has transition(s) that can never fire:
switch1_0_2
switch1_0_3
switch1_0_6
switch1_0_7
switch1_1_0
switch3_3_0
switch3_3_1
switch3_3_2
switch3_3_3
switch3_4_7
switch3_5_0
switch3_5_2
switch3_5_1
switch1_0_0
switch1_0_1
switch5_0_4
switch5_0_5
switch5_1_0
switch5_1_1
switch5_1_4
switch5_1_5
switch1_1_1
switch1_1_2
switch1_1_3
switch1_1_6
switch1_1_7
switch1_2_0
switch1_2_1
switch1_2_2
switch1_2_3
switch1_2_4
switch1_2_5
switch1_2_6
switch1_2_7
switch1_3_0
switch1_3_1
switch1_3_2
switch1_3_3
switch1_3_4
switch1_3_5
switch1_3_6
switch1_3_7
switch1_4_0
switch1_4_1
switch1_4_2
switch1_4_3
switch1_4_4
switch1_4_5
switch1_4_6
switch1_4_7
switch1_5_0
switch1_5_1
switch1_5_2
switch1_5_3
switch1_5_4
switch1_5_5
switch1_5_6
switch1_5_7
switch1_6_0
switch1_6_1
switch1_6_2
switch1_6_3
switch1_6_4
switch1_6_5
switch1_6_6
switch1_6_7
switch1_7_0
switch1_7_1
switch1_7_2
switch1_7_3
switch1_7_4
switch1_7_5
switch1_7_6
switch1_7_7
switch3_0_0
switch3_0_1
switch3_0_2
switch3_0_3
switch3_0_4
switch3_0_5
switch3_0_6
switch3_0_7
switch3_1_0
switch3_1_1
switch3_1_2
switch3_1_3
switch3_1_4
switch3_1_5
switch3_1_6
switch3_1_7
switch3_2_0
switch3_2_1
switch3_2_2
switch3_2_3
switch3_2_4
switch3_2_5
switch6_5_5
switch6_6_0
switch6_6_1
switch6_6_2
switch6_6_3
switch6_6_4
switch3_3_4
switch3_3_5
switch3_4_0
switch3_4_1
switch3_4_2
switch3_4_3
switch3_4_4
switch3_4_5
switch3_4_6
switch7_1_4
switch7_1_5
switch7_2_0
switch7_2_1
switch3_5_3
switch3_5_4
switch3_5_5
switch3_5_6
switch3_5_7
switch3_6_0
switch3_6_1
switch3_6_2
switch3_6_3
switch3_6_4
switch3_6_5
switch3_6_6
switch3_6_7
switch3_7_0
switch3_7_1
switch3_7_2
switch3_7_3
switch3_7_4
switch3_7_5
switch3_7_6
switch3_7_7
switch2_0_0
switch2_0_1
switch2_0_2
switch2_0_3
switch2_0_6
switch2_0_7
switch2_1_0
switch2_1_1
switch2_1_2
switch2_1_3
switch2_1_6
switch2_1_7
switch2_2_0
switch2_2_1
switch2_2_2
switch2_2_3
switch2_2_4
switch2_2_5
switch2_2_6
switch2_2_7
switch2_3_0
switch2_3_1
switch2_3_2
switch2_3_3
switch2_3_4
switch2_3_5
switch2_3_6
switch2_3_7
switch2_4_0
switch2_4_1
switch2_4_2
switch2_4_3
switch2_4_4
switch2_4_5
switch2_4_6
switch2_4_7
switch2_5_0
switch2_5_1
switch2_5_2
switch2_5_3
switch2_5_4
switch2_5_5
switch2_5_6
switch2_5_7
switch2_6_0
switch2_6_1
switch2_6_2
switch2_6_3
switch2_6_4
switch2_6_5
switch2_6_6
switch2_6_7
switch2_7_0
switch2_7_1
switch2_7_2
switch2_7_3
switch2_7_4
switch2_7_5
switch2_7_6
switch2_7_7
switch4_0_0
switch4_0_1
switch4_0_2
switch4_0_3
switch4_0_4
switch4_0_5
switch4_0_6
switch4_0_7
switch4_1_0
switch4_1_1
switch4_1_2
switch4_1_3
switch4_1_4
switch4_1_5
switch4_1_6
switch4_1_7
switch4_2_0
switch4_2_1
switch4_2_2
switch4_2_3
switch4_2_4
switch4_2_5
switch4_3_0
switch4_3_1
switch4_3_2
switch4_3_3
switch4_3_4
switch4_3_5
switch4_4_0
switch4_4_1
switch4_4_2
switch4_4_3
switch4_4_4
switch4_4_5
switch4_4_6
switch4_4_7
switch4_5_0
switch4_5_1
switch4_5_2
switch4_5_3
switch4_5_4
switch4_5_5
switch4_5_6
switch4_5_7
switch4_6_0
switch4_6_1
switch4_6_2
switch4_6_3
switch4_6_4
switch4_6_5
switch4_6_6
switch4_6_7
switch4_7_0
switch4_7_1
switch4_7_2
switch4_7_3
switch4_7_4
switch4_7_5
switch4_7_6
switch4_7_7
switch5_0_0
switch5_0_1
switch5_2_0
switch5_2_1
switch5_2_2
switch5_2_3
switch5_2_4
switch5_2_5
switch5_2_6
switch5_2_7
switch5_3_0
switch5_3_1
switch5_3_2
switch5_3_3
switch5_3_4
switch5_3_5
switch5_3_6
switch5_3_7
switch5_4_0
switch5_4_1
switch5_4_4
switch5_4_5
switch5_5_0
switch5_5_1
switch5_5_4
switch5_5_5
switch5_6_0
switch5_6_1
switch5_6_2
switch5_6_3
switch5_6_4
switch5_6_5
switch5_6_6
switch5_6_7
switch5_7_0
switch5_7_1
switch5_7_2
switch5_7_3
switch5_7_4
switch5_7_5
switch5_7_6
switch5_7_7
switch8_0_0
switch8_0_1
switch8_0_4
switch8_0_5
switch8_1_0
switch8_1_1
switch8_1_4
switch8_1_5
switch8_2_0
switch8_2_1
switch8_2_2
switch8_2_3
switch8_2_4
switch8_2_5
switch8_2_6
switch8_2_7
switch8_3_0
switch8_3_1
switch8_3_2
switch8_3_3
switch8_3_4
switch8_3_5
switch8_3_6
switch8_3_7
switch8_4_0
switch8_4_1
switch8_4_4
switch8_4_5
switch8_5_0
switch8_5_1
switch8_5_4
switch8_5_5
switch8_6_0
switch8_6_1
switch8_6_2
switch8_6_3
switch8_6_4
switch8_6_5
switch8_6_6
switch8_6_7
switch8_7_0
switch8_7_1
switch8_7_2
switch8_7_3
switch8_7_4
switch8_7_5
switch8_7_6
switch8_7_7
switch6_0_0
switch6_0_1
switch6_0_4
switch6_0_5
switch6_1_0
switch6_1_1
switch6_1_4
switch6_1_5
switch6_2_0
switch6_2_1
switch6_2_2
switch6_2_3
switch6_2_4
switch6_2_5
switch6_2_6
switch6_2_7
switch6_3_0
switch6_3_1
switch6_3_2
switch6_3_3
switch6_3_4
switch6_3_5
switch6_3_6
switch6_3_7
switch6_4_0
switch6_4_1
switch6_4_4
switch6_4_5
switch6_5_0
switch6_5_1
switch6_5_4
switch6_6_5
switch6_6_6
switch6_6_7
switch6_7_0
switch6_7_1
switch6_7_2
switch6_7_3
switch6_7_4
switch6_7_5
switch6_7_6
switch6_7_7
switch7_0_0
switch7_0_1
switch7_0_4
switch7_0_5
switch7_1_0
switch7_1_1
switch7_2_2
switch7_2_3
switch7_2_4
switch7_2_5
switch7_2_6
switch7_2_7
switch7_3_0
switch7_3_1
switch7_3_2
switch7_3_3
switch7_3_4
switch7_3_5
switch7_3_6
switch7_3_7
switch7_4_0
switch7_4_1
switch7_4_4
switch7_4_5
switch7_5_0
switch7_5_1
switch7_5_4
switch7_5_5
switch7_6_0
switch7_6_1
switch7_6_2
switch7_6_3
switch7_6_4
switch7_6_5
switch7_6_6
switch7_6_7
switch7_7_0
switch7_7_1
switch7_7_2
switch7_7_3
switch7_7_4
switch7_7_5
switch7_7_6
switch7_7_7

check for constant places
ok
check if there are places and transitions
ok
check if there are transitions without pre-places
ok
check if at least one transition is enabled in m0
ok
check if there are transitions that can never fire
ok

ptnet_zbdd.cc:66: Boundedness exception: net maybe not 1-bounded!

check for maximal unmarked siphon
found
The net has a maximal unmarked siphon:
aux5_input7
aux5_input6
in3_input3
aux8_input5
aux6_input6
aux8_input4
aux8_input1
aux8_input0
aux6_input7
aux7_input4
in3_input2
in3_input1
aux5_input3
aux5_input2
aux7_input0
aux7_input5
aux6_input3
aux7_input1
aux6_input2
in1_input2
in1_input3
in1_input4
in1_input5
in1_input6
in1_input7
in2_input0
in2_input1
in2_input4
in2_input5
in2_input6
in2_input7
in3_input6
in3_input7
in4_input0
in4_input1
in4_input2
in4_input3
in4_input4
in4_input5
in3_input0

The net has transition(s) that can never fire:
switch3_4_7
switch3_5_0
switch3_5_2
switch3_5_1
switch1_0_2
switch1_0_3
switch1_0_6
switch1_0_7
switch1_1_0
switch3_3_0
switch3_3_1
switch3_3_2
switch3_3_3
switch1_6_0
switch1_6_1
switch1_6_2
switch1_6_3
switch1_6_4
switch1_6_5
switch1_6_6
switch1_6_7
switch1_7_0
switch1_7_1
switch1_7_2
switch1_7_3
switch1_7_4
switch1_7_5
switch1_7_6
switch1_7_7
switch3_0_0
switch3_0_1
switch3_0_2
switch3_0_3
switch3_0_4
switch3_0_5
switch3_0_6
switch3_0_7
switch3_1_0
switch3_1_1
switch3_1_2
switch3_1_3
switch3_1_4
switch3_1_5
switch3_1_6
switch3_1_7
switch3_2_0
switch3_2_1
switch3_2_2
switch3_2_3
switch3_2_4
switch3_2_5
switch6_5_5
switch6_6_0
switch6_6_1
switch6_6_2
switch6_6_3
switch6_6_4
switch3_3_4
switch3_3_5
switch3_4_0
switch3_4_1
switch3_4_2
switch3_4_3
switch3_4_4
switch3_4_5
switch3_4_6
switch7_1_4
switch7_1_5
switch7_2_0
switch7_2_1
switch3_5_3
switch3_5_4
switch3_5_5
switch3_5_6
switch3_5_7
switch3_6_0
switch3_6_1
switch3_6_2
switch3_6_3
switch3_6_4
switch3_6_5
switch3_6_6
switch3_6_7
switch1_0_0
switch1_0_1
switch5_0_4
switch5_0_5
switch5_1_0
switch5_1_1
switch5_1_4
switch5_1_5
switch1_1_1
switch1_1_2
switch1_1_3
switch1_1_6
switch1_1_7
switch1_2_0
switch1_2_1
switch1_2_2
switch1_2_3
switch1_2_4
switch1_2_5
switch1_2_6
switch1_2_7
switch1_3_0
switch1_3_1
switch1_3_2
switch1_3_3
switch1_3_4
switch1_3_5
switch1_3_6
switch1_3_7
switch1_4_0
switch1_4_1
switch1_4_2
switch1_4_3
switch1_4_4
switch1_4_5
switch1_4_6
switch1_4_7
switch1_5_0
switch1_5_1
switch1_5_2
switch1_5_3
switch1_5_4
switch1_5_5
switch1_5_6
switch1_5_7
switch3_7_0
switch3_7_1
switch3_7_2
switch3_7_3
switch3_7_4
switch3_7_5
switch3_7_6
switch3_7_7
switch2_0_0
switch2_0_1
switch2_0_2
switch2_0_3
switch2_0_6
switch2_0_7
switch2_1_0
switch2_1_1
switch2_1_2
switch2_1_3
switch2_1_6
switch2_1_7
switch2_2_0
switch2_2_1
switch2_2_2
switch2_2_3
switch2_2_4
switch2_2_5
switch2_2_6
switch2_2_7
switch2_3_0
switch2_3_1
switch2_3_2
switch2_3_3
switch2_3_4
switch2_3_5
switch2_3_6
switch2_3_7
switch2_4_0
switch2_4_1
switch2_4_2
switch2_4_3
switch2_4_4
switch2_4_5
switch2_4_6
switch2_4_7
switch2_5_0
switch2_5_1
switch2_5_2
switch2_5_3
switch2_5_4
switch2_5_5
switch2_5_6
switch2_5_7
switch2_6_0
switch2_6_1
switch2_6_2
switch2_6_3
switch2_6_4
switch2_6_5
switch2_6_6
switch2_6_7
switch2_7_0
switch2_7_1
switch2_7_2
switch2_7_3
switch2_7_4
switch2_7_5
switch2_7_6
switch2_7_7
switch4_0_0
switch4_0_1
switch4_0_2
switch4_0_3
switch4_0_4
switch4_0_5
switch4_0_6
switch4_0_7
switch4_1_0
switch4_1_1
switch4_1_2
switch4_1_3
switch4_1_4
switch4_1_5
switch4_1_6
switch4_1_7
switch4_2_0
switch4_2_1
switch4_2_2
switch4_2_3
switch4_2_4
switch4_2_5
switch4_3_0
switch4_3_1
switch4_3_2
switch4_3_3
switch4_3_4
switch4_3_5
switch4_4_0
switch4_4_1
switch4_4_2
switch4_4_3
switch4_4_4
switch4_4_5
switch4_4_6
switch4_4_7
switch4_5_0
switch4_5_1
switch4_5_2
switch4_5_3
switch4_5_4
switch4_5_5
switch4_5_6
switch4_5_7
switch4_6_0
switch4_6_1
switch4_6_2
switch4_6_3
switch4_6_4
switch4_6_5
switch4_6_6
switch4_6_7
switch4_7_0
switch4_7_1
switch4_7_2
switch4_7_3
switch4_7_4
switch4_7_5
switch4_7_6
switch4_7_7
switch5_0_0
switch5_0_1
switch5_2_0
switch5_2_1
switch5_2_2
switch5_2_3
switch5_2_4
switch5_2_5
switch5_2_6
switch5_2_7
switch5_3_0
switch5_3_1
switch5_3_2
switch5_3_3
switch5_3_4
switch5_3_5
switch5_3_6
switch5_3_7
switch5_4_0
switch5_4_1
switch5_4_4
switch5_4_5
switch5_5_0
switch5_5_1
switch5_5_4
switch5_5_5
switch5_6_0
switch5_6_1
switch5_6_2
switch5_6_3
switch5_6_4
switch5_6_5
switch5_6_6
switch5_6_7
switch5_7_0
switch5_7_1
switch5_7_2
switch5_7_3
switch5_7_4
switch5_7_5
switch5_7_6
switch5_7_7
switch8_0_0
switch8_0_1
switch8_0_4
switch8_0_5
switch8_1_0
switch8_1_1
switch8_1_4
switch8_1_5
switch8_2_0
switch8_2_1
switch8_2_2
switch8_2_3
switch8_2_4
switch8_2_5
switch8_2_6
switch8_2_7
switch8_3_0
switch8_3_1
switch8_3_2
switch8_3_3
switch8_3_4
switch8_3_5
switch8_3_6
switch8_3_7
switch8_4_0
switch8_4_1
switch8_4_4
switch8_4_5
switch8_5_0
switch8_5_1
switch8_5_4
switch8_5_5
switch8_6_0
switch8_6_1
switch8_6_2
switch8_6_3
switch8_6_4
switch8_6_5
switch8_6_6
switch8_6_7
switch8_7_0
switch8_7_1
switch8_7_2
switch8_7_3
switch8_7_4
switch8_7_5
switch8_7_6
switch8_7_7
switch6_0_0
switch6_0_1
switch6_0_4
switch6_0_5
switch6_1_0
switch6_1_1
switch6_1_4
switch6_1_5
switch6_2_0
switch6_2_1
switch6_2_2
switch6_2_3
switch6_2_4
switch6_2_5
switch6_2_6
switch6_2_7
switch6_3_0
switch6_3_1
switch6_3_2
switch6_3_3
switch6_3_4
switch6_3_5
switch6_3_6
switch6_3_7
switch6_4_0
switch6_4_1
switch6_4_4
switch6_4_5
switch6_5_0
switch6_5_1
switch6_5_4
switch6_6_5
switch6_6_6
switch6_6_7
switch6_7_0
switch6_7_1
switch6_7_2
switch6_7_3
switch6_7_4
switch6_7_5
switch6_7_6
switch6_7_7
switch7_0_0
switch7_0_1
switch7_0_4
switch7_0_5
switch7_1_0
switch7_1_1
switch7_2_2
switch7_2_3
switch7_2_4
switch7_2_5
switch7_2_6
switch7_2_7
switch7_3_0
switch7_3_1
switch7_3_2
switch7_3_3
switch7_3_4
switch7_3_5
switch7_3_6
switch7_3_7
switch7_4_0
switch7_4_1
switch7_4_4
switch7_4_5
switch7_5_0
switch7_5_1
switch7_5_4
switch7_5_5
switch7_6_0
switch7_6_1
switch7_6_2
switch7_6_3
switch7_6_4
switch7_6_5
switch7_6_6
switch7_6_7
switch7_7_0
switch7_7_1
switch7_7_2
switch7_7_3
switch7_7_4
switch7_7_5
switch7_7_6
switch7_7_7

check for constant places
ok
check if there are places and transitions
ok
check if there are transitions without pre-places
ok
check if at least one transition is enabled in m0
ok
check if there are transitions that can never fire
ok


initing FirstDep: 0m 0.003sec

18222 23312 26903 41915
iterations count:424126 (414), effective:1828 (1)

initing FirstDep: 0m 0.005sec


iterations count:1025 (1), effective:1 (0)
46466 51055
iterations count:298758 (291), effective:1572 (1)

iterations count:6062 (5), effective:137 (0)

iterations count:1024 (1), effective:0 (0)
8750 11788
iterations count:244891 (239), effective:1777 (1)
35146 41069 45118 47464 49651 51810 53045 53979
iterations count:875740 (855), effective:4278 (4)

iterations count:47047 (45), effective:625 (0)

iterations count:47047 (45), effective:625 (0)

iterations count:47047 (45), effective:625 (0)
31248 37480 40573
iterations count:348267 (340), effective:2253 (2)

iterations count:1024 (1), effective:0 (0)

iterations count:47047 (45), effective:625 (0)

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-COL-01"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="marcie"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-COL-01.tgz
mv PermAdmissibility-COL-01 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool marcie"
echo " Input is PermAdmissibility-COL-01, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r031-blw7-149440474000345"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;