About the Execution of ITS-Tools for DLCround-PT-05a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
322.340 | 3456.00 | 8113.00 | 103.70 | TTFFFTTTFTTFTTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is DLCround-PT-05a, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r180-csrt-149580964300241
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-0
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-1
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-15
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-2
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-3
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-4
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-5
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-6
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-7
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-8
FORMULA_NAME DLCround-PT-05a-ReachabilityCardinality-9
=== Now, execution of the tool begins
BK_START 1496566067853
Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-reach command run as :
/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround\_PT\_05a\_flat\_flat\_mod,2.401e+09,0.213796,8760,184,21,1743,532,1130,1457,68,688,0
Total reachable state count : 2401000001
Verifying 16 reachability properties.
Invariant property DLCround-PT-05a-ReachabilityCardinality-0 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-0,0,0.215334,8840,1,0,1743,532,1148,1457,75,688,312
Invariant property DLCround-PT-05a-ReachabilityCardinality-1 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-1 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-1,0,0.215996,9148,1,0,1743,532,1154,1457,77,688,448
Reachability property DLCround-PT-05a-ReachabilityCardinality-2 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-2 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-05a-ReachabilityCardinality-2
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-2,0,0.216331,9148,1,0,1743,532,1159,1457,79,688,482
Invariant property DLCround-PT-05a-ReachabilityCardinality-3 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-3 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-3,0,0.21728,9148,1,0,1743,532,1174,1457,81,688,910
Reachability property DLCround-PT-05a-ReachabilityCardinality-4 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-4 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-4,2.1609e+08,0.217845,9148,96,32,1743,532,1179,1457,83,688,940
Reachability property DLCround-PT-05a-ReachabilityCardinality-5 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-5 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-05a-ReachabilityCardinality-5
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-5,0,0.217986,9148,1,0,1743,532,1181,1457,84,688,940
Invariant property DLCround-PT-05a-ReachabilityCardinality-6 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-6 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-6,0,0.218973,9148,1,0,1743,532,1196,1457,88,688,1156
Invariant property DLCround-PT-05a-ReachabilityCardinality-7 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-7 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-7,0,0.219831,9148,1,0,1743,532,1210,1457,91,688,1324
Reachability property DLCround-PT-05a-ReachabilityCardinality-8 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-8 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-05a-ReachabilityCardinality-8
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-8,0,0.220726,9148,1,0,1743,532,1235,1457,95,688,1466
Reachability property DLCround-PT-05a-ReachabilityCardinality-9 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-9 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-05a-ReachabilityCardinality-9
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-9,0,0.220849,9148,1,0,1743,532,1236,1457,95,688,1466
Reachability property DLCround-PT-05a-ReachabilityCardinality-10 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-05a-ReachabilityCardinality-10
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-10,0,0.221565,9148,1,0,1743,532,1254,1457,99,688,1516
Invariant property DLCround-PT-05a-ReachabilityCardinality-11 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-11,2.1609e+08,0.222746,9148,96,30,1743,532,1275,1457,110,688,1643
Reachability property DLCround-PT-05a-ReachabilityCardinality-12 does not hold.
FORMULA DLCround-PT-05a-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : DLCround-PT-05a-ReachabilityCardinality-12
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-12,0,0.222914,9148,1,0,1743,532,1276,1457,110,688,1643
Invariant property DLCround-PT-05a-ReachabilityCardinality-13 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-13,0,0.223269,9148,1,0,1743,532,1279,1457,110,688,1679
Reachability property DLCround-PT-05a-ReachabilityCardinality-14 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-14,3.087e+07,0.224839,9148,97,36,1743,532,1299,1457,110,688,1796
Invariant property DLCround-PT-05a-ReachabilityCardinality-15 is true.
FORMULA DLCround-PT-05a-ReachabilityCardinality-15 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
DLCround-PT-05a-ReachabilityCardinality-15,0,0.225088,9148,1,0,1743,532,1302,1457,110,688,1828
Exit code :0
BK_STOP 1496566071309
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityCardinality -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 04, 2017 8:47:49 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 04, 2017 8:47:49 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 119 ms
Jun 04, 2017 8:47:49 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 167 places.
Jun 04, 2017 8:47:49 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 1055 transitions.
Jun 04, 2017 8:47:49 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Found NUPN structural information;
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 162 ms
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 111 ms
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays to variables to allow decomposition.
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 145 ms
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 1614 redundant transitions.
Jun 04, 2017 8:47:50 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 23 ms
Jun 04, 2017 8:47:50 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
Read property : DLCround-PT-05a-ReachabilityCardinality-0 with value :(((((u15.p93==0)||(u10.p82==1))||(u6.p40>=2))&&(u6.p46>=2))||((u26.p104==0)||(u45.p123==1)))
Read property : DLCround-PT-05a-ReachabilityCardinality-1 with value :(((u3.p21==0)||(u14.p92==1))||(u10.p82>=1))
Read property : DLCround-PT-05a-ReachabilityCardinality-2 with value :(!((u10.p79==0)||(u79.p157==1)))
Read property : DLCround-PT-05a-ReachabilityCardinality-3 with value :(((u43.p121==0)||(u35.p113==1))||(((u1.p5==0)||(u88.p166==1))&&(!((u51.p129==0)||(u37.p115==1)))))
Read property : DLCround-PT-05a-ReachabilityCardinality-4 with value :(!((u7.p52==0)||(u8.p64==1)))
Read property : DLCround-PT-05a-ReachabilityCardinality-5 with value :(u81.p159>=3)
Read property : DLCround-PT-05a-ReachabilityCardinality-6 with value :(((u12.p90==0)||(u16.p94==1))||(!((u10.p84>=3)||((u6.p40==0)||(u10.p84==1)))))
Read property : DLCround-PT-05a-ReachabilityCardinality-7 with value :((((u27.p105>=2)||(u89.p0>=2))||(u76.p154>=1))||((u19.p97==0)||(u7.p58==1)))
Read property : DLCround-PT-05a-ReachabilityCardinality-8 with value :(((u8.p61==0)||(u66.p144==1))&&((((u33.p111==0)||(u75.p153==1))||((u5.p36==0)||(u33.p111==1)))&&((u10.p85>=1)&&(u9.p74>=3))))
Read property : DLCround-PT-05a-ReachabilityCardinality-9 with value :(u82.p160>=3)
Read property : DLCround-PT-05a-ReachabilityCardinality-10 with value :(((u39.p117==0)||(u4.p25==1))&&(((u8.p63>=3)&&((u12.p90==0)||(u1.p2==1)))&&((u9.p72>=2)||(u4.p28>=1))))
Read property : DLCround-PT-05a-ReachabilityCardinality-11 with value :((((u7.p57>=1)||(u7.p57>=3))&&(((u8.p65==0)||(u5.p33==1))||(u5.p32>=3)))||((u7.p54==0)||(u8.p60==1)))
Read property : DLCround-PT-05a-ReachabilityCardinality-12 with value :(u56.p134>=2)
Read property : DLCround-PT-05a-ReachabilityCardinality-13 with value :((u8.p65==0)||(u65.p143==1))
Read property : DLCround-PT-05a-ReachabilityCardinality-14 with value :((((u4.p25>=1)&&((u49.p127==0)||(u35.p113==1)))&&((u55.p133==0)||(u62.p140==1)))&&(((u80.p158>=1)||(u2.p12>=1))&&((u9.p72>=1)||((u69.p147==0)||(u10.p84==1)))))
Read property : DLCround-PT-05a-ReachabilityCardinality-15 with value :((u74.p152==0)||(u62.p140==1))
built 157 ordering constraints for composite.
Jun 04, 2017 8:47:50 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 0 in 711 ms.
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05a"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05a.tgz
mv DLCround-PT-05a execution
# this is for BenchKit: explicit launching of the test
cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is DLCround-PT-05a, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r180-csrt-149580964300241"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;