Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_SafeBus-COL-03, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r150-csrt-149443434800188
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SafeBus-COL-03-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1496657060578


Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-ctl command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 97 rows 57 cols
invariant : 1'Dom0:AMC_0 + -1'Dom0:wait_ack_0 + 1'Dom1:AMC_1 + -1'Dom1:wait_ack_1 + 1'Dom2:AMC_2 + -1'Dom2:wait_ack_2 + 1'It0:cable_used_0 + -1'It0:FMC_0 + -1'It0:wait_cable_0 + 1'It0:RMC_0= 0
invariant : 1'Dom6:wait_ack_6 + 1'Dom7:wait_ack_7 + 1'Dom8:wait_ack_8 + 1'It2:wait_cable_2 + 1'It2:listen_2 + 1'It2:wait_msg_2 + 1'It2:loop_em_2= 1
invariant : 1'Dom6:wait_ack_6 + 1'Dom7:wait_ack_7 + 1'Dom8:wait_ack_8 + 1'cable_free:cable_free[0] + -1'FMCb:FMCb[0] + 1'It0:cable_used_0 + -1'It0:FMC_0 + 1'It1:cable_used_1 + -1'It1:FMC_1 + 1'It2:PMC_2= 0
invariant : 1'Dom0:AMC_0 + -1'Dom2:AMC_2 + 1'Dom3:AMC_3 + -1'Dom5:AMC_5 + 1'Dom6:AMC_6 + -1'Dom8:AMC_8 + -1'It0:Cpt2_0 + 1'It0:Cpt1_0= 0
invariant : 1'Dom0:wait_ack_0 + 1'Dom1:wait_ack_1 + 1'Dom2:wait_ack_2 + -1'It0:cable_used_0 + 1'It0:FMC_0 + 1'It0:PMC_0= 0
invariant : 1'Dom0:wait_ack_0 + 1'Dom1:wait_ack_1 + 1'Dom2:wait_ack_2 + 1'It0:wait_cable_0 + 1'It0:listen_0 + 1'It0:wait_msg_0 + 1'It0:loop_em_0= 1
invariant : -1'Dom1:AMC_1 + 1'Dom2:AMC_2 + -1'Dom4:AMC_4 + 1'Dom5:AMC_5 + -1'Dom7:AMC_7 + 1'Dom8:AMC_8 + 1'It0:Cpt2_0 + 1'It1:Cpt2_1 + 1'It2:Cpt1_2= 1
invariant : -1'Dom0:AMC_0 + 1'Dom1:AMC_1 + -1'Dom3:AMC_3 + 1'Dom4:AMC_4 + -1'Dom6:AMC_6 + 1'Dom7:AMC_7 + -1'It1:Cpt2_1 + 1'It1:Cpt1_1= 0
invariant : 1'Dom3:wait_ack_3 + 1'Dom4:wait_ack_4 + 1'Dom5:wait_ack_5 + -1'It1:cable_used_1 + 1'It1:FMC_1 + 1'It1:PMC_1= 0
invariant : 1'Dom3:AMC_3 + -1'Dom3:wait_ack_3 + 1'Dom4:AMC_4 + -1'Dom4:wait_ack_4 + 1'Dom5:AMC_5 + -1'Dom5:wait_ack_5 + 1'It1:cable_used_1 + -1'It1:FMC_1 + -1'It1:wait_cable_1 + 1'It1:RMC_1= 0
invariant : -1'Dom0:wait_ack_0 + -1'Dom1:wait_ack_1 + -1'Dom2:wait_ack_2 + -1'Dom3:wait_ack_3 + -1'Dom4:wait_ack_4 + -1'Dom5:wait_ack_5 + -1'Dom6:wait_ack_6 + -1'Dom7:wait_ack_7 + -1'Dom8:wait_ack_8 + 1'ACK:ACK[0] + 1'T_out:T_out[0] + 1'It0:MSG_0 + 1'It1:MSG_1 + 1'It2:MSG_2= 0
invariant : 1'It0:Cpt2_0 + 1'It1:Cpt2_1 + 1'It2:Cpt2_2= 1
invariant : 1'Dom6:AMC_6 + -1'Dom6:wait_ack_6 + 1'Dom7:AMC_7 + -1'Dom7:wait_ack_7 + 1'Dom8:AMC_8 + -1'Dom8:wait_ack_8 + -1'cable_free:cable_free[0] + 1'FMCb:FMCb[0] + -1'It0:cable_used_0 + 1'It0:FMC_0 + -1'It1:cable_used_1 + 1'It1:FMC_1 + -1'It2:wait_cable_2 + 1'It2:RMC_2= 0
invariant : 1'Dom3:wait_ack_3 + 1'Dom4:wait_ack_4 + 1'Dom5:wait_ack_5 + 1'It1:wait_cable_1 + 1'It1:listen_1 + 1'It1:wait_msg_1 + 1'It1:loop_em_1= 1
invariant : 1'FMCb:FMCb[0] + 1'It0:FMC_0 + 1'It1:FMC_1 + 1'It2:FMC_2= 1
invariant : 1'R_tout:R_tout[0] + 1'S_tout:S_tout[0]= 1
invariant : 1'cable_free:cable_free[0] + 1'It0:cable_used_0 + 1'It1:cable_used_1 + 1'It2:cable_used_2= 1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,4650,0.836846,28756,897,254,56932,1682,225,37021,57,37888,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,0,1.08956,28756,1,0,56932,16853,788,37021,228,77819,81583

System contains 0 deadlocks (shown below if less than --print-limit option) !
FORMULA SafeBus-COL-03-ReachabilityDeadlock-0 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
[ 0 ]
Exit code :0

BK_STOP 1496657065497

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityDeadlock = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 05, 2017 10:04:22 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 05, 2017 10:04:22 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1342 ms
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 20 places.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :Dom->AMC,wait_ack,
Dot->cable_free,ACK,T_out,R_tout,S_tout,FMCb,
It->Cpt2,Cpt1,msgl,cable_used,FMC,wait_cable,listen,RMC,PMC,MSG,wait_msg,loop_em,

Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 14 transitions.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.logic.togal.ToGalTransformer toGal
WARNING: Unknown predicate type in boolean expression fr.lip6.move.gal.logic.impl.DeadlockImpl
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $x and $y of transition C_refuse
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $j of transition C_free
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $x and $y of transition C_provide
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $r and $i of transition I_rec1
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $j of transition I_emit
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $j of transition I_refused
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $r and $i of transition I_rec2
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 3 instantiations of transitions. Total transitions/syncs built is 112
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.DomainAnalyzer computeVariableDomains
INFO: Found a total of 1 fixed domain variables (out of 60 variables) in GAL type Document
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Found a total of 3 constant array cells/variables (out of 60 variables) in type Document
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: msgl[0-2],
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Simplifier simplifyConstantVariables
INFO: Simplified 6 expressions due to constant valuations.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property SafeBus-COL-03-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 74 ms
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays Cpt2, Cpt1, cable_used, FMC, AMC, wait_ack, wait_cable, listen, RMC, PMC, MSG, wait_msg, loop_em to variables to allow decomposition.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 96 redundant transitions.
Jun 05, 2017 10:04:23 AM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property SafeBus-COL-03-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
Jun 05, 2017 10:04:23 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 9 ms
Jun 05, 2017 10:04:24 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 17 place invariants in 32 ms
Jun 05, 2017 10:04:24 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 57 variables to be positive in 242 ms
Jun 05, 2017 10:04:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 97 transitions.
Jun 05, 2017 10:04:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/97 took 4 ms. Total solver calls (SAT/UNSAT): 18(1/17)
Jun 05, 2017 10:04:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 396 ms. Total solver calls (SAT/UNSAT): 2314(262/2052)
Jun 05, 2017 10:04:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 97 transitions.
Jun 05, 2017 10:04:25 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]
built 77 ordering constraints for composite.
Reverse transition relation is NOT exact ! Due to transitions I_reemit, C_free, I_rec1, loss_m, I_rec2, I_ask2_0, I_ask2_1, I_ask2_2, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/14/8/22

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_SafeBus-COL-03"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_SafeBus-COL-03.tgz
mv S_SafeBus-COL-03 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_SafeBus-COL-03, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r150-csrt-149443434800188"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;