About the Execution of ITS-Tools for S_ResAllocation-PT-R003C020
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 442.790 | 8161.00 | 27330.00 | 131.80 | TFFFTTTFFFFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_ResAllocation-PT-R003C020, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r150-csrt-149443434700097
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-0
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-1
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-10
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-11
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-12
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-13
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-14
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-15
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-2
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-3
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-4
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-5
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-6
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-7
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-8
FORMULA_NAME ResAllocation-PT-R003C020-ReachabilityCardinality-9
=== Now, execution of the tool begins
BK_START 1496651989829
Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-reach command run as :
/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 80 rows 120 cols
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + 1'p_16_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + 1'p_13_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + -1'r_16_2 + 1'r_17_2 + 1'p_18_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + 1'p_8_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + 1'p_15_2= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + -1'r_15_2 + 1'r_16_2 + -1'r_17_2 + 1'r_18_2 + 1'p_19_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + 1'p_11_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + 1'p_11_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + 1'p_10_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + 1'p_7_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + 1'p_12_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + 1'p_15_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + -1'r_16_1 + 1'r_17_1 + -1'r_18_1 + 1'r_19_1= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + 1'p_4_1= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + 1'p_12_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + 1'p_10_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + -1'r_15_0 + 1'r_16_0 + 1'p_17_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + -1'r_16_2 + 1'r_17_2 + -1'r_18_2 + 1'r_19_2= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + 1'p_3_2= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + 1'p_7_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + 1'p_7_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + 1'p_4_0= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + 1'p_6_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + 1'p_2_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + 1'p_6_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + 1'p_1_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + 1'p_13_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + 1'p_16_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + -1'r_16_0 + 1'r_17_0 + -1'r_18_0 + 1'r_19_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + 1'p_14_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + 1'p_5_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + 1'p_2_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + 1'p_3_1= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + -1'r_15_1 + 1'r_16_1 + 1'p_17_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + -1'r_15_0 + 1'r_16_0 + -1'r_17_0 + 1'r_18_0 + 1'p_19_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + 1'p_6_2= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + -1'r_16_1 + 1'r_17_1 + 1'p_18_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + 1'p_5_2= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + -1'r_15_2 + 1'r_16_2 + 1'p_17_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + 1'p_8_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + 1'p_12_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + 1'p_3_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + 1'p_9_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + 1'p_1_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + -1'r_15_1 + 1'r_16_1 + -1'r_17_1 + 1'r_18_1 + 1'p_19_1= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + 1'p_2_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + 1'p_1_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + 1'p_9_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + 1'p_10_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + 1'p_13_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + -1'r_16_0 + 1'r_17_0 + 1'p_18_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + 1'p_5_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + 1'p_11_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + 1'p_14_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + 1'p_8_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + 1'p_9_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + 1'p_16_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + 1'p_15_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + 1'p_14_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + 1'p_4_2= 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 80 rows 120 cols
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + 1'p_16_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + 1'p_13_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + -1'r_16_2 + 1'r_17_2 + 1'p_18_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + 1'p_8_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + 1'p_15_2= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + -1'r_15_2 + 1'r_16_2 + -1'r_17_2 + 1'r_18_2 + 1'p_19_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + 1'p_11_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + 1'p_11_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + 1'p_10_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + 1'p_7_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + 1'p_12_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + 1'p_15_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + -1'r_16_1 + 1'r_17_1 + -1'r_18_1 + 1'r_19_1= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + 1'p_4_1= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + 1'p_12_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + 1'p_10_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + -1'r_15_0 + 1'r_16_0 + 1'p_17_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + -1'r_16_2 + 1'r_17_2 + -1'r_18_2 + 1'r_19_2= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + 1'p_3_2= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + 1'p_7_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + 1'p_7_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + 1'p_4_0= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + 1'p_6_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + 1'p_2_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + 1'p_6_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + 1'p_1_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + 1'p_13_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + -1'r_14_2 + 1'r_15_2 + 1'p_16_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + -1'r_16_0 + 1'r_17_0 + -1'r_18_0 + 1'r_19_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + 1'p_14_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + 1'p_5_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + 1'p_2_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + 1'p_3_1= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + -1'r_15_1 + 1'r_16_1 + 1'p_17_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0 + -1'r_15_0 + 1'r_16_0 + -1'r_17_0 + 1'r_18_0 + 1'p_19_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + 1'p_6_2= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + -1'r_14_1 + 1'r_15_1 + -1'r_16_1 + 1'r_17_1 + 1'p_18_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + 1'p_5_2= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2 + -1'r_15_2 + 1'r_16_2 + 1'p_17_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + 1'p_8_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + 1'p_12_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + 1'p_3_0= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + 1'p_9_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + 1'p_1_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + -1'r_15_1 + 1'r_16_1 + -1'r_17_1 + 1'r_18_1 + 1'p_19_1= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + 1'p_2_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + 1'p_1_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + 1'p_9_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + 1'p_10_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + 1'p_13_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + -1'r_16_0 + 1'r_17_0 + 1'p_18_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + 1'p_5_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + 1'p_11_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + 1'p_14_1= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + 1'p_8_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + 1'p_9_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + -1'r_14_0 + 1'r_15_0 + 1'p_16_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1 + 1'p_15_1= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + 1'p_14_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + 1'p_4_2= 0
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-0 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-1 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-2 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-3 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O3, model.c], workingDir=/home/mcc/execution]
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-4 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-6 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-7 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-8 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Exit code :0
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Exit code :0
Exit code :1
Found Violation
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-5 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-11 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Exit code :1
Found Violation
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-9 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Exit code :1
Found Violation
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-10 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-12 TRUE TECHNIQUES SAT_SMT K_INDUCTION(0)
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation\_PT\_R003C020\_flat\_flat,4.06455e+11,4.62078,123872,2,35492,5,514240,6,0,563,729698,0
Total reachable state count : 406454747136
Verifying 16 reachability properties.
Invariant property ResAllocation-PT-R003C020-ReachabilityCardinality-0 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-0,0,4.64746,124100,1,0,5,514240,7,0,569,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-1 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-1,0,4.66218,124168,1,0,5,514240,8,0,578,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-2 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-2
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-2,0,4.74557,124168,1,0,5,514240,9,0,584,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-3 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-3
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-3,0,4.74594,124168,1,0,5,514240,10,0,585,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-4 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-4
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-4,0,4.76928,124168,1,0,5,514240,11,0,591,729698,0
Invariant property ResAllocation-PT-R003C020-ReachabilityCardinality-5 does not hold.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-5,2.59042e+10,4.80842,124168,2,13886,6,514240,12,0,597,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-6 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-6
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-6,0,4.81844,124168,1,0,6,514240,13,0,607,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-7 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-7
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-7,0,4.82643,124168,1,0,6,514240,14,0,608,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-8 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-8
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-8,0,4.8276,124168,1,0,6,514240,15,0,609,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-9 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-9,2048,4.82865,124168,2,176,7,514240,16,0,620,729698,0
Invariant property ResAllocation-PT-R003C020-ReachabilityCardinality-10 does not hold.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-10,2.64792e+09,4.85811,124168,2,3359,8,514240,17,0,639,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-11 does not hold.
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-11
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-11,0,4.90676,124168,1,0,8,514240,18,0,640,729698,0
Invariant property ResAllocation-PT-R003C020-ReachabilityCardinality-12 is true.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-12,0,4.9263,124168,1,0,8,514240,19,0,641,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-13 is true.
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-13,84,4.92927,124168,2,142,9,514240,20,0,662,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-14 is true.
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-14,3.76108e+09,4.99574,124168,2,4643,10,514240,21,0,690,729698,0
Reachability property ResAllocation-PT-R003C020-ReachabilityCardinality-15 does not hold.
FORMULA ResAllocation-PT-R003C020-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C020-ReachabilityCardinality-15
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C020-ReachabilityCardinality-15,0,5.08202,124168,1,0,10,514240,22,0,700,729698,0
Exit code :0
BK_STOP 1496651997990
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityCardinality -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 05, 2017 8:39:51 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 05, 2017 8:39:51 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 76 ms
Jun 05, 2017 8:39:51 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 120 places.
Jun 05, 2017 8:39:51 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 80 transitions.
Jun 05, 2017 8:39:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 52 ms
Jun 05, 2017 8:39:51 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 19 ms
Jun 05, 2017 8:39:51 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 10 ms
Jun 05, 2017 8:39:51 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 29 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 253 ms.
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-0(UNSAT) depth K=0 took 5 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-1(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-2(UNSAT) depth K=0 took 2 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-3(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 60 place invariants in 30 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-4(UNSAT) depth K=0 took 10 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-5(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-6(UNSAT) depth K=0 took 2 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-7(UNSAT) depth K=0 took 7 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-8(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-9(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-10(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-11(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-12(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-13(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-14(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-15(UNSAT) depth K=0 took 7 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 60 place invariants in 15 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-0(UNSAT) depth K=1 took 229 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-1(UNSAT) depth K=1 took 119 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-2(UNSAT) depth K=1 took 112 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-3(UNSAT) depth K=1 took 58 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-4(UNSAT) depth K=1 took 57 ms
Jun 05, 2017 8:39:52 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 120 variables to be positive in 612 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 120 variables to be positive in 728 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 80 transitions.
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/80 took 2 ms. Total solver calls (SAT/UNSAT): 4(2/2)
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-5(UNSAT) depth K=1 took 162 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-6(UNSAT) depth K=1 took 59 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-7(UNSAT) depth K=1 took 58 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-8(UNSAT) depth K=1 took 59 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 328 ms. Total solver calls (SAT/UNSAT): 428(194/234)
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 80 transitions.
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-9(UNSAT) depth K=1 took 117 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-10(UNSAT) depth K=1 took 111 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-11(UNSAT) depth K=1 took 58 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 221 ms. Total solver calls (SAT/UNSAT): 428(158/270)
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 80 transitions.
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant ResAllocation-PT-R003C020-ReachabilityCardinality-0
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-0
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-0(TRUE) depth K=0 took 687 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-12(UNSAT) depth K=1 took 115 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-13(UNSAT) depth K=1 took 128 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-14(UNSAT) depth K=1 took 108 ms
Jun 05, 2017 8:39:53 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-15(UNSAT) depth K=1 took 58 ms
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-1
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-1
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-1(FALSE) depth K=0 took 404 ms
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-2
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-2
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-2(FALSE) depth K=0 took 265 ms
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of enabling matrix(43/80) took 1004 ms. Total solver calls (SAT/UNSAT): 2574(2420/154)
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-3
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-3
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-3(FALSE) depth K=0 took 265 ms
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-1(UNSAT) depth K=2 took 720 ms
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished enabling matrix. took 1230 ms. Total solver calls (SAT/UNSAT): 3240(2967/273)
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 80 transitions.
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 1 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 2687ms conformant to PINS in folder :/home/mcc/execution
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-4
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-4
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-4(FALSE) depth K=0 took 267 ms
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesResAllocation-PT-R003C020-ReachabilityCardinality-5
Jun 05, 2017 8:39:54 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-5(SAT) depth K=0 took 125 ms
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-6
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-6
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-6(FALSE) depth K=0 took 268 ms
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-7
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-7
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-7(FALSE) depth K=0 took 266 ms
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-2(UNSAT) depth K=2 took 896 ms
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-8
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-8
Jun 05, 2017 8:39:55 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-8(FALSE) depth K=0 took 265 ms
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-3(UNSAT) depth K=2 took 635 ms
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesResAllocation-PT-R003C020-ReachabilityCardinality-9
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-9(SAT) depth K=0 took 478 ms
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesResAllocation-PT-R003C020-ReachabilityCardinality-10
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-10(SAT) depth K=0 took 276 ms
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-seq, ./gal.so, -p, --pins-guards, --when, -i, ResAllocationPTR003C020ReachabilityCardinality5==true], workingDir=/home/mcc/execution]
pins2lts-seq, 0.000: Registering PINS so language module
pins2lts-seq, 0.000: Loading model from ./gal.so
pins2lts-seq, 0.000: library has no initializer
pins2lts-seq, 0.000: loading model GAL
pins2lts-seq, 0.001: completed loading model GAL
pins2lts-seq, 0.001: Initializing POR dependencies: labels 96, guards 80
pins2lts-seq, 0.007: Expression is: (ResAllocationPTR003C020ReachabilityCardinality5 == true )
pins2lts-seq, 0.007: Forcing the use of a cycle proviso. For best results use --proviso=color.
pins2lts-seq, 0.007: There are 96 state labels and 1 edge labels
pins2lts-seq, 0.007: State length is 120, there are 80 groups
pins2lts-seq, 0.007: Running dfs search strategy
pins2lts-seq, 0.007: Using a tree for state storage
pins2lts-seq, 0.007: Visible groups: 0 / 80, labels: 1 / 96
pins2lts-seq, 0.007: POR cycle proviso: stack
pins2lts-seq, 0.042:
pins2lts-seq, 0.042: Invariant violation (ResAllocationPTR003C020ReachabilityCardinality5==true) found at depth 51!
pins2lts-seq, 0.042:
pins2lts-seq, 0.042: exiting now
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C020-ReachabilityCardinality-11
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-11
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-11(FALSE) depth K=0 took 264 ms
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-seq, ./gal.so, -p, --pins-guards, --when, -i, ResAllocationPTR003C020ReachabilityCardinality9==true], workingDir=/home/mcc/execution]
pins2lts-seq, 0.000: Registering PINS so language module
pins2lts-seq, 0.000: Loading model from ./gal.so
pins2lts-seq, 0.000: library has no initializer
pins2lts-seq, 0.000: loading model GAL
pins2lts-seq, 0.000: completed loading model GAL
pins2lts-seq, 0.000: Initializing POR dependencies: labels 96, guards 80
pins2lts-seq, 0.006: Expression is: (ResAllocationPTR003C020ReachabilityCardinality9 == true )
pins2lts-seq, 0.006: Forcing the use of a cycle proviso. For best results use --proviso=color.
pins2lts-seq, 0.007: There are 96 state labels and 1 edge labels
pins2lts-seq, 0.007: State length is 120, there are 80 groups
pins2lts-seq, 0.007: Running dfs search strategy
pins2lts-seq, 0.007: Using a tree for state storage
pins2lts-seq, 0.007: Visible groups: 0 / 80, labels: 1 / 96
pins2lts-seq, 0.007: POR cycle proviso: stack
pins2lts-seq, 0.085:
pins2lts-seq, 0.085: Invariant violation (ResAllocationPTR003C020ReachabilityCardinality9==true) found at depth 34!
pins2lts-seq, 0.085:
pins2lts-seq, 0.085: exiting now
Jun 05, 2017 8:39:56 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-seq, ./gal.so, -p, --pins-guards, --when, -i, ResAllocationPTR003C020ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
pins2lts-seq, 0.000: Registering PINS so language module
pins2lts-seq, 0.000: Loading model from ./gal.so
pins2lts-seq, 0.000: library has no initializer
pins2lts-seq, 0.000: loading model GAL
pins2lts-seq, 0.000: completed loading model GAL
pins2lts-seq, 0.000: Initializing POR dependencies: labels 96, guards 80
pins2lts-seq, 0.005: Expression is: (ResAllocationPTR003C020ReachabilityCardinality10 == true )
pins2lts-seq, 0.005: Forcing the use of a cycle proviso. For best results use --proviso=color.
pins2lts-seq, 0.006: There are 96 state labels and 1 edge labels
pins2lts-seq, 0.006: State length is 120, there are 80 groups
pins2lts-seq, 0.006: Running dfs search strategy
pins2lts-seq, 0.006: Using a tree for state storage
pins2lts-seq, 0.006: Visible groups: 0 / 80, labels: 1 / 96
pins2lts-seq, 0.006: POR cycle proviso: stack
pins2lts-seq, 0.010:
pins2lts-seq, 0.010: Invariant violation (ResAllocationPTR003C020ReachabilityCardinality10==true) found at depth 44!
pins2lts-seq, 0.010:
pins2lts-seq, 0.010: exiting now
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved invariant ResAllocation-PT-R003C020-ReachabilityCardinality-12
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C020-ReachabilityCardinality-12
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-12(TRUE) depth K=0 took 267 ms
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-4(UNSAT) depth K=2 took 910 ms
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is SAT, non conclusive we might be starting from unreachable statesResAllocation-PT-R003C020-ReachabilityCardinality-13
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C020-ReachabilityCardinality-13(SAT) depth K=0 took 552 ms
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-0 with value :(!((r_8_1<=p_3_2)&&((r_10_2>=2)||(r_12_0>=3))))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-1 with value :((((r_7_1>=2)&&(r_17_0>=3))&&((p_2_1<=r_6_2)&&(r_16_1<=p_13_0)))&&(r_8_2<=r_14_0))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-2 with value :((r_19_0>=2)&&(p_10_0<=r_8_2))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-3 with value :(p_2_2>=3)
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-4 with value :(((!(r_5_0>=3))||(p_11_1>=1))&&(r_11_0>=2))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-5 with value :(p_5_0<=p_8_2)
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-6 with value :(((!(p_5_2>=3))||((p_4_2<=r_2_1)||(p_17_0<=p_8_1)))&&((r_2_1>=3)&&((p_16_2>=1)||(p_10_2>=1))))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-7 with value :(p_3_1>=3)
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-8 with value :(p_14_2>=3)
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-9 with value :(!((!(r_12_1<=p_15_1))||((r_19_1>=1)&&(r_0_1<=r_18_2))))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-10 with value :((p_17_1<=r_6_2)||((r_3_1>=1)&&((r_0_1>=1)||(r_16_1<=p_18_1))))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-11 with value :(r_18_0>=2)
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-12 with value :(!(r_14_0>=2))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-13 with value :((((r_1_0<=p_11_0)&&(p_8_0>=2))&&((r_2_2<=p_11_0)&&(r_17_1<=p_10_1)))||(!((p_3_0>=1)||(r_8_0<=r_19_0))))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-14 with value :((!((r_11_2<=p_2_2)||(p_17_0<=r_7_2)))&&(((r_18_1<=p_10_0)||(r_1_1>=1))||((p_5_1>=2)||(p_10_1<=p_12_1))))
Read property : ResAllocation-PT-R003C020-ReachabilityCardinality-15 with value :((r_2_0>=2)&&((!(p_2_2>=1))||(p_3_2<=p_2_0)))
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.itstools.ProcessController$1 run
WARNING: null
Jun 05, 2017 8:39:57 AM fr.lip6.move.gal.itstools.ProcessController forwardStream
WARNING: Stream closed
LTSmin timed out on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-seq, ./gal.so, -p, --pins-guards, --when, -i, ResAllocationPTR003C020ReachabilityCardinality12==true], workingDir=/home/mcc/execution]
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_ResAllocation-PT-R003C020"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/S_ResAllocation-PT-R003C020.tgz
mv S_ResAllocation-PT-R003C020 execution
# this is for BenchKit: explicit launching of the test
cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_ResAllocation-PT-R003C020, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r150-csrt-149443434700097"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;