Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_ResAllocation-PT-R003C015, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r150-csrt-149443434700088
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-0
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-1
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-10
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-11
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-12
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-13
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-14
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-15
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-2
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-3
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-4
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-5
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-6
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-7
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-8
FORMULA_NAME ResAllocation-PT-R003C015-ReachabilityCardinality-9

=== Now, execution of the tool begins

BK_START 1496651943349

Using solver YICES2 to compute partial order matrices.

Built C files in :
/home/mcc/execution
its-reach command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness
Loading property file ReachabilityCardinality.prop.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 60 rows 90 cols
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + 1'p_6_2= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + 1'p_14_1= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + 1'p_4_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + 1'p_3_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + 1'p_11_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + 1'p_13_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + 1'p_6_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + 1'p_8_2= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + 1'p_10_1= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + 1'p_10_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + 1'p_13_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + 1'p_10_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + 1'p_11_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + 1'p_12_0= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + 1'p_2_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + 1'p_7_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + 1'p_14_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + 1'p_9_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + 1'p_2_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + 1'p_1_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + 1'p_3_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + 1'p_6_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + 1'p_5_2= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + 1'p_14_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + 1'p_5_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + 1'p_11_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + 1'p_2_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + 1'p_7_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + 1'p_9_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + 1'p_13_1= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + 1'p_8_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + 1'p_3_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + 1'p_1_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + 1'p_8_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + 1'p_1_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + 1'p_12_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + 1'p_5_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + 1'p_12_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + 1'p_7_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + 1'p_9_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + 1'p_4_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + 1'p_4_0= 0
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 60 rows 90 cols
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + 1'p_6_2= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + -1'r_13_2 + 1'r_14_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + -1'r_12_1 + 1'r_13_1 + 1'p_14_1= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + 1'p_4_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + 1'p_3_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + 1'p_11_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + 1'p_13_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + 1'p_6_0= 0
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + 1'p_8_2= 0
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + 1'p_10_1= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + 1'p_10_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + -1'r_11_2 + 1'r_12_2 + 1'p_13_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + 1'p_10_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + 1'p_11_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + 1'p_12_0= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + 1'p_2_0= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + 1'p_7_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + -1'r_12_2 + 1'r_13_2 + 1'p_14_2= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + 1'p_9_0= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + 1'p_2_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + 1'p_1_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + 1'p_3_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + 1'p_6_1= 0
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + 1'p_5_2= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + -1'r_8_0 + 1'r_9_0 + -1'r_10_0 + 1'r_11_0 + -1'r_12_0 + 1'r_13_0 + 1'p_14_0= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + 1'p_5_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + -1'r_9_2 + 1'r_10_2 + 1'p_11_2= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + 1'p_2_1= 0
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + 1'p_7_0= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + -1'r_7_2 + 1'r_8_2 + 1'p_9_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + 1'p_13_1= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + 1'p_8_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + 1'p_3_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + 1'p_1_0= 1
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + -1'r_4_0 + 1'r_5_0 + -1'r_6_0 + 1'r_7_0 + 1'p_8_0= 0
invariant : 1'p_0_2 + 1'r_0_2 + 1'p_1_2= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + -1'r_4_2 + 1'r_5_2 + -1'r_6_2 + 1'r_7_2 + -1'r_8_2 + 1'r_9_2 + -1'r_10_2 + 1'r_11_2 + 1'p_12_2= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + 1'p_5_1= 1
invariant : 1'p_0_0 + 1'r_0_0 + -1'r_1_0 + 1'r_2_0 + -1'r_3_0 + 1'r_4_0 + -1'r_5_0 + 1'r_6_0 + -1'r_7_0 + 1'r_8_0 + -1'r_9_0 + 1'r_10_0 + -1'r_11_0 + 1'r_12_0 + -1'r_13_0 + 1'r_14_0= 1
invariant : -1'p_0_1 + -1'r_0_1 + 1'r_1_1 + -1'r_2_1 + 1'r_3_1 + -1'r_4_1 + 1'r_5_1 + -1'r_6_1 + 1'r_7_1 + -1'r_8_1 + 1'r_9_1 + -1'r_10_1 + 1'r_11_1 + 1'p_12_1= 0
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + -1'r_9_1 + 1'r_10_1 + -1'r_11_1 + 1'r_12_1 + -1'r_13_1 + 1'r_14_1= 1
invariant : 1'p_0_2 + 1'r_0_2 + -1'r_1_2 + 1'r_2_2 + -1'r_3_2 + 1'r_4_2 + -1'r_5_2 + 1'r_6_2 + 1'p_7_2= 1
invariant : 1'p_0_1 + 1'r_0_1 + -1'r_1_1 + 1'r_2_1 + -1'r_3_1 + 1'r_4_1 + -1'r_5_1 + 1'r_6_1 + -1'r_7_1 + 1'r_8_1 + 1'p_9_1= 1
invariant : -1'p_0_2 + -1'r_0_2 + 1'r_1_2 + -1'r_2_2 + 1'r_3_2 + 1'p_4_2= 0
invariant : -1'p_0_0 + -1'r_0_0 + 1'r_1_0 + -1'r_2_0 + 1'r_3_0 + 1'p_4_0= 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation\_PT\_R003C015\_flat\_flat,5.78878e+08,0.527966,22900,2,6564,5,76517,6,0,423,106011,0
Total reachable state count : 578878464

Verifying 16 reachability properties.
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-0 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-0 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-0

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-0,0,0.534124,23056,1,0,5,76517,7,0,432,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-1 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-1 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-1

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-1,0,0.539019,23124,1,0,5,76517,8,0,442,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-2 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-2 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-2

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-2,0,0.542495,23124,1,0,5,76517,9,0,443,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-3 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-3 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-3,2.90304e+06,0.544434,23124,2,1188,6,76517,10,0,456,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-4 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-4 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-4,0,0.551584,23124,1,0,6,76517,11,0,461,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-5 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-5 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-5,96,0.553842,23128,2,126,7,76517,12,0,473,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-6 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-6 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-6

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-6,0,0.557598,23128,1,0,7,76517,13,0,483,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-7 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-7 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-7,0,0.559063,23128,1,0,7,76517,14,0,484,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-8 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-8 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-8,0,0.562538,23128,1,0,7,76517,15,0,485,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-9 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-9 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-9,8,0.563059,23128,2,96,8,76517,16,0,494,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-10 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-10

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-10,0,0.574955,23128,1,0,8,76517,17,0,501,106011,0
Reachability property ResAllocation-PT-R003C015-ReachabilityCardinality-11 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING
No reachable states exhibit your property : ResAllocation-PT-R003C015-ReachabilityCardinality-11

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-11,0,0.580283,23128,1,0,8,76517,18,0,508,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-12 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-12 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-12,96,0.582129,23128,2,124,9,76517,19,0,513,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-13 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-13,0,0.587454,23128,1,0,9,76517,20,0,523,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-14 is true.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-14,0,0.588675,23128,1,0,9,76517,21,0,543,106011,0
Invariant property ResAllocation-PT-R003C015-ReachabilityCardinality-15 does not hold.
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
ResAllocation-PT-R003C015-ReachabilityCardinality-15,512,0.589243,23128,2,127,10,76517,22,0,558,106011,0
FORMULA ResAllocation-PT-R003C015-ReachabilityCardinality-0 FALSE TECHNIQUES SAT_SMT K_INDUCTION(0)
Exit code :0

BK_STOP 1496651946933

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityCardinality -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 05, 2017 8:39:04 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 71 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 90 places.
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 60 transitions.
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 77 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 19 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 12 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 14 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 0 / 16 in 261 ms.
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-0(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-1(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-2(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-3(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-4(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-5(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-6(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-7(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-8(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-9(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-10(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-11(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-12(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-13(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-14(UNSAT) depth K=0 took 0 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-15(UNSAT) depth K=0 took 1 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 45 place invariants in 45 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-0(UNSAT) depth K=1 took 21 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-1(UNSAT) depth K=1 took 22 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-2(UNSAT) depth K=1 took 22 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 45 place invariants in 9 ms
Jun 05, 2017 8:39:05 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-3(UNSAT) depth K=1 took 41 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-4(UNSAT) depth K=1 took 40 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-5(UNSAT) depth K=1 took 40 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-6(UNSAT) depth K=1 took 38 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-7(UNSAT) depth K=1 took 21 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-8(UNSAT) depth K=1 took 21 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-9(UNSAT) depth K=1 took 23 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-10(UNSAT) depth K=1 took 23 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-11(UNSAT) depth K=1 took 22 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 90 variables to be positive in 394 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 60 transitions.
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/60 took 1 ms. Total solver calls (SAT/UNSAT): 2(1/1)
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 90 variables to be positive in 312 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-12(UNSAT) depth K=1 took 29 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-13(UNSAT) depth K=1 took 22 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-14(UNSAT) depth K=1 took 21 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-15(UNSAT) depth K=1 took 44 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 134 ms. Total solver calls (SAT/UNSAT): 318(144/174)
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 60 transitions.
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 135 ms. Total solver calls (SAT/UNSAT): 318(118/200)
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 60 transitions.
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, proved UNreachability of reachability predicate ResAllocation-PT-R003C015-ReachabilityCardinality-0
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: Induction result is UNSAT, successfully proved induction at step 0 for ResAllocation-PT-R003C015-ReachabilityCardinality-0
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runKInduction
INFO: KInduction solution for property ResAllocation-PT-R003C015-ReachabilityCardinality-0(FALSE) depth K=0 took 279 ms
Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness], workingDir=/home/mcc/execution]
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-0 with value :(((p_4_0>=2)&&(!(p_11_0<=r_14_0)))&&(p_3_2>=1))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-1 with value :((((p_10_0<=p_6_2)&&(p_9_1<=p_1_0))&&((p_11_1<=p_4_0)&&(p_12_1>=3)))&&(((p_6_2<=r_4_2)||(r_3_0<=p_12_0))&&((r_4_2>=3)&&(r_5_0>=2))))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-2 with value :(r_13_0>=3)
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-3 with value :(!((r_5_2<=r_10_2)||(p_0_2<=r_4_1)))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-4 with value :(r_13_0<=r_14_0)
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-5 with value :(((!(p_9_0<=p_5_0))&&(!(r_3_1>=3)))||(p_9_0<=p_13_0))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-6 with value :(((r_10_2>=2)||(r_5_0>=3))&&(((r_9_2>=2)&&(p_0_2<=p_5_1))||(!(p_7_0>=1))))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-7 with value :(!(r_6_1>=2))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-8 with value :(!(r_11_0>=3))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-9 with value :(!(((p_2_0>=3)||(p_0_2<=p_13_2))||(r_11_1>=1)))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-10 with value :((p_12_0>=3)&&(r_8_2<=r_14_1))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-11 with value :((!(r_5_0<=p_5_1))&&(r_13_0>=3))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-12 with value :(!((!(r_5_0>=2))&&((p_5_0>=1)&&(p_0_1>=1))))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-13 with value :(!((p_5_1>=3)&&((r_13_0>=2)||(p_2_2<=p_8_0))))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-14 with value :((!((r_3_0<=r_11_0)&&(r_10_2>=2)))||(((r_7_1>=3)||(r_4_2<=r_9_2))&&((p_4_2>=1)&&(r_0_2<=p_0_0))))
Read property : ResAllocation-PT-R003C015-ReachabilityCardinality-15 with value :((((p_3_2>=3)&&(r_11_2>=1))||(p_12_2<=p_2_2))||(p_6_0<=p_1_1))

Jun 05, 2017 8:39:06 AM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_ResAllocation-PT-R003C015"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_ResAllocation-PT-R003C015.tgz
mv S_ResAllocation-PT-R003C015 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_ResAllocation-PT-R003C015, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r150-csrt-149443434700088"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;