Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.........
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is S_PermAdmissibility-PT-01, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r120-blw7-149441652100404
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1496471796704


Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-ctl command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 592 rows 168 cols
invariant : -1'aux8_7 + 1'c12 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + 2'c11 + 2'c110 + 2'c9= 0
invariant : 2'c20 + 2'out7_1 + 2'out7_0 + 2'out7_3 + 2'out7_2 + 2'out7_5 + 2'out7_4 + 2'out7_7 + 2'out7_6 + 2'c19 + 1'aux13_2 + 1'aux13_1 + 1'aux13_0 + 1'aux13_7 + 1'c18 + 1'aux13_3 + 1'aux13_4 + 1'aux13_5 + 1'aux13_6 + 1'aux6_0 + 1'c12 + 1'aux6_5 + 1'aux6_1 + 1'aux6_4 + 2'c13 + 1'in3_5 + 1'in3_4 + 1'c6= 2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out3_0 + 1'out3_1 + 1'out3_6 + 1'out3_7 + 1'out3_2 + 1'out3_3 + 1'out3_4 + 1'out3_5= 0
invariant : -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out8_1 + 1'out8_0 + 1'out8_3 + 1'out8_2 + 1'out8_6 + 1'out8_7 + 1'out8_4 + 1'out8_5= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + 2'c14= 0
invariant : -2'c20 + -2'out7_1 + -2'out7_0 + -2'out7_3 + -2'out7_2 + -2'out7_5 + -2'out7_4 + -2'out7_7 + -2'out7_6 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux6_0 + -1'c12 + -1'aux6_5 + -1'aux6_1 + -1'aux6_4 + -2'c13 + -2'in3_5 + -2'in3_4 + 2'c5= -2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out4_0 + 1'out4_1 + 1'out4_7 + 1'out4_6 + 1'out4_3 + 1'out4_2 + 1'out4_5 + 1'out4_4= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_4 + 1'aux16_5 + -1'c20 + -1'out7_3 + -1'out7_2 + -1'out7_7 + -1'out7_6 + 1'out5_1 + -1'c19 + 1'out5_0 + 1'out5_5 + 1'out5_4 + 1'aux15_1 + 1'aux15_0 + 1'aux15_5 + 1'aux15_4 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -1'out3_7 + -1'out3_2 + -1'out3_3 + 1'out1_0 + 1'out1_5 + 1'out1_1 + 1'out1_4 + -1'c12 + 1'aux12_5 + 1'aux12_4 + 1'aux12_1 + 1'aux12_0 + -2'c13 + -1'c11 + 1'aux10_0 + 1'aux10_1 + 1'aux10_4 + 1'aux10_5= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + -1'aux15_2 + -1'aux15_1 + -1'aux15_0 + -1'aux15_6 + -1'aux15_5 + -1'aux15_4 + -1'aux15_3 + -1'aux15_7 + -1'c18 + 2'c16= 0
invariant : -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_6 + -1'aux14_5 + 1'c20 + -1'aux14_7 + 2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'c15= 0
invariant : 1'aux8_7 + -1'c12 + 1'aux8_3 + 1'aux8_6 + 1'aux8_2 + -2'c11 + -1'aux7_7 + -1'aux7_6 + -1'c110 + -1'aux7_3 + -1'aux7_2 + 2'c8= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out5_1 + 1'out5_2 + 1'out5_0 + 1'out5_5 + 1'out5_6 + 1'out5_3 + 1'out5_4 + 1'out5_7= 0
invariant : -1'aux16_0 + -1'aux16_1 + 1'aux16_2 + 1'aux16_3 + -1'aux16_4 + -1'aux16_5 + 1'aux16_6 + 1'aux16_7 + 1'c20 + 2'out7_3 + 2'out7_2 + 2'out7_7 + 2'out7_6 + -2'out5_1 + -2'out5_0 + -2'out5_5 + -2'out5_4 + 1'aux15_2 + -1'aux15_1 + -1'aux15_0 + 1'aux15_6 + -1'aux15_5 + -1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'out3_6 + 2'out3_7 + 2'out3_2 + 2'out3_3 + -2'out1_0 + -2'out1_5 + -2'out1_1 + -2'out1_4 + -2'c12 + -2'aux12_5 + -2'aux12_4 + -2'aux12_1 + -2'aux12_0 + -2'c11 + 2'aux10_2 + 2'aux10_3 + 2'aux10_6 + 2'aux10_7= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + -2'aux13_2 + -2'aux13_1 + -2'aux13_0 + 1'aux15_7 + -2'aux13_7 + -1'c18 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + 2'aux12_6 + 2'aux12_5 + 2'aux12_4 + 2'aux12_3 + 2'aux12_2 + 2'aux12_1 + 2'aux12_0 + -4'c13 + 2'aux12_7= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out6_1 + 1'out6_2 + 1'out6_0 + 1'out6_6 + 1'out6_5 + 1'out6_4 + 1'out6_3 + 1'out6_7= 0
invariant : -1'in3_5 + -1'in3_4 + 1'in1_1 + 1'in1_0= 0
invariant : -1'aux16_0 + -1'aux16_1 + -1'aux16_2 + -1'aux16_3 + -1'aux16_4 + -1'aux16_5 + -1'aux16_6 + -1'aux16_7 + 1'c20 + 2'c19 + 2'c18 + 2'c17= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out2_0 + 1'out2_7 + 1'out2_5 + 1'out2_6 + 1'out2_3 + 1'out2_4 + 1'out2_1 + 1'out2_2= 0
invariant : = 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out1_0 + 1'out1_6 + 1'out1_5 + 1'out1_7 + 1'out1_2 + 1'out1_1 + 1'out1_4 + 1'out1_3= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -4'c12 + -4'c13 + 2'aux11_5 + 2'aux11_4 + 2'aux11_3 + 2'aux11_2 + 2'aux11_1 + 2'aux11_0 + 2'aux11_7 + 2'aux11_6= 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,52537,9.61942,232432,2,49937,5,147174,6,0,1098,59698,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,18688,68.0609,1598396,2,15392,1157,3.65527e+06,1135,526,18428,963347,1126

System contains 18688 deadlocks (shown below if less than --print-limit option) !
FORMULA PermAdmissibility-COL-01-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Exit code :0
[ 18688 states ]

BK_STOP 1496471867734

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityDeadlock = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 113 ms
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 592 transitions.
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.logic.togal.ToGalTransformer toGal
WARNING: Unknown predicate type in boolean expression fr.lip6.move.gal.logic.impl.DeadlockImpl
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property PermAdmissibility-COL-01-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
Jun 03, 2017 6:36:38 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 186 ms
Jun 03, 2017 6:36:38 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 28 ms
Jun 03, 2017 6:36:39 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 21 place invariants in 185 ms
Jun 03, 2017 6:36:47 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 168 variables to be positive in 8614 ms
Jun 03, 2017 6:36:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 592 transitions.
Jun 03, 2017 6:36:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/592 took 48 ms. Total solver calls (SAT/UNSAT): 136(8/128)
Jun 03, 2017 6:36:48 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :21/592 took 1091 ms. Total solver calls (SAT/UNSAT): 2992(176/2816)
Jun 03, 2017 6:36:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :43/592 took 2131 ms. Total solver calls (SAT/UNSAT): 5984(352/5632)
Jun 03, 2017 6:36:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :60/592 took 3224 ms. Total solver calls (SAT/UNSAT): 8326(600/7726)
Jun 03, 2017 6:36:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :66/592 took 4325 ms. Total solver calls (SAT/UNSAT): 9232(984/8248)
Jun 03, 2017 6:36:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :72/592 took 5429 ms. Total solver calls (SAT/UNSAT): 10138(1368/8770)
Jun 03, 2017 6:36:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :78/592 took 6667 ms. Total solver calls (SAT/UNSAT): 11044(1752/9292)
Jun 03, 2017 6:36:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :84/592 took 7829 ms. Total solver calls (SAT/UNSAT): 11950(2136/9814)
Jun 03, 2017 6:36:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :90/592 took 8925 ms. Total solver calls (SAT/UNSAT): 12856(2520/10336)
Jun 03, 2017 6:36:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :96/592 took 10023 ms. Total solver calls (SAT/UNSAT): 13762(2904/10858)
Jun 03, 2017 6:36:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :102/592 took 11096 ms. Total solver calls (SAT/UNSAT): 14653(3232/11421)
Jun 03, 2017 6:37:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :111/592 took 12270 ms. Total solver calls (SAT/UNSAT): 15952(3584/12368)
Jun 03, 2017 6:37:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :117/592 took 13431 ms. Total solver calls (SAT/UNSAT): 16858(3968/12890)
Jun 03, 2017 6:37:02 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :123/592 took 14455 ms. Total solver calls (SAT/UNSAT): 17749(4296/13453)
Jun 03, 2017 6:37:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :147/592 took 15495 ms. Total solver calls (SAT/UNSAT): 21013(4488/16525)
Jun 03, 2017 6:37:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :157/592 took 16722 ms. Total solver calls (SAT/UNSAT): 22418(4736/17682)
Jun 03, 2017 6:37:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :169/592 took 17763 ms. Total solver calls (SAT/UNSAT): 24080(4944/19136)
Jun 03, 2017 6:37:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :188/592 took 18854 ms. Total solver calls (SAT/UNSAT): 26598(5208/21390)
Jun 03, 2017 6:37:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :194/592 took 19870 ms. Total solver calls (SAT/UNSAT): 27216(5592/21624)
Jun 03, 2017 6:37:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :201/592 took 21033 ms. Total solver calls (SAT/UNSAT): 27937(6040/21897)
Jun 03, 2017 6:37:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :207/592 took 22054 ms. Total solver calls (SAT/UNSAT): 28555(6424/22131)
Jun 03, 2017 6:37:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :214/592 took 23213 ms. Total solver calls (SAT/UNSAT): 29276(6872/22404)
Jun 03, 2017 6:37:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :221/592 took 24364 ms. Total solver calls (SAT/UNSAT): 29997(7320/22677)
Jun 03, 2017 6:37:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :231/592 took 25391 ms. Total solver calls (SAT/UNSAT): 31192(7680/23512)
Jun 03, 2017 6:37:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :238/592 took 26526 ms. Total solver calls (SAT/UNSAT): 31913(8128/23785)
Jun 03, 2017 6:37:15 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :245/592 took 27683 ms. Total solver calls (SAT/UNSAT): 32634(8576/24058)
Jun 03, 2017 6:37:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :253/592 took 28713 ms. Total solver calls (SAT/UNSAT): 33242(8965/24277)
Jun 03, 2017 6:37:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :279/592 took 29788 ms. Total solver calls (SAT/UNSAT): 33832(9353/24479)
Jun 03, 2017 6:37:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :290/592 took 30822 ms. Total solver calls (SAT/UNSAT): 34485(9705/24780)
Jun 03, 2017 6:37:19 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :304/592 took 31865 ms. Total solver calls (SAT/UNSAT): 35010(10018/24992)
Jun 03, 2017 6:37:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :317/592 took 32999 ms. Total solver calls (SAT/UNSAT): 35864(10440/25424)
Jun 03, 2017 6:37:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :327/592 took 34009 ms. Total solver calls (SAT/UNSAT): 37046(10856/26190)
Jun 03, 2017 6:37:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :347/592 took 35150 ms. Total solver calls (SAT/UNSAT): 38212(11244/26968)
Jun 03, 2017 6:37:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :354/592 took 36238 ms. Total solver calls (SAT/UNSAT): 39423(11692/27731)
Jun 03, 2017 6:37:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :361/592 took 37307 ms. Total solver calls (SAT/UNSAT): 40634(12140/28494)
Jun 03, 2017 6:37:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :368/592 took 38387 ms. Total solver calls (SAT/UNSAT): 41845(12588/29257)
Jun 03, 2017 6:37:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :375/592 took 39426 ms. Total solver calls (SAT/UNSAT): 43056(13036/30020)
Jun 03, 2017 6:37:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :385/592 took 40556 ms. Total solver calls (SAT/UNSAT): 44741(13487/31254)
Jun 03, 2017 6:37:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :399/592 took 41649 ms. Total solver calls (SAT/UNSAT): 47043(13879/33164)
Jun 03, 2017 6:37:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :406/592 took 42751 ms. Total solver calls (SAT/UNSAT): 48254(14327/33927)
Jun 03, 2017 6:37:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :426/592 took 43755 ms. Total solver calls (SAT/UNSAT): 51474(14599/36875)
Jun 03, 2017 6:37:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :451/592 took 44879 ms. Total solver calls (SAT/UNSAT): 55484(14876/40608)
Jun 03, 2017 6:37:33 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :458/592 took 45994 ms. Total solver calls (SAT/UNSAT): 56695(15324/41371)
Jun 03, 2017 6:37:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :478/592 took 47004 ms. Total solver calls (SAT/UNSAT): 59915(15596/44319)
Jun 03, 2017 6:37:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :485/592 took 48118 ms. Total solver calls (SAT/UNSAT): 61126(16044/45082)
Jun 03, 2017 6:37:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :492/592 took 49235 ms. Total solver calls (SAT/UNSAT): 62337(16492/45845)
Jun 03, 2017 6:37:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :499/592 took 50355 ms. Total solver calls (SAT/UNSAT): 63548(16940/46608)
Jun 03, 2017 6:37:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :506/592 took 51474 ms. Total solver calls (SAT/UNSAT): 64759(17388/47371)
Jun 03, 2017 6:37:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :513/592 took 52581 ms. Total solver calls (SAT/UNSAT): 65970(17836/48134)
Jun 03, 2017 6:37:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :520/592 took 53675 ms. Total solver calls (SAT/UNSAT): 67181(18284/48897)
Jun 03, 2017 6:37:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :536/592 took 54715 ms. Total solver calls (SAT/UNSAT): 69784(18615/51169)
Jun 03, 2017 6:37:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :568/592 took 55716 ms. Total solver calls (SAT/UNSAT): 74870(18773/56097)
Jun 03, 2017 6:37:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 56236 ms. Total solver calls (SAT/UNSAT): 78504(18796/59708)
Jun 03, 2017 6:37:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 592 transitions.
Jun 03, 2017 6:37:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :3/592 took 1064 ms. Total solver calls (SAT/UNSAT): 544(272/272)
Jun 03, 2017 6:37:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :7/592 took 2103 ms. Total solver calls (SAT/UNSAT): 1088(544/544)
Jun 03, 2017 6:37:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :11/592 took 3164 ms. Total solver calls (SAT/UNSAT): 1632(816/816)
Jun 03, 2017 6:37:47 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions switch9_2_0, switch9_3_0, switch9_4_0, switch9_3_5, switch9_1_5, switch9_2_5, switch9_7_4, switch9_0_5, switch9_6_4, switch9_3_6, switch9_4_6, switch9_1_6, switch9_2_6, switch9_7_5, switch9_0_6, switch9_6_5, switch9_4_7, switch9_3_7, switch9_2_7, switch9_1_7, switch9_0_7, switch9_5_6, switch10_4_0, switch10_3_0, switch10_2_0, switch9_5_7, switch9_2_1, switch9_3_1, switch9_4_1, switch9_5_0, switch9_6_0, switch9_7_0, switch9_1_2, switch9_4_2, switch9_5_1, switch9_6_1, switch9_7_1, switch9_0_2, switch9_1_3, switch9_4_3, switch9_6_2, switch9_5_2, switch9_0_3, switch9_7_2, switch9_2_4, switch9_1_4, switch9_3_4, switch9_6_3, switch9_5_3, switch9_0_4, switch9_7_3, switch10_7_4, switch10_0_5, switch10_6_4, switch10_3_5, switch10_1_5, switch10_2_5, switch10_7_5, switch10_0_6, switch10_6_5, switch10_3_6, switch10_4_6, switch10_1_6, switch10_2_6, switch10_0_7, switch10_5_6, switch10_4_7, switch10_3_7, switch10_2_7, switch10_1_7, switch10_5_7, switch11_4_0, switch11_3_0, switch11_2_0, switch10_5_0, switch10_6_0, switch10_7_0, switch10_2_1, switch10_3_1, switch10_4_1, switch10_5_1, switch10_6_1, switch10_7_1, switch10_0_2, switch10_1_2, switch10_4_2, switch10_6_2, switch10_5_2, switch10_0_3, switch10_7_2, switch10_1_3, switch10_4_3, switch10_6_3, switch10_5_3, switch10_0_4, switch10_7_3, switch10_2_4, switch10_1_4, switch10_3_4, switch11_4_6, switch11_3_6, switch11_2_6, switch11_1_6, switch11_0_6, switch11_7_5, switch11_6_5, switch11_3_5, switch11_2_5, switch11_1_5, switch11_0_5, switch11_7_4, switch11_6_4, switch11_5_7, switch11_3_7, switch11_4_7, switch11_1_7, switch11_2_7, switch11_0_7, switch11_5_6, switch11_1_2, switch11_4_2, switch11_6_1, switch11_5_1, switch11_0_2, switch11_7_1, switch11_2_1, switch11_4_1, switch11_3_1, switch11_6_0, switch11_5_0, switch11_7_0, switch11_1_4, switch11_2_4, switch11_3_4, switch11_5_3, switch11_6_3, switch11_7_3, switch11_0_4, switch11_1_3, switch11_4_3, switch11_5_2, switch11_6_2, switch11_7_2, switch11_0_3, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :64/384/144/592

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_PermAdmissibility-PT-01"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_PermAdmissibility-PT-01.tgz
mv S_PermAdmissibility-PT-01 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is S_PermAdmissibility-PT-01, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r120-blw7-149441652100404"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;