fond
Model Checking Contest @ Petri Nets 2017
7th edition, Zaragoza, Spain, June 27, 2017
Execution of r048-smll-149440869500061
Last Updated
June 27, 2017

About the Execution of LoLA for Peterson-PT-4

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
14666.120 1769903.00 3541546.00 4448.40 TTFFTF?TTFTTFFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...........
=====================================================================
Generated by BenchKit 2-3254
Executing tool lola
Input is Peterson-PT-4, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r048-smll-149440869500061
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-0
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-1
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-10
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-11
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-12
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-13
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-14
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-15
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-2
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-3
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-4
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-5
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-6
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-7
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-8
FORMULA_NAME Peterson-COL-4-ReachabilityCardinality-9

=== Now, execution of the tool begins

BK_START 1494502233683


Time: 3600 - MCC
----- Start make prepare stdout -----
checking for too many tokens
----- Start make result stdout -----
ReachabilityCardinality @ Peterson-PT-4 @ 3540 seconds
----- Start make result stdout -----
lola: LoLA will run for 3540 seconds at most (--timelimit)
lola: NET
lola: reading net from model.pnml.lola
lola: finished parsing
lola: closed net file model.pnml.lola
lola: 1170/65536 symbol table entries, 0 collisions
lola: preprocessing...
lola: finding significant places
lola: 480 places, 690 transitions, 461 significant places
lola: computing forward-conflicting sets
lola: computing back-conflicting sets
lola: 1055 transition conflict sets
lola: TASK
lola: reading formula from Peterson-COL-4-ReachabilityCardinality.task
lola: A (G (TRUE)) : E (F (((2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3) AND (1 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) AND (TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 <= 0) AND ((Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4 <= 2) OR (BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0 <= 2))))) : A (G (((2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3)))) : A (G ((CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4))) : A (G (((AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR ((1 <= WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F) AND (Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4)) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2)))) : A (G (TRUE)) : A (G (((EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3 <= 1) OR (WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 0) OR (TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4)))) : E (F (((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 0) AND ((2 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4) OR (IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3)) AND ((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) OR (2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3) OR (TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4))))) : E (F ((((2 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) OR ((3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3) AND (AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4))) AND (Idle_0 + Idle_1 + Idle_2 + Idle_3 + Idle_4 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4)))) : E (F (((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + 1 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4) AND (WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4)))) : E (F (())) : A (G ((((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= 2) OR (IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4 <= 1)) AND ((TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4) OR (TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + TestIdentity_1_2_2 + TestIdentity_1_2_3 + TestIdentity_1_2_4 + TestIdentity_4_1_0 + TestIdentity_4_1_1 + TestIdentity_4_1_2 + TestIdentity_4_1_3 + TestIdentity_4_1_4 + TestIdentity_1_3_0 + TestIdentity_1_3_1 + TestIdentity_1_3_2 + TestIdentity_1_3_3 + TestIdentity_1_3_4 + TestIdentity_4_2_0 + TestIdentity_4_2_1 + TestIdentity_4_2_2 + TestIdentity_4_2_3 + TestIdentity_4_2_4 + TestIdentity_4_3_0 + TestIdentity_4_3_1 + TestIdentity_4_3_2 + TestIdentity_4_3_3 + TestIdentity_4_3_4 + TestIdentity_2_0_0 + TestIdentity_2_0_1 + TestIdentity_2_0_2 + TestIdentity_2_0_3 + TestIdentity_2_0_4 + TestIdentity_2_1_0 + TestIdentity_2_1_1 + TestIdentity_2_1_2 + TestIdentity_2_1_3 + TestIdentity_2_1_4 + TestIdentity_2_2_0 + TestIdentity_2_2_1 + TestIdentity_2_2_2 + TestIdentity_2_2_3 + TestIdentity_2_2_4 + TestIdentity_2_3_0 + TestIdentity_2_3_1 + TestIdentity_2_3_2 + TestIdentity_2_3_3 + TestIdentity_2_3_4 + TestIdentity_0_0_0 + TestIdentity_0_0_1 + TestIdentity_0_0_2 + TestIdentity_0_0_3 + TestIdentity_0_0_4 + TestIdentity_0_1_0 + TestIdentity_0_1_1 + TestIdentity_0_1_2 + TestIdentity_0_1_3 + TestIdentity_0_1_4 + TestIdentity_3_0_0 + TestIdentity_3_0_1 + TestIdentity_3_0_2 + TestIdentity_3_0_3 + TestIdentity_3_0_4 + TestIdentity_0_2_0 + TestIdentity_0_2_1 + TestIdentity_0_2_2 + TestIdentity_0_2_3 + TestIdentity_0_2_4 + TestIdentity_3_1_0 + TestIdentity_3_1_1 + TestIdentity_3_1_2 + TestIdentity_3_1_3 + TestIdentity_3_1_4 + TestIdentity_0_3_0 + TestIdentity_0_3_1 + TestIdentity_0_3_2 + TestIdentity_0_3_3 + TestIdentity_0_3_4 + TestIdentity_3_2_0 + TestIdentity_3_2_1 + TestIdentity_3_2_2 + TestIdentity_3_2_3 + TestIdentity_3_2_4 + TestIdentity_3_3_0 + TestIdentity_3_3_1 + TestIdentity_3_3_2 + TestIdentity_3_3_3 + TestIdentity_3_3_4 <= BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0) OR ((AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F) AND (3 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3)))))) : E (F (((BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0 + 1 <= AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2) AND (AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 + 1 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) AND (2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3)))) : A (G ((((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_1 + BeginLoop_2_3_2 + BeginLoop_2_3_3 + BeginLoop_2_3_4 + BeginLoop_0_0_0 + BeginLoop_0_0_1 + BeginLoop_0_0_2 + BeginLoop_0_0_3 + BeginLoop_0_0_4 + BeginLoop_0_1_0 + BeginLoop_0_1_1 + BeginLoop_0_1_2 + BeginLoop_0_1_3 + BeginLoop_0_1_4 + BeginLoop_3_0_0 + BeginLoop_3_0_1 + BeginLoop_3_0_2 + BeginLoop_3_0_3 + BeginLoop_3_0_4 + BeginLoop_0_2_0 + BeginLoop_0_2_1 + BeginLoop_0_2_2 + BeginLoop_0_2_3 + BeginLoop_0_2_4 + BeginLoop_3_1_0 + BeginLoop_3_1_1 + BeginLoop_3_1_2 + BeginLoop_3_1_3 + BeginLoop_3_1_4 + BeginLoop_0_3_0 + BeginLoop_0_3_1 + BeginLoop_0_3_2 + BeginLoop_0_3_3 + BeginLoop_0_3_4 + BeginLoop_3_2_0 + BeginLoop_3_2_1 + BeginLoop_3_2_2 + BeginLoop_3_2_3 + BeginLoop_3_2_4 + BeginLoop_3_3_0 + BeginLoop_3_3_1 + BeginLoop_3_3_2 + BeginLoop_3_3_3 + BeginLoop_3_3_4 + BeginLoop_4_2_4 + BeginLoop_4_2_3 + BeginLoop_1_0_0 + BeginLoop_1_0_1 + BeginLoop_1_0_2 + BeginLoop_1_0_3 + BeginLoop_1_0_4 + BeginLoop_1_1_0 + BeginLoop_1_1_1 + BeginLoop_1_1_2 + BeginLoop_1_1_3 + BeginLoop_1_1_4 + BeginLoop_4_0_0 + BeginLoop_4_0_1 + BeginLoop_4_0_2 + BeginLoop_4_0_3 + BeginLoop_4_0_4 + BeginLoop_1_2_0 + BeginLoop_1_2_1 + BeginLoop_1_2_2 + BeginLoop_1_2_3 + BeginLoop_1_2_4 + BeginLoop_4_1_0 + BeginLoop_4_1_1 + BeginLoop_4_1_2 + BeginLoop_4_1_3 + BeginLoop_4_1_4 + BeginLoop_4_2_2 + BeginLoop_1_3_0 + BeginLoop_1_3_1 + BeginLoop_1_3_2 + BeginLoop_1_3_3 + BeginLoop_1_3_4 + BeginLoop_4_2_1 + BeginLoop_4_2_0) AND (2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3)) OR (TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3 + 1 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4)))) : E (F ((3 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4))) : E (F (((((1 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4) AND (3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlone_0_0_2 + TestAlone_0_0_3 + TestAlone_0_0_4 + TestAlone_0_1_1 + TestAlone_0_1_2 + TestAlone_0_1_3 + TestAlone_0_1_4 + TestAlone_3_0_0 + TestAlone_3_0_1 + TestAlone_3_0_2 + TestAlone_3_0_4 + TestAlone_4_2_2 + TestAlone_0_2_1 + TestAlone_0_2_2 + TestAlone_0_2_3 + TestAlone_0_2_4 + TestAlone_3_1_0 + TestAlone_3_1_1 + TestAlone_3_1_2 + TestAlone_3_1_4 + TestAlone_4_2_1 + TestAlone_4_2_0 + TestAlone_0_3_1 + TestAlone_0_3_2 + TestAlone_0_3_3 + TestAlone_0_3_4 + TestAlone_3_2_0 + TestAlone_3_2_1 + TestAlone_3_2_2 + TestAlone_3_2_4 + TestAlone_3_3_0 + TestAlone_3_3_1 + TestAlone_3_3_2 + TestAlone_3_3_4 + TestAlone_1_0_0 + TestAlone_1_0_2 + TestAlone_1_0_3 + TestAlone_1_0_4 + TestAlone_1_1_0 + TestAlone_1_1_2 + TestAlone_1_1_3 + TestAlone_1_1_4 + TestAlone_4_0_0 + TestAlone_4_0_1 + TestAlone_4_0_2 + TestAlone_4_0_3 + TestAlone_1_2_0 + TestAlone_1_2_2 + TestAlone_1_2_3 + TestAlone_1_2_4 + TestAlone_4_1_0 + TestAlone_4_1_1 + TestAlone_4_1_2 + TestAlone_4_1_3 + TestAlone_1_3_0 + TestAlone_1_3_2 + TestAlone_1_3_3 + TestAlone_1_3_4 + TestAlone_4_2_3)) OR (Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 + IsEndLoop_3_0_1 + IsEndLoop_3_0_2 + IsEndLoop_3_0_3 + IsEndLoop_3_0_4 + IsEndLoop_0_2_0 + IsEndLoop_0_2_1 + IsEndLoop_0_2_2 + IsEndLoop_0_2_3 + IsEndLoop_0_2_4 + IsEndLoop_3_1_0 + IsEndLoop_3_1_1 + IsEndLoop_3_1_2 + IsEndLoop_3_1_3 + IsEndLoop_3_1_4 + IsEndLoop_0_3_0 + IsEndLoop_0_3_1 + IsEndLoop_0_3_2 + IsEndLoop_0_3_3 + IsEndLoop_0_3_4 + IsEndLoop_3_2_0 + IsEndLoop_3_2_1 + IsEndLoop_3_2_2 + IsEndLoop_3_2_3 + IsEndLoop_3_2_4 + IsEndLoop_3_3_0 + IsEndLoop_3_3_1 + IsEndLoop_3_3_2 + IsEndLoop_3_3_3 + IsEndLoop_3_3_4 + IsEndLoop_1_0_0 + IsEndLoop_1_0_1 + IsEndLoop_1_0_2 + IsEndLoop_1_0_3 + IsEndLoop_1_0_4 + IsEndLoop_1_1_0 + IsEndLoop_1_1_1 + IsEndLoop_1_1_2 + IsEndLoop_1_1_3 + IsEndLoop_1_1_4 + IsEndLoop_4_0_0 + IsEndLoop_4_0_1 + IsEndLoop_4_0_2 + IsEndLoop_4_0_3 + IsEndLoop_4_0_4 + IsEndLoop_1_2_0 + IsEndLoop_1_2_1 + IsEndLoop_1_2_2 + IsEndLoop_1_2_3 + IsEndLoop_1_2_4 + IsEndLoop_4_1_0 + IsEndLoop_4_1_1 + IsEndLoop_4_1_2 + IsEndLoop_4_1_3 + IsEndLoop_4_1_4 + IsEndLoop_1_3_0 + IsEndLoop_1_3_1 + IsEndLoop_1_3_2 + IsEndLoop_1_3_3 + IsEndLoop_1_3_4 + IsEndLoop_4_2_0 + IsEndLoop_4_2_1 + IsEndLoop_4_2_2 + IsEndLoop_4_2_3 + IsEndLoop_4_2_4 + IsEndLoop_4_3_0 + IsEndLoop_4_3_1 + IsEndLoop_4_3_2 + IsEndLoop_4_3_3 + IsEndLoop_4_3_4 + IsEndLoop_2_0_0 + IsEndLoop_2_0_1 + IsEndLoop_2_0_2 + IsEndLoop_2_0_3 + IsEndLoop_2_0_4 + IsEndLoop_2_1_0 + IsEndLoop_2_1_1 + IsEndLoop_2_1_2 + IsEndLoop_2_1_3 + IsEndLoop_2_1_4 + IsEndLoop_2_2_0 + IsEndLoop_2_2_1 + IsEndLoop_2_2_2 + IsEndLoop_2_2_3 + IsEndLoop_2_2_4 + IsEndLoop_2_3_0 + IsEndLoop_2_3_1 + IsEndLoop_2_3_2 + IsEndLoop_2_3_3 + IsEndLoop_2_3_4)) AND (AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSection_4_2 <= WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F))))
lola: computing a collection of formulas
lola: RUNNING
lola: subprocess 0 will run for 221 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (TRUE))
lola: ========================================
lola: SUBTASK
lola: checking initial satisfaction
lola: processed formula: TRUE
lola: processed formula length: 4
lola: 3 rewrites
lola: formula mentions 0 of 480 places; total mentions: 0
lola: closed formula file Peterson-COL-4-ReachabilityCardinality.task
lola: processed formula with 0 atomic propositions
lola: RUNNING
lola: SUBRESULT
lola: result: yes
lola: produced by: preprocessing
lola: The net satisfies the property already in its initial state.
lola: ========================================
lola: subprocess 1 will run for 236 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((2 <= EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3) AND (1 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlon... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 8 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality.sara
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 2 will run for 252 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (((2 <= Turn_2_0 + Turn_2_1 + Turn_2_2 + Turn_2_3 + Turn_3_0 + Turn_3_1 + Turn_3_2 + Turn_3_3 + Turn_1_3 + Turn_1_2 + Turn_1_1 + Turn_1_0 + Turn_0_0 + Turn_0_1 + Turn_0_2 + Turn_0_3 + Turn_0_4 + Turn_1_4 + Turn_3_4 + Turn_2_4) OR (CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + T... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 2 literals and 1 conjunctive subformulas
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is invariant.
lola: ========================================
lola: subprocess 3 will run for 272 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G ((CS_0 + CS_1 + CS_2 + CS_3 + CS_4 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + TestIdentity_1_0_4 + TestIdentity_1_1_0 + TestIdentity_1_1_1 + TestIdentity_1_1_2 + TestIdentity_1_1_3 + TestIdentity_1_1_4 + TestIdentity_4_0_0 + TestIdentity_4_0_1 + TestIdentity_4_0_2 + TestIdentity_4_0_3 + TestIdentity_4_0_4 + TestIdentity_1_2_0 + TestIdentity_1_2_1 + ... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 1 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-3.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-3.sara.
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 4 will run for 295 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (((AskForSection_0_0 + AskForSection_0_1 + AskForSection_0_2 + AskForSection_0_3 + AskForSection_1_0 + AskForSection_1_1 + AskForSection_1_2 + AskForSection_1_3 + AskForSection_2_0 + AskForSection_2_1 + AskForSection_2_2 + AskForSection_2_3 + AskForSection_3_0 + AskForSection_3_1 + AskForSection_3_2 + AskForSection_3_3 + AskForSection_4_3 + AskForSection_4_0 + AskForSection_4_1 + AskForSectio... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 8 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-4.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-4.sara.
sara: place or transition ordering is non-deterministic

lola: state equation: solution impossible
lola: SUBRESULT
lola: result: yes
lola: produced by: state equation
lola: The predicate is invariant.
lola: ========================================
lola: subprocess 5 will run for 321 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (TRUE))
lola: ========================================
lola: SUBTASK
lola: checking initial satisfaction
lola: processed formula: TRUE
lola: processed formula length: 4
lola: 3 rewrites
lola: formula mentions 0 of 480 places; total mentions: 0
lola: closed formula file Peterson-COL-4-ReachabilityCardinality.task
lola: processed formula with 0 atomic propositions
lola: RUNNING
lola: SUBRESULT
lola: result: yes
lola: produced by: preprocessing
lola: The net satisfies the property already in its initial state.
lola: ========================================
lola: subprocess 6 will run for 353 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G (((EndTurn_0_2 + EndTurn_1_0 + EndTurn_1_1 + EndTurn_1_2 + EndTurn_1_3 + EndTurn_0_1 + EndTurn_2_0 + EndTurn_2_1 + EndTurn_2_2 + EndTurn_2_3 + EndTurn_3_0 + EndTurn_3_1 + EndTurn_3_2 + EndTurn_3_3 + EndTurn_4_0 + EndTurn_4_1 + EndTurn_4_2 + EndTurn_4_3 + EndTurn_0_0 + EndTurn_0_3 <= 1) OR (WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 3 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-6.sara
lola: state equation: calling and running sara
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 7 will run for 393 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= 0) AND ((2 <= IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_0_0_4 + IsEndLoop_0_1_0 + IsEndLoop_0_1_1 + IsEndLoop_0_1_2 + IsEndLoop_0_1_3 + IsEndLoop_0_1_4 + IsEndLoop_3_0_0 +... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 18 literals and 6 conjunctive subformulas
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-7.sara
lola: The predicate is unreachable.
lola: ========================================
lola: subprocess 8 will run for 442 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F ((((2 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 + TestAlone_2_3_4 + TestAlone_0_0_1 + TestAlon... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 5 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-8.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-8.sara.
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 9 will run for 505 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 + 1 <= TestIdentity_1_0_0 + TestIdentity_1_0_1 + TestIdentity_1_0_2 + TestIdentity_1_0_3 + Tes... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 2 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-9.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-9.sara.
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 10 will run for 589 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (()))
lola: ========================================
lola: SUBTASK
lola: checking initial satisfaction
lola: processed formula: FALSE
lola: processed formula length: 5
lola: 3 rewrites
lola: formula mentions 0 of 480 places; total mentions: 0
lola: closed formula file Peterson-COL-4-ReachabilityCardinality.task
lola: processed formula with 0 atomic propositions
lola: RUNNING
lola: SUBRESULT
lola: result: no
lola: produced by: preprocessing
lola: The net violates the given property already in its initial state.
lola: ========================================
lola: subprocess 11 will run for 707 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G ((((TestTurn_0_0 + TestTurn_0_1 + TestTurn_0_2 + TestTurn_0_3 + TestTurn_1_0 + TestTurn_1_1 + TestTurn_1_2 + TestTurn_1_3 + TestTurn_2_0 + TestTurn_2_1 + TestTurn_2_2 + TestTurn_2_3 + TestTurn_3_0 + TestTurn_3_1 + TestTurn_3_2 + TestTurn_3_3 + TestTurn_4_0 + TestTurn_4_1 + TestTurn_4_2 + TestTurn_4_3 <= 2) OR (IsEndLoop_0_0_0 + IsEndLoop_0_0_1 + IsEndLoop_0_0_2 + IsEndLoop_0_0_3 + IsEndLoop_... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 8 literals and 3 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-11.sara
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 12 will run for 884 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_1_1 + BeginLoop_2_1_2 + BeginLoop_2_1_3 + BeginLoop_2_1_4 + BeginLoop_2_2_0 + BeginLoop_2_2_1 + BeginLoop_2_2_2 + BeginLoop_2_2_3 + BeginLoop_2_2_4 + BeginLoop_2_3_0 + BeginLoop_2_3_... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 3 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-12.sara
lola: state equation: calling and running sara
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: ========================================
lola: subprocess 13 will run for 1179 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: A (G ((((WantSection_4_T + WantSection_4_F + WantSection_3_T + WantSection_3_F + WantSection_2_T + WantSection_2_F + WantSection_1_T + WantSection_1_F + WantSection_0_T + WantSection_0_F <= BeginLoop_4_3_0 + BeginLoop_4_3_1 + BeginLoop_4_3_2 + BeginLoop_4_3_3 + BeginLoop_4_3_4 + BeginLoop_2_0_0 + BeginLoop_2_0_1 + BeginLoop_2_0_2 + BeginLoop_2_0_3 + BeginLoop_2_0_4 + BeginLoop_2_1_0 + BeginLoop_2_... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking invariance
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 6 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-13.sara
lola: SUBRESULT
lola: result: no
lola: produced by: state space
lola: The predicate is not invariant.
lola: ========================================
lola: subprocess 14 will run for 1769 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F ((3 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4)))
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 1 literals and 1 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-14.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-14.sara.
sara: place or transition ordering is non-deterministic
lola: sara is running 0 secs || 183930 markings, 660435 edges, 36786 markings/sec, 0 secs
lola: sara is running 5 secs || 353859 markings, 1335702 edges, 33986 markings/sec, 5 secs
lola: sara is running 10 secs || 524280 markings, 1980475 edges, 34084 markings/sec, 10 secs
sara: warning, failure of lp_solve (at job 1894)
lola: sara is running 15 secs || 695693 markings, 2625233 edges, 34283 markings/sec, 15 secs
lola: sara is running 20 secs || 862530 markings, 3286587 edges, 33367 markings/sec, 20 secs
lola: sara is running 25 secs || 1032309 markings, 3916232 edges, 33956 markings/sec, 25 secs
lola: sara is running 30 secs || 1198651 markings, 4575308 edges, 33268 markings/sec, 30 secs
lola: sara is running 35 secs || 1365265 markings, 5221387 edges, 33323 markings/sec, 35 secs
lola: sara is running 40 secs || 1533982 markings, 5848701 edges, 33743 markings/sec, 40 secs
lola: sara is running 45 secs || 1699156 markings, 6494294 edges, 33035 markings/sec, 45 secs
lola: sara is running 50 secs || 1862873 markings, 7135580 edges, 32743 markings/sec, 50 secs
lola: sara is running 55 secs || 2028205 markings, 7763979 edges, 33066 markings/sec, 55 secs
lola: sara is running 60 secs || 2190884 markings, 8404032 edges, 32536 markings/sec, 60 secs
lola: sara is running 65 secs || 2353772 markings, 9026765 edges, 32578 markings/sec, 65 secs
lola: sara is running 70 secs || 2516649 markings, 9678604 edges, 32575 markings/sec, 70 secs
lola: sara is running 75 secs || 2679197 markings, 10331419 edges, 32510 markings/sec, 75 secs
lola: sara is running 80 secs || 2843347 markings, 10952804 edges, 32830 markings/sec, 80 secs
lola: sara is running 85 secs || 3006782 markings, 11569300 edges, 32687 markings/sec, 85 secs
lola: sara is running 90 secs || 3169147 markings, 12187066 edges, 32473 markings/sec, 90 secs
lola: sara is running 95 secs || 3335620 markings, 12846356 edges, 33295 markings/sec, 95 secs
lola: sara is running 100 secs || 3504869 markings, 13535514 edges, 33850 markings/sec, 100 secs
lola: sara is running 105 secs || 3673284 markings, 14206361 edges, 33683 markings/sec, 105 secs
lola: sara is running 110 secs || 3843229 markings, 14898212 edges, 33989 markings/sec, 110 secs
lola: sara is running 115 secs || 4010908 markings, 15568079 edges, 33536 markings/sec, 115 secs
lola: sara is running 120 secs || 4177461 markings, 16250717 edges, 33311 markings/sec, 120 secs
lola: sara is running 125 secs || 4347429 markings, 16933367 edges, 33994 markings/sec, 125 secs
lola: sara is running 130 secs || 4514366 markings, 17581625 edges, 33387 markings/sec, 130 secs
lola: sara is running 135 secs || 4676490 markings, 18239132 edges, 32425 markings/sec, 135 secs
lola: sara is running 140 secs || 4842497 markings, 18874132 edges, 33201 markings/sec, 140 secs
lola: sara is running 145 secs || 5005277 markings, 19560600 edges, 32556 markings/sec, 145 secs
lola: sara is running 150 secs || 5170293 markings, 20238639 edges, 33003 markings/sec, 150 secs
lola: sara is running 155 secs || 5333665 markings, 20911686 edges, 32674 markings/sec, 155 secs
lola: sara is running 160 secs || 5496759 markings, 21550748 edges, 32619 markings/sec, 160 secs
lola: sara is running 165 secs || 5659186 markings, 22215484 edges, 32485 markings/sec, 165 secs
lola: sara is running 170 secs || 5816208 markings, 22889023 edges, 31404 markings/sec, 170 secs
lola: sara is running 175 secs || 5978477 markings, 23565697 edges, 32454 markings/sec, 175 secs
lola: sara is running 180 secs || 6144896 markings, 24222155 edges, 33284 markings/sec, 180 secs
lola: sara is running 185 secs || 6308092 markings, 24896440 edges, 32639 markings/sec, 185 secs
lola: sara is running 190 secs || 6484325 markings, 25530645 edges, 35247 markings/sec, 190 secs
lola: sara is running 195 secs || 6655229 markings, 26187361 edges, 34181 markings/sec, 195 secs
lola: sara is running 200 secs || 6820253 markings, 26832232 edges, 33005 markings/sec, 200 secs
lola: sara is running 205 secs || 6983985 markings, 27475498 edges, 32746 markings/sec, 205 secs
lola: sara is running 210 secs || 7151731 markings, 28142878 edges, 33549 markings/sec, 210 secs
lola: sara is running 215 secs || 7312977 markings, 28790631 edges, 32249 markings/sec, 215 secs
lola: sara is running 220 secs || 7476903 markings, 29428867 edges, 32785 markings/sec, 220 secs
lola: sara is running 225 secs || 7637356 markings, 30085243 edges, 32091 markings/sec, 225 secs
lola: sara is running 230 secs || 7798944 markings, 30732977 edges, 32318 markings/sec, 230 secs
lola: sara is running 235 secs || 7958048 markings, 31381302 edges, 31821 markings/sec, 235 secs
lola: sara is running 240 secs || 8112375 markings, 32016512 edges, 30865 markings/sec, 240 secs
lola: sara is running 245 secs || 8269206 markings, 32666897 edges, 31366 markings/sec, 245 secs
lola: sara is running 250 secs || 8429283 markings, 33299736 edges, 32015 markings/sec, 250 secs
lola: sara is running 255 secs || 8586022 markings, 33946380 edges, 31348 markings/sec, 255 secs
lola: sara is running 260 secs || 8738338 markings, 34585818 edges, 30463 markings/sec, 260 secs
lola: sara is running 265 secs || 8893393 markings, 35201516 edges, 31011 markings/sec, 265 secs
lola: sara is running 270 secs || 9050893 markings, 35848531 edges, 31500 markings/sec, 270 secs
lola: sara is running 275 secs || 9211214 markings, 36493930 edges, 32064 markings/sec, 275 secs
lola: sara is running 280 secs || 9371479 markings, 37116170 edges, 32053 markings/sec, 280 secs
lola: sara is running 285 secs || 9531271 markings, 37718418 edges, 31958 markings/sec, 285 secs
lola: sara is running 290 secs || 9688275 markings, 38329282 edges, 31401 markings/sec, 290 secs
lola: sara is running 295 secs || 9846168 markings, 38932664 edges, 31579 markings/sec, 295 secs
lola: sara is running 300 secs || 10007626 markings, 39576690 edges, 32292 markings/sec, 300 secs
lola: sara is running 305 secs || 10168788 markings, 40217079 edges, 32232 markings/sec, 305 secs
lola: sara is running 310 secs || 10328431 markings, 40863934 edges, 31929 markings/sec, 310 secs
lola: sara is running 315 secs || 10486311 markings, 41527613 edges, 31576 markings/sec, 315 secs
lola: sara is running 320 secs || 10635907 markings, 42186018 edges, 29919 markings/sec, 320 secs
lola: sara is running 325 secs || 10779730 markings, 42831580 edges, 28765 markings/sec, 325 secs
lola: sara is running 330 secs || 10931217 markings, 43450693 edges, 30297 markings/sec, 330 secs
lola: sara is running 335 secs || 11081064 markings, 44063254 edges, 29969 markings/sec, 335 secs
lola: sara is running 340 secs || 11224371 markings, 44676493 edges, 28661 markings/sec, 340 secs
lola: sara is running 345 secs || 11370252 markings, 45317551 edges, 29176 markings/sec, 345 secs
lola: sara is running 350 secs || 11522306 markings, 45929328 edges, 30411 markings/sec, 350 secs
lola: sara is running 355 secs || 11670554 markings, 46510038 edges, 29650 markings/sec, 355 secs
lola: sara is running 360 secs || 11817955 markings, 47086963 edges, 29480 markings/sec, 360 secs
lola: sara is running 365 secs || 11963819 markings, 47658369 edges, 29173 markings/sec, 365 secs
lola: sara is running 370 secs || 12107992 markings, 48265933 edges, 28835 markings/sec, 370 secs
lola: sara is running 375 secs || 12257572 markings, 48910020 edges, 29916 markings/sec, 375 secs
lola: sara is running 380 secs || 12411447 markings, 49514367 edges, 30775 markings/sec, 380 secs
lola: sara is running 385 secs || 12571041 markings, 50134361 edges, 31919 markings/sec, 385 secs
lola: sara is running 390 secs || 12732645 markings, 50742919 edges, 32321 markings/sec, 390 secs
lola: sara is running 395 secs || 12883633 markings, 51355995 edges, 30198 markings/sec, 395 secs
lola: sara is running 400 secs || 13037277 markings, 52004483 edges, 30729 markings/sec, 400 secs
lola: sara is running 405 secs || 13189149 markings, 52618357 edges, 30374 markings/sec, 405 secs
lola: sara is running 410 secs || 13338068 markings, 53251117 edges, 29784 markings/sec, 410 secs
lola: sara is running 415 secs || 13486189 markings, 53895276 edges, 29624 markings/sec, 415 secs
lola: sara is running 420 secs || 13630363 markings, 54542962 edges, 28835 markings/sec, 420 secs
lola: sara is running 425 secs || 13771199 markings, 55199056 edges, 28167 markings/sec, 425 secs
lola: sara is running 430 secs || 13920349 markings, 55823737 edges, 29830 markings/sec, 430 secs
lola: sara is running 435 secs || 14069364 markings, 56420785 edges, 29803 markings/sec, 435 secs
lola: sara is running 440 secs || 14217396 markings, 57016203 edges, 29606 markings/sec, 440 secs
lola: sara is running 445 secs || 14363587 markings, 57633001 edges, 29238 markings/sec, 445 secs
lola: sara is running 450 secs || 14518951 markings, 58228131 edges, 31073 markings/sec, 450 secs
lola: sara is running 455 secs || 14668253 markings, 58824088 edges, 29860 markings/sec, 455 secs
lola: sara is running 460 secs || 14819975 markings, 59415517 edges, 30344 markings/sec, 460 secs
lola: sara is running 465 secs || 14968038 markings, 60044799 edges, 29613 markings/sec, 465 secs
lola: sara is running 470 secs || 15113248 markings, 60709733 edges, 29042 markings/sec, 470 secs
lola: sara is running 475 secs || 15260063 markings, 61309133 edges, 29363 markings/sec, 475 secs
lola: sara is running 480 secs || 15410949 markings, 61924905 edges, 30177 markings/sec, 480 secs
lola: sara is running 485 secs || 15565370 markings, 62528623 edges, 30884 markings/sec, 485 secs
lola: sara is running 490 secs || 15713111 markings, 63135619 edges, 29548 markings/sec, 490 secs
lola: sara is running 495 secs || 15862048 markings, 63725497 edges, 29787 markings/sec, 495 secs
lola: sara is running 500 secs || 16012818 markings, 64312934 edges, 30154 markings/sec, 500 secs
lola: sara is running 505 secs || 16164377 markings, 64906279 edges, 30312 markings/sec, 505 secs
lola: sara is running 510 secs || 16315134 markings, 65520747 edges, 30151 markings/sec, 510 secs
lola: sara is running 515 secs || 16458732 markings, 66134084 edges, 28720 markings/sec, 515 secs
lola: sara is running 520 secs || 16601131 markings, 66764622 edges, 28480 markings/sec, 520 secs
lola: sara is running 525 secs || 16738969 markings, 67396982 edges, 27568 markings/sec, 525 secs
lola: sara is running 530 secs || 16887944 markings, 68010290 edges, 29795 markings/sec, 530 secs
lola: sara is running 535 secs || 17025733 markings, 68643035 edges, 27558 markings/sec, 535 secs
lola: sara is running 540 secs || 17171898 markings, 69229002 edges, 29233 markings/sec, 540 secs
lola: sara is running 545 secs || 17322334 markings, 69802366 edges, 30087 markings/sec, 545 secs
lola: sara is running 550 secs || 17468723 markings, 70384101 edges, 29278 markings/sec, 550 secs
lola: sara is running 555 secs || 17614031 markings, 70964643 edges, 29062 markings/sec, 555 secs
lola: sara is running 560 secs || 17755112 markings, 71553914 edges, 28216 markings/sec, 560 secs
lola: sara is running 565 secs || 17904108 markings, 72140797 edges, 29799 markings/sec, 565 secs
lola: sara is running 570 secs || 18054839 markings, 72724935 edges, 30146 markings/sec, 570 secs
lola: sara is running 575 secs || 18203891 markings, 73302050 edges, 29810 markings/sec, 575 secs
lola: sara is running 580 secs || 18343989 markings, 73917991 edges, 28020 markings/sec, 580 secs
lola: sara is running 585 secs || 18486475 markings, 74514299 edges, 28497 markings/sec, 585 secs
lola: sara is running 590 secs || 18636074 markings, 75091970 edges, 29920 markings/sec, 590 secs
lola: sara is running 595 secs || 18776227 markings, 75689341 edges, 28031 markings/sec, 595 secs
lola: sara is running 600 secs || 18925315 markings, 76277077 edges, 29818 markings/sec, 600 secs
lola: sara is running 605 secs || 19070749 markings, 76864586 edges, 29087 markings/sec, 605 secs
lola: sara is running 610 secs || 19217115 markings, 77455476 edges, 29273 markings/sec, 610 secs
lola: sara is running 615 secs || 19367157 markings, 78040564 edges, 30008 markings/sec, 615 secs
lola: sara is running 620 secs || 19526409 markings, 78634556 edges, 31850 markings/sec, 620 secs
lola: sara is running 625 secs || 19680872 markings, 79230436 edges, 30893 markings/sec, 625 secs
lola: sara is running 630 secs || 19829807 markings, 79835665 edges, 29787 markings/sec, 630 secs
lola: sara is running 635 secs || 19981518 markings, 80386339 edges, 30342 markings/sec, 635 secs
lola: sara is running 640 secs || 20124917 markings, 80959055 edges, 28680 markings/sec, 640 secs
lola: sara is running 645 secs || 20271109 markings, 81518000 edges, 29238 markings/sec, 645 secs
lola: sara is running 650 secs || 20417614 markings, 82101012 edges, 29301 markings/sec, 650 secs
lola: sara is running 655 secs || 20563281 markings, 82708509 edges, 29133 markings/sec, 655 secs
lola: sara is running 660 secs || 20709205 markings, 83300759 edges, 29185 markings/sec, 660 secs
lola: sara is running 665 secs || 20857218 markings, 83895149 edges, 29603 markings/sec, 665 secs
lola: sara is running 670 secs || 21001642 markings, 84472763 edges, 28885 markings/sec, 670 secs
lola: sara is running 675 secs || 21140163 markings, 85057158 edges, 27704 markings/sec, 675 secs
lola: sara is running 680 secs || 21285917 markings, 85610269 edges, 29151 markings/sec, 680 secs
lola: sara is running 685 secs || 21429086 markings, 86198073 edges, 28634 markings/sec, 685 secs
lola: sara is running 690 secs || 21568681 markings, 86779168 edges, 27919 markings/sec, 690 secs
lola: sara is running 695 secs || 21713074 markings, 87365312 edges, 28879 markings/sec, 695 secs
lola: sara is running 700 secs || 21857304 markings, 87960506 edges, 28846 markings/sec, 700 secs
lola: sara is running 705 secs || 22022660 markings, 88567492 edges, 33071 markings/sec, 705 secs
lola: sara is running 710 secs || 22181971 markings, 89189457 edges, 31862 markings/sec, 710 secs
lola: sara is running 715 secs || 22336217 markings, 89803917 edges, 30849 markings/sec, 715 secs
lola: sara is running 720 secs || 22483220 markings, 90418282 edges, 29401 markings/sec, 720 secs
lola: sara is running 725 secs || 22634927 markings, 91038184 edges, 30341 markings/sec, 725 secs
lola: sara is running 730 secs || 22788939 markings, 91616747 edges, 30802 markings/sec, 730 secs
lola: sara is running 735 secs || 22941439 markings, 92198695 edges, 30500 markings/sec, 735 secs
lola: sara is running 740 secs || 23084045 markings, 92778650 edges, 28521 markings/sec, 740 secs
lola: sara is running 745 secs || 23223505 markings, 93369651 edges, 27892 markings/sec, 745 secs
lola: sara is running 750 secs || 23373588 markings, 93998010 edges, 30017 markings/sec, 750 secs
lola: sara is running 755 secs || 23533617 markings, 94626588 edges, 32006 markings/sec, 755 secs
lola: sara is running 760 secs || 23687304 markings, 95272756 edges, 30737 markings/sec, 760 secs
lola: sara is running 765 secs || 23833612 markings, 95851511 edges, 29262 markings/sec, 765 secs
lola: sara is running 770 secs || 23973493 markings, 96435516 edges, 27976 markings/sec, 770 secs
lola: sara is running 775 secs || 24126341 markings, 97066076 edges, 30570 markings/sec, 775 secs
lola: sara is running 780 secs || 24275226 markings, 97696707 edges, 29777 markings/sec, 780 secs
lola: sara is running 785 secs || 24425961 markings, 98361068 edges, 30147 markings/sec, 785 secs
lola: sara is running 790 secs || 24573497 markings, 99018216 edges, 29507 markings/sec, 790 secs
lola: sara is running 795 secs || 24725517 markings, 99670088 edges, 30404 markings/sec, 795 secs
lola: sara is running 800 secs || 24871294 markings, 100268481 edges, 29155 markings/sec, 800 secs
lola: sara is running 805 secs || 25018936 markings, 100860705 edges, 29528 markings/sec, 805 secs
lola: sara is running 810 secs || 25166184 markings, 101480734 edges, 29450 markings/sec, 810 secs
lola: sara is running 815 secs || 25308191 markings, 102088280 edges, 28401 markings/sec, 815 secs
lola: sara is running 820 secs || 25450529 markings, 102678132 edges, 28468 markings/sec, 820 secs
lola: sara is running 825 secs || 25599685 markings, 103250047 edges, 29831 markings/sec, 825 secs
lola: sara is running 830 secs || 25747841 markings, 103817892 edges, 29631 markings/sec, 830 secs
lola: sara is running 835 secs || 25893815 markings, 104400286 edges, 29195 markings/sec, 835 secs
lola: sara is running 840 secs || 26038149 markings, 105003427 edges, 28867 markings/sec, 840 secs
lola: sara is running 845 secs || 26182223 markings, 105609478 edges, 28815 markings/sec, 845 secs
lola: sara is running 850 secs || 26323034 markings, 106196811 edges, 28162 markings/sec, 850 secs
lola: sara is running 855 secs || 26490689 markings, 106902770 edges, 33531 markings/sec, 855 secs
lola: sara is running 860 secs || 26652415 markings, 107585089 edges, 32345 markings/sec, 860 secs
lola: sara is running 865 secs || 26815302 markings, 108229463 edges, 32577 markings/sec, 865 secs
lola: sara is running 870 secs || 26982888 markings, 108880942 edges, 33517 markings/sec, 870 secs
lola: sara is running 875 secs || 27154025 markings, 109541480 edges, 34227 markings/sec, 875 secs
lola: sara is running 880 secs || 27322483 markings, 110197178 edges, 33692 markings/sec, 880 secs
lola: sara is running 885 secs || 27493638 markings, 110891682 edges, 34231 markings/sec, 885 secs
lola: sara is running 890 secs || 27664683 markings, 111589844 edges, 34209 markings/sec, 890 secs
lola: sara is running 895 secs || 27830620 markings, 112286866 edges, 33187 markings/sec, 895 secs
lola: sara is running 900 secs || 27997094 markings, 112997248 edges, 33295 markings/sec, 900 secs
lola: sara is running 905 secs || 28159292 markings, 113702133 edges, 32440 markings/sec, 905 secs
lola: sara is running 910 secs || 28324149 markings, 114381390 edges, 32971 markings/sec, 910 secs
lola: sara is running 915 secs || 28484482 markings, 115073908 edges, 32067 markings/sec, 915 secs
lola: sara is running 920 secs || 28632774 markings, 115715034 edges, 29658 markings/sec, 920 secs
lola: sara is running 925 secs || 28789819 markings, 116390339 edges, 31409 markings/sec, 925 secs
lola: sara is running 930 secs || 28945408 markings, 117044806 edges, 31118 markings/sec, 930 secs
lola: sara is running 935 secs || 29106660 markings, 117661155 edges, 32250 markings/sec, 935 secs
lola: sara is running 940 secs || 29268780 markings, 118280678 edges, 32424 markings/sec, 940 secs
lola: sara is running 945 secs || 29429406 markings, 118924607 edges, 32125 markings/sec, 945 secs
lola: sara is running 950 secs || 29587665 markings, 119583271 edges, 31652 markings/sec, 950 secs
lola: sara is running 955 secs || 29744841 markings, 120247051 edges, 31435 markings/sec, 955 secs
lola: sara is running 960 secs || 29900078 markings, 120902029 edges, 31047 markings/sec, 960 secs
lola: sara is running 965 secs || 30059374 markings, 121508896 edges, 31859 markings/sec, 965 secs
lola: sara is running 970 secs || 30220051 markings, 122125898 edges, 32135 markings/sec, 970 secs
lola: sara is running 975 secs || 30375803 markings, 122751346 edges, 31150 markings/sec, 975 secs
lola: sara is running 980 secs || 30531319 markings, 123400603 edges, 31103 markings/sec, 980 secs
lola: sara is running 985 secs || 30685656 markings, 124051005 edges, 30867 markings/sec, 985 secs
lola: sara is running 990 secs || 30842119 markings, 124703922 edges, 31293 markings/sec, 990 secs
lola: sara is running 995 secs || 31010372 markings, 125372404 edges, 33651 markings/sec, 995 secs
lola: sara is running 1000 secs || 31177199 markings, 126036207 edges, 33365 markings/sec, 1000 secs
lola: sara is running 1005 secs || 31335307 markings, 126714229 edges, 31622 markings/sec, 1005 secs
lola: sara is running 1010 secs || 31494338 markings, 127388059 edges, 31806 markings/sec, 1010 secs
lola: sara is running 1015 secs || 31656690 markings, 128039584 edges, 32470 markings/sec, 1015 secs
lola: sara is running 1020 secs || 31813286 markings, 128702915 edges, 31319 markings/sec, 1020 secs
lola: sara is running 1025 secs || 31974879 markings, 129380579 edges, 32319 markings/sec, 1025 secs
lola: sara is running 1030 secs || 32136511 markings, 130022385 edges, 32326 markings/sec, 1030 secs
lola: sara is running 1035 secs || 32297377 markings, 130642809 edges, 32173 markings/sec, 1035 secs
lola: sara is running 1040 secs || 32458313 markings, 131269261 edges, 32187 markings/sec, 1040 secs
lola: sara is running 1045 secs || 32617313 markings, 131902610 edges, 31800 markings/sec, 1045 secs
lola: sara is running 1050 secs || 32774709 markings, 132586814 edges, 31479 markings/sec, 1050 secs
lola: sara is running 1055 secs || 32935553 markings, 133224868 edges, 32169 markings/sec, 1055 secs
lola: sara is running 1060 secs || 33094164 markings, 133867925 edges, 31722 markings/sec, 1060 secs
lola: sara is running 1065 secs || 33249332 markings, 134507561 edges, 31034 markings/sec, 1065 secs
lola: sara is running 1070 secs || 33405487 markings, 135115929 edges, 31231 markings/sec, 1070 secs
lola: sara is running 1075 secs || 33558868 markings, 135772215 edges, 30676 markings/sec, 1075 secs
lola: sara is running 1080 secs || 33721744 markings, 136439279 edges, 32575 markings/sec, 1080 secs
lola: sara is running 1085 secs || 33880802 markings, 137115600 edges, 31812 markings/sec, 1085 secs
lola: sara is running 1090 secs || 34037529 markings, 137801241 edges, 31345 markings/sec, 1090 secs
lola: sara is running 1095 secs || 34195334 markings, 138456883 edges, 31561 markings/sec, 1095 secs
lola: sara is running 1100 secs || 34356290 markings, 139079411 edges, 32191 markings/sec, 1100 secs
lola: sara is running 1105 secs || 34517532 markings, 139704704 edges, 32248 markings/sec, 1105 secs
lola: sara is running 1110 secs || 34669849 markings, 140342285 edges, 30463 markings/sec, 1110 secs
lola: sara is running 1115 secs || 34823130 markings, 140961357 edges, 30656 markings/sec, 1115 secs
lola: sara is running 1120 secs || 34971447 markings, 141601059 edges, 29663 markings/sec, 1120 secs
lola: sara is running 1125 secs || 35121434 markings, 142240474 edges, 29997 markings/sec, 1125 secs
lola: sara is running 1130 secs || 35280941 markings, 142873150 edges, 31901 markings/sec, 1130 secs
lola: sara is running 1135 secs || 35441512 markings, 143497680 edges, 32114 markings/sec, 1135 secs
lola: sara is running 1140 secs || 35596752 markings, 144100073 edges, 31048 markings/sec, 1140 secs
lola: sara is running 1145 secs || 35759763 markings, 144775859 edges, 32602 markings/sec, 1145 secs
lola: sara is running 1150 secs || 35919034 markings, 145448528 edges, 31854 markings/sec, 1150 secs
lola: sara is running 1155 secs || 36077580 markings, 146096295 edges, 31709 markings/sec, 1155 secs
lola: sara is running 1160 secs || 36233606 markings, 146744401 edges, 31205 markings/sec, 1160 secs
lola: sara is running 1165 secs || 36390648 markings, 147397945 edges, 31408 markings/sec, 1165 secs
lola: sara is running 1170 secs || 36551034 markings, 148067376 edges, 32077 markings/sec, 1170 secs
lola: sara is running 1175 secs || 36706466 markings, 148725533 edges, 31086 markings/sec, 1175 secs
lola: sara is running 1180 secs || 36862741 markings, 149373262 edges, 31255 markings/sec, 1180 secs
lola: sara is running 1185 secs || 37016766 markings, 150025566 edges, 30805 markings/sec, 1185 secs
lola: sara is running 1190 secs || 37173047 markings, 150709257 edges, 31256 markings/sec, 1190 secs
lola: sara is running 1195 secs || 37322971 markings, 151375789 edges, 29985 markings/sec, 1195 secs
lola: sara is running 1200 secs || 37473833 markings, 152028672 edges, 30172 markings/sec, 1200 secs
lola: sara is running 1205 secs || 37621786 markings, 152653194 edges, 29591 markings/sec, 1205 secs
lola: sara is running 1210 secs || 37777188 markings, 153311359 edges, 31080 markings/sec, 1210 secs
lola: sara is running 1215 secs || 37936519 markings, 153967774 edges, 31866 markings/sec, 1215 secs
lola: sara is running 1220 secs || 38083729 markings, 154601778 edges, 29442 markings/sec, 1220 secs
lola: sara is running 1225 secs || 38225384 markings, 155224004 edges, 28331 markings/sec, 1225 secs
lola: sara is running 1230 secs || 38363024 markings, 155807509 edges, 27528 markings/sec, 1230 secs
lola: sara is running 1235 secs || 38512226 markings, 156445576 edges, 29840 markings/sec, 1235 secs
lola: sara is running 1240 secs || 38647547 markings, 157017567 edges, 27064 markings/sec, 1240 secs
lola: sara is running 1245 secs || 38795414 markings, 157640993 edges, 29573 markings/sec, 1245 secs
lola: sara is running 1250 secs || 38931790 markings, 158216215 edges, 27275 markings/sec, 1250 secs
lola: sara is running 1255 secs || 39076546 markings, 158829282 edges, 28951 markings/sec, 1255 secs
lola: sara is running 1260 secs || 39200988 markings, 159407858 edges, 24888 markings/sec, 1260 secs
lola: sara is running 1265 secs || 39342083 markings, 160011787 edges, 28219 markings/sec, 1265 secs
lola: sara is running 1270 secs || 39496062 markings, 160660873 edges, 30796 markings/sec, 1270 secs
lola: sara is running 1275 secs || 39645999 markings, 161290613 edges, 29987 markings/sec, 1275 secs
lola: sara is running 1280 secs || 39793211 markings, 161897539 edges, 29442 markings/sec, 1280 secs
lola: sara is running 1285 secs || 39938370 markings, 162489630 edges, 29032 markings/sec, 1285 secs
lola: sara is running 1290 secs || 40082244 markings, 163091168 edges, 28775 markings/sec, 1290 secs
lola: sara is running 1295 secs || 40223002 markings, 163681539 edges, 28152 markings/sec, 1295 secs
lola: sara is running 1300 secs || 40364108 markings, 164293917 edges, 28221 markings/sec, 1300 secs
lola: sara is running 1305 secs || 40520051 markings, 164868434 edges, 31189 markings/sec, 1305 secs
lola: sara is running 1310 secs || 40670164 markings, 165457644 edges, 30023 markings/sec, 1310 secs
lola: sara is running 1315 secs || 40818322 markings, 166070169 edges, 29632 markings/sec, 1315 secs
lola: sara is running 1320 secs || 40967913 markings, 166666267 edges, 29918 markings/sec, 1320 secs
lola: sara is running 1325 secs || 41114578 markings, 167256936 edges, 29333 markings/sec, 1325 secs
lola: sara is running 1330 secs || 41262622 markings, 167859261 edges, 29609 markings/sec, 1330 secs
lola: sara is running 1335 secs || 41406541 markings, 168463896 edges, 28784 markings/sec, 1335 secs
lola: sara is running 1340 secs || 41547813 markings, 169068297 edges, 28254 markings/sec, 1340 secs
lola: sara is running 1345 secs || 41698925 markings, 169634417 edges, 30222 markings/sec, 1345 secs
lola: sara is running 1350 secs || 41846452 markings, 170205195 edges, 29505 markings/sec, 1350 secs
lola: sara is running 1355 secs || 41993111 markings, 170789374 edges, 29332 markings/sec, 1355 secs
lola: sara is running 1360 secs || 42133886 markings, 171359450 edges, 28155 markings/sec, 1360 secs
lola: sara is running 1365 secs || 42276346 markings, 171959386 edges, 28492 markings/sec, 1365 secs
lola: sara is running 1370 secs || 42443893 markings, 172558106 edges, 33509 markings/sec, 1370 secs
lola: sara is running 1375 secs || 42603527 markings, 173163055 edges, 31927 markings/sec, 1375 secs
lola: sara is running 1380 secs || 42759871 markings, 173780182 edges, 31269 markings/sec, 1380 secs
lola: sara is running 1385 secs || 42913262 markings, 174385055 edges, 30678 markings/sec, 1385 secs
lola: sara is running 1390 secs || 43062856 markings, 174946369 edges, 29919 markings/sec, 1390 secs
lola: sara is running 1395 secs || 43209684 markings, 175506283 edges, 29366 markings/sec, 1395 secs
lola: sara is running 1400 secs || 43347458 markings, 176074984 edges, 27555 markings/sec, 1400 secs
lola: sara is running 1405 secs || 43493963 markings, 176649851 edges, 29301 markings/sec, 1405 secs
lola: sara is running 1410 secs || 43635952 markings, 177198635 edges, 28398 markings/sec, 1410 secs
lola: sara is running 1415 secs || 43775222 markings, 177759229 edges, 27854 markings/sec, 1415 secs
lola: sara is running 1420 secs || 43920342 markings, 178310405 edges, 29024 markings/sec, 1420 secs
lola: sara is running 1425 secs || 44059794 markings, 178890353 edges, 27890 markings/sec, 1425 secs
lola: sara is running 1430 secs || 44199644 markings, 179468483 edges, 27970 markings/sec, 1430 secs
lola: sara is running 1435 secs || 44338627 markings, 180007191 edges, 27797 markings/sec, 1435 secs
lola: sara is running 1440 secs || 44475080 markings, 180554855 edges, 27291 markings/sec, 1440 secs
lola: sara is running 1445 secs || 44618301 markings, 181128604 edges, 28644 markings/sec, 1445 secs
lola: sara is running 1450 secs || 44767273 markings, 181694639 edges, 29794 markings/sec, 1450 secs
lola: sara is running 1455 secs || 44911372 markings, 182293895 edges, 28820 markings/sec, 1455 secs
lola: sara is running 1460 secs || 45054404 markings, 182884584 edges, 28606 markings/sec, 1460 secs
lola: sara is running 1465 secs || 45201639 markings, 183457036 edges, 29447 markings/sec, 1465 secs
lola: sara is running 1470 secs || 45343713 markings, 184029788 edges, 28415 markings/sec, 1470 secs
lola: sara is running 1475 secs || 45486213 markings, 184602148 edges, 28500 markings/sec, 1475 secs
lola: sara is running 1480 secs || 45626940 markings, 185175691 edges, 28145 markings/sec, 1480 secs
lola: sara is running 1485 secs || 45777814 markings, 185782487 edges, 30175 markings/sec, 1485 secs
lola: sara is running 1490 secs || 45934826 markings, 186389387 edges, 31402 markings/sec, 1490 secs
lola: sara is running 1495 secs || 46086397 markings, 186990843 edges, 30314 markings/sec, 1495 secs
lola: sara is running 1500 secs || 46240052 markings, 187593258 edges, 30731 markings/sec, 1500 secs
lola: sara is running 1505 secs || 46388084 markings, 188192806 edges, 29606 markings/sec, 1505 secs
lola: sara is running 1510 secs || 46543882 markings, 188769776 edges, 31160 markings/sec, 1510 secs
lola: sara is running 1515 secs || 46697238 markings, 189384968 edges, 30671 markings/sec, 1515 secs
lola: sara is running 1520 secs || 46845644 markings, 190000784 edges, 29681 markings/sec, 1520 secs
lola: sara is running 1525 secs || 46990925 markings, 190571236 edges, 29056 markings/sec, 1525 secs
lola: sara is running 1530 secs || 47130412 markings, 191155978 edges, 27897 markings/sec, 1530 secs
lola: sara is running 1535 secs || 47274019 markings, 191784104 edges, 28721 markings/sec, 1535 secs
lola: sara is running 1540 secs || 47420946 markings, 192410755 edges, 29385 markings/sec, 1540 secs
lola: sara is running 1545 secs || 47573788 markings, 192993793 edges, 30568 markings/sec, 1545 secs
lola: sara is running 1550 secs || 47721596 markings, 193592545 edges, 29562 markings/sec, 1550 secs
lola: sara is running 1555 secs || 47865279 markings, 194175683 edges, 28737 markings/sec, 1555 secs
lola: sara is running 1560 secs || 48021876 markings, 194737949 edges, 31319 markings/sec, 1560 secs
lola: sara is running 1565 secs || 48176739 markings, 195314154 edges, 30973 markings/sec, 1565 secs
lola: sara is running 1570 secs || 48324750 markings, 195899105 edges, 29602 markings/sec, 1570 secs
lola: sara is running 1575 secs || 48468296 markings, 196499968 edges, 28709 markings/sec, 1575 secs
lola: sara is running 1580 secs || 48612650 markings, 197102894 edges, 28871 markings/sec, 1580 secs
lola: sara is running 1585 secs || 48757779 markings, 197678241 edges, 29026 markings/sec, 1585 secs
lola: sara is running 1590 secs || 48896444 markings, 198249593 edges, 27733 markings/sec, 1590 secs
lola: sara is running 1595 secs || 49033799 markings, 198823465 edges, 27471 markings/sec, 1595 secs
lola: sara is running 1600 secs || 49175412 markings, 199430729 edges, 28323 markings/sec, 1600 secs
lola: sara is running 1605 secs || 49317207 markings, 200021920 edges, 28359 markings/sec, 1605 secs
lola: sara is running 1610 secs || 49464624 markings, 200626630 edges, 29483 markings/sec, 1610 secs
lola: sara is running 1615 secs || 49611481 markings, 201254133 edges, 29371 markings/sec, 1615 secs
lola: sara is running 1620 secs || 49751785 markings, 201862009 edges, 28061 markings/sec, 1620 secs
lola: sara is running 1625 secs || 49894168 markings, 202444361 edges, 28477 markings/sec, 1625 secs
lola: sara is running 1630 secs || 50034612 markings, 203008681 edges, 28089 markings/sec, 1630 secs
lola: sara is running 1635 secs || 50173057 markings, 203563268 edges, 27689 markings/sec, 1635 secs
lola: sara is running 1640 secs || 50308346 markings, 204135185 edges, 27058 markings/sec, 1640 secs
lola: sara is running 1645 secs || 50446685 markings, 204672899 edges, 27668 markings/sec, 1645 secs
lola: sara is running 1650 secs || 50580839 markings, 205212324 edges, 26831 markings/sec, 1650 secs
lola: sara is running 1655 secs || 50718447 markings, 205760971 edges, 27522 markings/sec, 1655 secs
lola: sara is running 1660 secs || 50867336 markings, 206329249 edges, 29778 markings/sec, 1660 secs
lola: sara is running 1665 secs || 51016463 markings, 206903186 edges, 29825 markings/sec, 1665 secs
lola: sara is running 1670 secs || 51161059 markings, 207504180 edges, 28919 markings/sec, 1670 secs
lola: sara is running 1675 secs || 51298756 markings, 208068434 edges, 27539 markings/sec, 1675 secs
lola: sara is running 1680 secs || 51438806 markings, 208682928 edges, 28010 markings/sec, 1680 secs
lola: sara is running 1685 secs || 51582944 markings, 209259811 edges, 28828 markings/sec, 1685 secs
lola: sara is running 1690 secs || 51724204 markings, 209839256 edges, 28252 markings/sec, 1690 secs
lola: sara is running 1695 secs || 51861453 markings, 210441664 edges, 27450 markings/sec, 1695 secs
lola: sara is running 1700 secs || 51994944 markings, 211028312 edges, 26698 markings/sec, 1700 secs
lola: sara is running 1705 secs || 52133944 markings, 211592837 edges, 27800 markings/sec, 1705 secs
lola: sara is running 1710 secs || 52285345 markings, 212144305 edges, 30280 markings/sec, 1710 secs
lola: sara is running 1715 secs || 52432527 markings, 212724287 edges, 29436 markings/sec, 1715 secs
lola: sara is running 1720 secs || 52578595 markings, 213312932 edges, 29214 markings/sec, 1720 secs
lola: sara is running 1725 secs || 52717160 markings, 213863106 edges, 27713 markings/sec, 1725 secs
lola: sara is running 1730 secs || 52851666 markings, 214407423 edges, 26901 markings/sec, 1730 secs
lola: sara is running 1735 secs || 52980702 markings, 214956748 edges, 25807 markings/sec, 1735 secs
lola: sara is running 1740 secs || 53116411 markings, 215528134 edges, 27142 markings/sec, 1740 secs
lola: sara is running 1745 secs || 53258260 markings, 216099090 edges, 28370 markings/sec, 1745 secs
lola: sara is running 1750 secs || 53407961 markings, 216643911 edges, 29940 markings/sec, 1750 secs
lola: sara is running 1755 secs || 53549616 markings, 217226258 edges, 28331 markings/sec, 1755 secs
lola: sara is running 1760 secs || 53695019 markings, 217800100 edges, 29081 markings/sec, 1760 secs
lola: local time limit reached - aborting
lola: Child process aborted or communication problem between parent and child process
lola: subprocess 15 will run for 1770 seconds at most (--localtimelimit=-1)
lola: ========================================
lola: ...considering subproblem: E (F (((((1 <= CS_0 + CS_1 + CS_2 + CS_3 + CS_4) AND (3 <= TestAlone_4_3_0 + TestAlone_4_3_1 + TestAlone_4_3_2 + TestAlone_4_3_3 + TestAlone_2_0_0 + TestAlone_2_0_1 + TestAlone_2_0_3 + TestAlone_2_0_4 + TestAlone_2_1_0 + TestAlone_2_1_1 + TestAlone_2_1_3 + TestAlone_2_1_4 + TestAlone_2_2_0 + TestAlone_2_2_1 + TestAlone_2_2_3 + TestAlone_2_2_4 + TestAlone_2_3_0 + TestAlone_2_3_1 + TestAlone_2_3_3 +... (shortened)
lola: ========================================
lola: SUBTASK
lola: checking reachability
lola: Planning: workflow for reachability check: stateequation||search (--findpath=off)
lola: STORE
lola: using a bit-perfect encoder (--encoder=bit)
lola: using 60 bytes per marking, with 19 unused bits
lola: using a prefix tree store (--store=prefix)
lola: SEARCH (state space)
lola: state space: using reachability graph (--search=depth)
lola: state space: using reachability preserving stubborn set method with insertion algorithm (--stubborn=tarjan)
lola: RUNNING
lola: state equation: Generated DNF with 5 literals and 2 conjunctive subformulas
lola: state equation: write sara problem file to Peterson-COL-4-ReachabilityCardinality-15.sara
lola: state equation: calling and running sara
sara: try reading problem file Peterson-COL-4-ReachabilityCardinality-15.sara.
lola: SUBRESULT
lola: result: yes
lola: produced by: state space
lola: The predicate is reachable.
lola: lola: RESULT========================================

lola:
SUMMARY: yes yes yes no yes yes no no yes yes no no yes no unknown yes
FORMULA Peterson-COL-4-ReachabilityCardinality-0 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-1 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-2 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-3 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-4 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-5 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-6 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-7 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-8 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-9 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-14 CANNOT_COMPUTE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
FORMULA Peterson-COL-4-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION STUBBORN_SETS TOPOLOGICAL USE_NUPN
----- Kill lola and sara stdout -----
----- Finished stdout -----

BK_STOP 1494504003586

--------------------
content from stderr:

----- Start make prepare stderr -----
----- Start make result stderr -----
----- Start make result stderr -----
----- Kill lola and sara stderr -----
----- Finished stderr -----

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Peterson-PT-4"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/Peterson-PT-4.tgz
mv Peterson-PT-4 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool lola"
echo " Input is Peterson-PT-4, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r048-smll-149440869500061"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;