Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is PermAdmissibility-PT-01, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r040-blw7-149440486600404
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-ReachabilityDeadlock-0

=== Now, execution of the tool begins

BK_START 1496317930887


Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-ctl command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 592 rows 168 cols
invariant : -1'aux8_7 + 1'c12 + -1'aux8_3 + -1'aux8_6 + -1'aux8_2 + 2'c11 + 2'c110 + 2'c9= 0
invariant : 2'c20 + 2'out7_1 + 2'out7_0 + 2'out7_3 + 2'out7_2 + 2'out7_5 + 2'out7_4 + 2'out7_7 + 2'out7_6 + 2'c19 + 1'aux13_2 + 1'aux13_1 + 1'aux13_0 + 1'aux13_7 + 1'c18 + 1'aux13_3 + 1'aux13_4 + 1'aux13_5 + 1'aux13_6 + 1'aux6_0 + 1'c12 + 1'aux6_5 + 1'aux6_1 + 1'aux6_4 + 2'c13 + 1'in3_5 + 1'in3_4 + 1'c6= 2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out3_0 + 1'out3_1 + 1'out3_6 + 1'out3_7 + 1'out3_2 + 1'out3_3 + 1'out3_4 + 1'out3_5= 0
invariant : -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out8_1 + 1'out8_0 + 1'out8_3 + 1'out8_2 + 1'out8_6 + 1'out8_7 + 1'out8_4 + 1'out8_5= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + 2'c14= 0
invariant : -2'c20 + -2'out7_1 + -2'out7_0 + -2'out7_3 + -2'out7_2 + -2'out7_5 + -2'out7_4 + -2'out7_7 + -2'out7_6 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'aux6_0 + -1'c12 + -1'aux6_5 + -1'aux6_1 + -1'aux6_4 + -2'c13 + -2'in3_5 + -2'in3_4 + 2'c5= -2
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + 1'out4_0 + 1'out4_1 + 1'out4_7 + 1'out4_6 + 1'out4_3 + 1'out4_2 + 1'out4_5 + 1'out4_4= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_4 + 1'aux16_5 + -1'c20 + -1'out7_3 + -1'out7_2 + -1'out7_7 + -1'out7_6 + 1'out5_1 + -1'c19 + 1'out5_0 + 1'out5_5 + 1'out5_4 + 1'aux15_1 + 1'aux15_0 + 1'aux15_5 + 1'aux15_4 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -1'out3_6 + -1'out3_7 + -1'out3_2 + -1'out3_3 + 1'out1_0 + 1'out1_5 + 1'out1_1 + 1'out1_4 + -1'c12 + 1'aux12_5 + 1'aux12_4 + 1'aux12_1 + 1'aux12_0 + -2'c13 + -1'c11 + 1'aux10_0 + 1'aux10_1 + 1'aux10_4 + 1'aux10_5= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + -1'aux15_2 + -1'aux15_1 + -1'aux15_0 + -1'aux15_6 + -1'aux15_5 + -1'aux15_4 + -1'aux15_3 + -1'aux15_7 + -1'c18 + 2'c16= 0
invariant : -1'aux14_0 + -1'aux14_1 + -1'aux14_2 + -1'aux14_3 + -1'aux14_4 + -1'aux14_6 + -1'aux14_5 + 1'c20 + -1'aux14_7 + 2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'c15= 0
invariant : 1'aux8_7 + -1'c12 + 1'aux8_3 + 1'aux8_6 + 1'aux8_2 + -2'c11 + -1'aux7_7 + -1'aux7_6 + -1'c110 + -1'aux7_3 + -1'aux7_2 + 2'c8= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out5_1 + 1'out5_2 + 1'out5_0 + 1'out5_5 + 1'out5_6 + 1'out5_3 + 1'out5_4 + 1'out5_7= 0
invariant : -1'aux16_0 + -1'aux16_1 + 1'aux16_2 + 1'aux16_3 + -1'aux16_4 + -1'aux16_5 + 1'aux16_6 + 1'aux16_7 + 1'c20 + 2'out7_3 + 2'out7_2 + 2'out7_7 + 2'out7_6 + -2'out5_1 + -2'out5_0 + -2'out5_5 + -2'out5_4 + 1'aux15_2 + -1'aux15_1 + -1'aux15_0 + 1'aux15_6 + -1'aux15_5 + -1'aux15_4 + 1'aux15_3 + 1'aux15_7 + 1'c18 + 2'out3_6 + 2'out3_7 + 2'out3_2 + 2'out3_3 + -2'out1_0 + -2'out1_5 + -2'out1_1 + -2'out1_4 + -2'c12 + -2'aux12_5 + -2'aux12_4 + -2'aux12_1 + -2'aux12_0 + -2'c11 + 2'aux10_2 + 2'aux10_3 + 2'aux10_6 + 2'aux10_7= 0
invariant : 1'aux16_0 + 1'aux16_1 + 1'aux16_2 + 1'aux16_3 + 1'aux16_4 + 1'aux16_5 + 1'aux16_6 + 1'aux16_7 + -1'c20 + -2'c19 + 1'aux15_2 + 1'aux15_1 + 1'aux15_0 + 1'aux15_6 + 1'aux15_5 + 1'aux15_4 + 1'aux15_3 + -2'aux13_2 + -2'aux13_1 + -2'aux13_0 + 1'aux15_7 + -2'aux13_7 + -1'c18 + -2'aux13_3 + -2'aux13_4 + -2'aux13_5 + -2'aux13_6 + 2'aux12_6 + 2'aux12_5 + 2'aux12_4 + 2'aux12_3 + 2'aux12_2 + 2'aux12_1 + 2'aux12_0 + -4'c13 + 2'aux12_7= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + 1'out6_1 + 1'out6_2 + 1'out6_0 + 1'out6_6 + 1'out6_5 + 1'out6_4 + 1'out6_3 + 1'out6_7= 0
invariant : -1'in3_5 + -1'in3_4 + 1'in1_1 + 1'in1_0= 0
invariant : -1'aux16_0 + -1'aux16_1 + -1'aux16_2 + -1'aux16_3 + -1'aux16_4 + -1'aux16_5 + -1'aux16_6 + -1'aux16_7 + 1'c20 + 2'c19 + 2'c18 + 2'c17= 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out2_0 + 1'out2_7 + 1'out2_5 + 1'out2_6 + 1'out2_3 + 1'out2_4 + 1'out2_1 + 1'out2_2= 0
invariant : = 0
invariant : -1'c20 + -1'out7_1 + -1'out7_0 + -1'out7_3 + -1'out7_2 + -1'out7_5 + -1'out7_4 + -1'out7_7 + -1'out7_6 + -1'c19 + -1'c18 + 1'out1_0 + 1'out1_6 + 1'out1_5 + 1'out1_7 + 1'out1_2 + 1'out1_1 + 1'out1_4 + 1'out1_3= 0
invariant : 1'aux14_0 + 1'aux14_1 + 1'aux14_2 + 1'aux14_3 + 1'aux14_4 + 1'aux14_6 + 1'aux14_5 + -1'c20 + 1'aux14_7 + -2'c19 + -1'aux13_2 + -1'aux13_1 + -1'aux13_0 + -1'aux13_7 + -1'c18 + -1'aux13_3 + -1'aux13_4 + -1'aux13_5 + -1'aux13_6 + -4'c12 + -4'c13 + 2'aux11_5 + 2'aux11_4 + 2'aux11_3 + 2'aux11_2 + 2'aux11_1 + 2'aux11_0 + 2'aux11_7 + 2'aux11_6= 0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,52537,8.64148,232328,2,49937,5,147174,6,0,1098,59698,0


Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,18688,70.8077,1597660,2,15392,1157,3.65527e+06,1135,526,18428,963347,1126

System contains 18688 deadlocks (shown below if less than --print-limit option) !
FORMULA PermAdmissibility-COL-01-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Exit code :0
[ 18688 states ]

BK_STOP 1496318004609

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityDeadlock = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 118 ms
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 168 places.
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 592 transitions.
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.logic.togal.ToGalTransformer toGal
WARNING: Unknown predicate type in boolean expression fr.lip6.move.gal.logic.impl.DeadlockImpl
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property PermAdmissibility-COL-01-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
Jun 01, 2017 11:52:12 AM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 222 ms
Jun 01, 2017 11:52:12 AM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 23 ms
Jun 01, 2017 11:52:13 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 21 place invariants in 130 ms
Jun 01, 2017 11:52:21 AM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 168 variables to be positive in 8460 ms
Jun 01, 2017 11:52:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 592 transitions.
Jun 01, 2017 11:52:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/592 took 85 ms. Total solver calls (SAT/UNSAT): 136(8/128)
Jun 01, 2017 11:52:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :17/592 took 1105 ms. Total solver calls (SAT/UNSAT): 2448(144/2304)
Jun 01, 2017 11:52:24 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :38/592 took 2128 ms. Total solver calls (SAT/UNSAT): 5304(312/4992)
Jun 01, 2017 11:52:25 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :59/592 took 3267 ms. Total solver calls (SAT/UNSAT): 8175(536/7639)
Jun 01, 2017 11:52:26 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :65/592 took 4356 ms. Total solver calls (SAT/UNSAT): 9081(920/8161)
Jun 01, 2017 11:52:27 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :71/592 took 5455 ms. Total solver calls (SAT/UNSAT): 9987(1304/8683)
Jun 01, 2017 11:52:28 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :77/592 took 6548 ms. Total solver calls (SAT/UNSAT): 10893(1688/9205)
Jun 01, 2017 11:52:29 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :83/592 took 7647 ms. Total solver calls (SAT/UNSAT): 11799(2072/9727)
Jun 01, 2017 11:52:30 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :89/592 took 8747 ms. Total solver calls (SAT/UNSAT): 12705(2456/10249)
Jun 01, 2017 11:52:31 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :95/592 took 9845 ms. Total solver calls (SAT/UNSAT): 13611(2840/10771)
Jun 01, 2017 11:52:32 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :102/592 took 10980 ms. Total solver calls (SAT/UNSAT): 14653(3232/11421)
Jun 01, 2017 11:52:34 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :111/592 took 12075 ms. Total solver calls (SAT/UNSAT): 15952(3584/12368)
Jun 01, 2017 11:52:35 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :117/592 took 13221 ms. Total solver calls (SAT/UNSAT): 16858(3968/12890)
Jun 01, 2017 11:52:36 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :124/592 took 14239 ms. Total solver calls (SAT/UNSAT): 17885(4304/13581)
Jun 01, 2017 11:52:37 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :145/592 took 15276 ms. Total solver calls (SAT/UNSAT): 20741(4472/16269)
Jun 01, 2017 11:52:38 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :158/592 took 16393 ms. Total solver calls (SAT/UNSAT): 22569(4800/17769)
Jun 01, 2017 11:52:39 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :179/592 took 17415 ms. Total solver calls (SAT/UNSAT): 25440(5024/20416)
Jun 01, 2017 11:52:40 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :191/592 took 18544 ms. Total solver calls (SAT/UNSAT): 26907(5400/21507)
Jun 01, 2017 11:52:41 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :197/592 took 19588 ms. Total solver calls (SAT/UNSAT): 27525(5784/21741)
Jun 01, 2017 11:52:42 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :204/592 took 20743 ms. Total solver calls (SAT/UNSAT): 28246(6232/22014)
Jun 01, 2017 11:52:43 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :210/592 took 21794 ms. Total solver calls (SAT/UNSAT): 28864(6616/22248)
Jun 01, 2017 11:52:44 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :216/592 took 22839 ms. Total solver calls (SAT/UNSAT): 29482(7000/22482)
Jun 01, 2017 11:52:45 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :225/592 took 23841 ms. Total solver calls (SAT/UNSAT): 30541(7352/23189)
Jun 01, 2017 11:52:46 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :232/592 took 24885 ms. Total solver calls (SAT/UNSAT): 31295(7744/23551)
Jun 01, 2017 11:52:47 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :238/592 took 26023 ms. Total solver calls (SAT/UNSAT): 31913(8128/23785)
Jun 01, 2017 11:52:49 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :245/592 took 27183 ms. Total solver calls (SAT/UNSAT): 32634(8576/24058)
Jun 01, 2017 11:52:50 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :253/592 took 28205 ms. Total solver calls (SAT/UNSAT): 33242(8965/24277)
Jun 01, 2017 11:52:51 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :279/592 took 29282 ms. Total solver calls (SAT/UNSAT): 33832(9353/24479)
Jun 01, 2017 11:52:52 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :290/592 took 30300 ms. Total solver calls (SAT/UNSAT): 34485(9705/24780)
Jun 01, 2017 11:52:53 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :304/592 took 31367 ms. Total solver calls (SAT/UNSAT): 35010(10018/24992)
Jun 01, 2017 11:52:54 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :316/592 took 32410 ms. Total solver calls (SAT/UNSAT): 35691(10376/25315)
Jun 01, 2017 11:52:55 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :324/592 took 33416 ms. Total solver calls (SAT/UNSAT): 36801(10776/26025)
Jun 01, 2017 11:52:56 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :341/592 took 34456 ms. Total solver calls (SAT/UNSAT): 37845(11116/26729)
Jun 01, 2017 11:52:57 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :351/592 took 35569 ms. Total solver calls (SAT/UNSAT): 38904(11500/27404)
Jun 01, 2017 11:52:58 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :358/592 took 36660 ms. Total solver calls (SAT/UNSAT): 40115(11948/28167)
Jun 01, 2017 11:52:59 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :365/592 took 37764 ms. Total solver calls (SAT/UNSAT): 41326(12396/28930)
Jun 01, 2017 11:53:00 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :372/592 took 38858 ms. Total solver calls (SAT/UNSAT): 42537(12844/29693)
Jun 01, 2017 11:53:01 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :379/592 took 39964 ms. Total solver calls (SAT/UNSAT): 43748(13292/30456)
Jun 01, 2017 11:53:03 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :395/592 took 41108 ms. Total solver calls (SAT/UNSAT): 46351(13623/32728)
Jun 01, 2017 11:53:04 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :402/592 took 42207 ms. Total solver calls (SAT/UNSAT): 47562(14071/33491)
Jun 01, 2017 11:53:05 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :409/592 took 43312 ms. Total solver calls (SAT/UNSAT): 48773(14519/34254)
Jun 01, 2017 11:53:06 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :447/592 took 44320 ms. Total solver calls (SAT/UNSAT): 54792(14620/40172)
Jun 01, 2017 11:53:07 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :454/592 took 45433 ms. Total solver calls (SAT/UNSAT): 56003(15068/40935)
Jun 01, 2017 11:53:08 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :474/592 took 46440 ms. Total solver calls (SAT/UNSAT): 59223(15340/43883)
Jun 01, 2017 11:53:09 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :481/592 took 47554 ms. Total solver calls (SAT/UNSAT): 60434(15788/44646)
Jun 01, 2017 11:53:10 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :487/592 took 48607 ms. Total solver calls (SAT/UNSAT): 61472(16172/45300)
Jun 01, 2017 11:53:11 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :493/592 took 49622 ms. Total solver calls (SAT/UNSAT): 62510(16556/45954)
Jun 01, 2017 11:53:12 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :500/592 took 50751 ms. Total solver calls (SAT/UNSAT): 63721(17004/46717)
Jun 01, 2017 11:53:13 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :506/592 took 51911 ms. Total solver calls (SAT/UNSAT): 64759(17388/47371)
Jun 01, 2017 11:53:14 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :512/592 took 52915 ms. Total solver calls (SAT/UNSAT): 65797(17772/48025)
Jun 01, 2017 11:53:16 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :519/592 took 54047 ms. Total solver calls (SAT/UNSAT): 67008(18220/48788)
Jun 01, 2017 11:53:17 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :535/592 took 55106 ms. Total solver calls (SAT/UNSAT): 69611(18551/51060)
Jun 01, 2017 11:53:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :557/592 took 56108 ms. Total solver calls (SAT/UNSAT): 73132(18762/54370)
Jun 01, 2017 11:53:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 56934 ms. Total solver calls (SAT/UNSAT): 78504(18796/59708)
Jun 01, 2017 11:53:18 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 592 transitions.
Jun 01, 2017 11:53:20 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :3/592 took 1178 ms. Total solver calls (SAT/UNSAT): 544(272/272)
Jun 01, 2017 11:53:21 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :7/592 took 2263 ms. Total solver calls (SAT/UNSAT): 1088(544/544)
Jun 01, 2017 11:53:22 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :11/592 took 3315 ms. Total solver calls (SAT/UNSAT): 1632(816/816)
Jun 01, 2017 11:53:23 AM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :15/592 took 4364 ms. Total solver calls (SAT/UNSAT): 2176(1088/1088)
Jun 01, 2017 11:53:24 AM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]
Reverse transition relation is NOT exact ! Due to transitions switch9_2_0, switch9_3_0, switch9_4_0, switch9_3_5, switch9_1_5, switch9_2_5, switch9_7_4, switch9_0_5, switch9_6_4, switch9_3_6, switch9_4_6, switch9_1_6, switch9_2_6, switch9_7_5, switch9_0_6, switch9_6_5, switch9_4_7, switch9_3_7, switch9_2_7, switch9_1_7, switch9_0_7, switch9_5_6, switch10_4_0, switch10_3_0, switch10_2_0, switch9_5_7, switch9_2_1, switch9_3_1, switch9_4_1, switch9_5_0, switch9_6_0, switch9_7_0, switch9_1_2, switch9_4_2, switch9_5_1, switch9_6_1, switch9_7_1, switch9_0_2, switch9_1_3, switch9_4_3, switch9_6_2, switch9_5_2, switch9_0_3, switch9_7_2, switch9_2_4, switch9_1_4, switch9_3_4, switch9_6_3, switch9_5_3, switch9_0_4, switch9_7_3, switch10_7_4, switch10_0_5, switch10_6_4, switch10_3_5, switch10_1_5, switch10_2_5, switch10_7_5, switch10_0_6, switch10_6_5, switch10_3_6, switch10_4_6, switch10_1_6, switch10_2_6, switch10_0_7, switch10_5_6, switch10_4_7, switch10_3_7, switch10_2_7, switch10_1_7, switch10_5_7, switch11_4_0, switch11_3_0, switch11_2_0, switch10_5_0, switch10_6_0, switch10_7_0, switch10_2_1, switch10_3_1, switch10_4_1, switch10_5_1, switch10_6_1, switch10_7_1, switch10_0_2, switch10_1_2, switch10_4_2, switch10_6_2, switch10_5_2, switch10_0_3, switch10_7_2, switch10_1_3, switch10_4_3, switch10_6_3, switch10_5_3, switch10_0_4, switch10_7_3, switch10_2_4, switch10_1_4, switch10_3_4, switch11_4_6, switch11_3_6, switch11_2_6, switch11_1_6, switch11_0_6, switch11_7_5, switch11_6_5, switch11_3_5, switch11_2_5, switch11_1_5, switch11_0_5, switch11_7_4, switch11_6_4, switch11_5_7, switch11_3_7, switch11_4_7, switch11_1_7, switch11_2_7, switch11_0_7, switch11_5_6, switch11_1_2, switch11_4_2, switch11_6_1, switch11_5_1, switch11_0_2, switch11_7_1, switch11_2_1, switch11_4_1, switch11_3_1, switch11_6_0, switch11_5_0, switch11_7_0, switch11_1_4, switch11_2_4, switch11_3_4, switch11_5_3, switch11_6_3, switch11_7_3, switch11_0_4, switch11_1_3, switch11_4_3, switch11_5_2, switch11_6_2, switch11_7_2, switch11_0_3, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :64/384/144/592

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PermAdmissibility-PT-01"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/PermAdmissibility-PT-01.tgz
mv PermAdmissibility-PT-01 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is PermAdmissibility-PT-01, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r040-blw7-149440486600404"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityDeadlock.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;