About the Execution of ITS-Tools for BridgeAndVehicles-COL-V20P20N10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1140.600 | 47324.00 | 96763.00 | 154.10 | T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Waiting for the VM to be ready (probing ssh)
.......
=====================================================================
Generated by BenchKit 2-3254
Executing tool itstools
Input is BridgeAndVehicles-COL-V20P20N10, examination is ReachabilityDeadlock
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r010-csrt-149436129500305
=====================================================================
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME BridgeAndVehicles-COL-V20P20N10-ReachabilityDeadlock-0
=== Now, execution of the tool begins
BK_START 1496254553507
Using solver YICES2 to compute partial order matrices.
Built C files in :
/home/mcc/execution
its-ctl command run as :
/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityDeadlock.pnml.gal -t CGAL -ctl DEADLOCK
No direction supplied, using forward translation only.
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
// Phase 1: matrix 548 rows 68 cols
invariant : 1'sens0:CONTROLEUR_0 + 1'sens0:CHOIX_0 + 1'sens0:VIDANGE_0 + 1'sens1:CONTROLEUR_1 + 1'sens1:CHOIX_1 + 1'sens1:VIDANGE_1= 1
invariant : -1'CAPACITE:CAPACITE[0] + 1'SORTI_A:SORTI_A[0] + 1'ROUTE_A:ROUTE_A[0] + 1'ATTENTE_A:ATTENTE_A[0] + 1'ATTENTE_B:ATTENTE_B[0] + 1'ROUTE_B:ROUTE_B[0] + 1'SORTI_B:SORTI_B[0]= 20
invariant : 1'CAPACITE:CAPACITE[0] + -1'SORTI_A:SORTI_A[0] + -1'ROUTE_A:ROUTE_A[0] + -1'ATTENTE_A:ATTENTE_A[0] + 1'SUR_PONT_B:SUR_PONT_B[0]= 0
invariant : 1'SORTI_A:SORTI_A[0] + 1'ROUTE_A:ROUTE_A[0] + 1'ATTENTE_A:ATTENTE_A[0] + 1'SUR_PONT_A:SUR_PONT_A[0]= 20
invariant : 1'compteur0:COMPTEUR_0 + 1'compteur1:COMPTEUR_1 + 1'compteur2:COMPTEUR_2 + 1'compteur3:COMPTEUR_3 + 1'compteur4:COMPTEUR_4 + 1'compteur5:COMPTEUR_5 + 1'compteur6:COMPTEUR_6 + 1'compteur7:COMPTEUR_7 + 1'compteur8:COMPTEUR_8 + 1'compteur9:COMPTEUR_9 + 1'compteur10:COMPTEUR_10= 1
invariant : 1'voitureA0:NB_ATTENTE_A_0 + 1'voitureA1:NB_ATTENTE_A_1 + 1'voitureA2:NB_ATTENTE_A_2 + 1'voitureA3:NB_ATTENTE_A_3 + 1'voitureA4:NB_ATTENTE_A_4 + 1'voitureA5:NB_ATTENTE_A_5 + 1'voitureA6:NB_ATTENTE_A_6 + 1'voitureA7:NB_ATTENTE_A_7 + 1'voitureA8:NB_ATTENTE_A_8 + 1'voitureA9:NB_ATTENTE_A_9 + 1'voitureA10:NB_ATTENTE_A_10 + 1'voitureA11:NB_ATTENTE_A_11 + 1'voitureA12:NB_ATTENTE_A_12 + 1'voitureA13:NB_ATTENTE_A_13 + 1'voitureA14:NB_ATTENTE_A_14 + 1'voitureA15:NB_ATTENTE_A_15 + 1'voitureA16:NB_ATTENTE_A_16 + 1'voitureA17:NB_ATTENTE_A_17 + 1'voitureA18:NB_ATTENTE_A_18 + 1'voitureA19:NB_ATTENTE_A_19 + 1'voitureA20:NB_ATTENTE_A_20= 1
invariant : 1'voitureB0:NB_ATTENTE_B_0 + 1'voitureB1:NB_ATTENTE_B_1 + 1'voitureB2:NB_ATTENTE_B_2 + 1'voitureB3:NB_ATTENTE_B_3 + 1'voitureB4:NB_ATTENTE_B_4 + 1'voitureB5:NB_ATTENTE_B_5 + 1'voitureB6:NB_ATTENTE_B_6 + 1'voitureB7:NB_ATTENTE_B_7 + 1'voitureB8:NB_ATTENTE_B_8 + 1'voitureB9:NB_ATTENTE_B_9 + 1'voitureB10:NB_ATTENTE_B_10 + 1'voitureB11:NB_ATTENTE_B_11 + 1'voitureB12:NB_ATTENTE_B_12 + 1'voitureB13:NB_ATTENTE_B_13 + 1'voitureB14:NB_ATTENTE_B_14 + 1'voitureB15:NB_ATTENTE_B_15 + 1'voitureB16:NB_ATTENTE_B_16 + 1'voitureB17:NB_ATTENTE_B_17 + 1'voitureB18:NB_ATTENTE_B_18 + 1'voitureB19:NB_ATTENTE_B_19 + 1'voitureB20:NB_ATTENTE_B_20= 1
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,6.73257e+06,28.1054,767512,93659,30,1.74029e+06,242,316,1.79421e+06,17,443,0
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
dead,20,43.3003,767512,87,8,1.74029e+06,1067,1262,1.96738e+06,91,3358,5553424
System contains 20 deadlocks (shown below if less than --print-limit option) !
FORMULA BridgeAndVehicles-COL-V20P20N10-ReachabilityDeadlock-0 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL USE_NUPN
Exit code :0
[ 20 states ]
BK_STOP 1496254600831
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityDeadlock = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityDeadlock -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.201.v20161025-1711.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination ReachabilityDeadlock -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -smt
May 31, 2017 6:15:55 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 31, 2017 6:15:55 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
May 31, 2017 6:15:56 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 1464 ms
May 31, 2017 6:15:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 15 places.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :sens->CONTROLEUR,CHOIX,VIDANGE,
compteur->COMPTEUR,
Dot->CAPACITE,SORTI_A,ROUTE_A,ATTENTE_A,SUR_PONT_A,SUR_PONT_B,ATTENTE_B,ROUTE_B,SORTI_B,
voitureA->NB_ATTENTE_A,
voitureB->NB_ATTENTE_B,
May 31, 2017 6:15:56 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 11 transitions.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.logic.togal.ToGalTransformer toGal
WARNING: Unknown predicate type in boolean expression fr.lip6.move.gal.logic.impl.DeadlockImpl
May 31, 2017 6:15:56 PM fr.lip6.move.gal.application.MccTranslator applyOrder
INFO: Applying decomposition
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.CompositeBuilder decomposeWithOrder
INFO: Decomposing Gal with order
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 59 instantiations of transitions. Total transitions/syncs built is 178
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property BridgeAndVehicles-COL-V20P20N10-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 68 ms
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.CompositeBuilder rewriteArraysToAllowPartition
INFO: Rewriting arrays NB_ATTENTE_A, NB_ATTENTE_B, CONTROLEUR, CHOIX, COMPTEUR, VIDANGE to variables to allow decomposition.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.Instantiator fuseIsomorphicEffects
INFO: Removed a total of 125 redundant transitions.
May 31, 2017 6:15:56 PM fr.lip6.move.gal.instantiate.PropertySimplifier rewriteWithInitialState
INFO: Reachable property BridgeAndVehicles-COL-V20P20N10-ReachabilityDeadlock-0 is trivially true : it is verified in initial state.
May 31, 2017 6:15:56 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityDeadlock.pnml.gal : 11 ms
May 31, 2017 6:15:57 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 7 place invariants in 45 ms
May 31, 2017 6:15:57 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 68 variables to be positive in 601 ms
May 31, 2017 6:15:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 548 transitions.
May 31, 2017 6:15:57 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :0/548 took 70 ms. Total solver calls (SAT/UNSAT): 293(2/291)
May 31, 2017 6:15:58 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :24/548 took 1097 ms. Total solver calls (SAT/UNSAT): 7246(55/7191)
May 31, 2017 6:16:00 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :52/548 took 2113 ms. Total solver calls (SAT/UNSAT): 15569(139/15430)
May 31, 2017 6:16:01 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :76/548 took 3135 ms. Total solver calls (SAT/UNSAT): 22606(211/22395)
May 31, 2017 6:16:02 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :104/548 took 4143 ms. Total solver calls (SAT/UNSAT): 30754(295/30459)
May 31, 2017 6:16:03 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :138/548 took 5170 ms. Total solver calls (SAT/UNSAT): 40752(397/40355)
May 31, 2017 6:16:04 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :169/548 took 6170 ms. Total solver calls (SAT/UNSAT): 49916(490/49426)
May 31, 2017 6:16:05 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :202/548 took 7192 ms. Total solver calls (SAT/UNSAT): 59636(589/59047)
May 31, 2017 6:16:06 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :235/548 took 8212 ms. Total solver calls (SAT/UNSAT): 69356(688/68668)
May 31, 2017 6:16:07 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :267/548 took 9240 ms. Total solver calls (SAT/UNSAT): 78787(784/78003)
May 31, 2017 6:16:08 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :299/548 took 10249 ms. Total solver calls (SAT/UNSAT): 88229(880/87349)
May 31, 2017 6:16:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :330/548 took 11263 ms. Total solver calls (SAT/UNSAT): 97393(973/96420)
May 31, 2017 6:16:10 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :364/548 took 12264 ms. Total solver calls (SAT/UNSAT): 107391(1075/106316)
May 31, 2017 6:16:11 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :398/548 took 13270 ms. Total solver calls (SAT/UNSAT): 117389(1177/116212)
May 31, 2017 6:16:12 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :431/548 took 14289 ms. Total solver calls (SAT/UNSAT): 127109(1276/125833)
May 31, 2017 6:16:13 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :466/548 took 15290 ms. Total solver calls (SAT/UNSAT): 135956(1367/134589)
May 31, 2017 6:16:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :540/548 took 16291 ms. Total solver calls (SAT/UNSAT): 145018(1495/143523)
May 31, 2017 6:16:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 16314 ms. Total solver calls (SAT/UNSAT): 145178(1508/143670)
May 31, 2017 6:16:14 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 548 transitions.
May 31, 2017 6:16:15 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :11/548 took 1020 ms. Total solver calls (SAT/UNSAT): 3516(156/3360)
May 31, 2017 6:16:16 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :26/548 took 2051 ms. Total solver calls (SAT/UNSAT): 7800(281/7519)
May 31, 2017 6:16:17 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :48/548 took 3076 ms. Total solver calls (SAT/UNSAT): 14276(345/13931)
May 31, 2017 6:16:18 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :71/548 took 4102 ms. Total solver calls (SAT/UNSAT): 21034(412/20622)
May 31, 2017 6:16:19 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :93/548 took 5126 ms. Total solver calls (SAT/UNSAT): 27514(476/27038)
May 31, 2017 6:16:20 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :116/548 took 6141 ms. Total solver calls (SAT/UNSAT): 34272(543/33729)
May 31, 2017 6:16:21 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :138/548 took 7176 ms. Total solver calls (SAT/UNSAT): 40752(607/40145)
May 31, 2017 6:16:22 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :159/548 took 8185 ms. Total solver calls (SAT/UNSAT): 46954(668/46286)
May 31, 2017 6:16:23 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :182/548 took 9218 ms. Total solver calls (SAT/UNSAT): 53712(735/52977)
May 31, 2017 6:16:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :205/548 took 10239 ms. Total solver calls (SAT/UNSAT): 60470(802/59668)
May 31, 2017 6:16:25 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :228/548 took 11313 ms. Total solver calls (SAT/UNSAT): 67409(868/66541)
May 31, 2017 6:16:26 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :246/548 took 12350 ms. Total solver calls (SAT/UNSAT): 72589(921/71668)
May 31, 2017 6:16:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :259/548 took 13416 ms. Total solver calls (SAT/UNSAT): 76381(959/75422)
May 31, 2017 6:16:28 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :271/548 took 14423 ms. Total solver calls (SAT/UNSAT): 79899(994/78905)
May 31, 2017 6:16:29 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :283/548 took 15446 ms. Total solver calls (SAT/UNSAT): 83598(1028/82570)
May 31, 2017 6:16:30 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :296/548 took 16492 ms. Total solver calls (SAT/UNSAT): 87395(1066/86329)
May 31, 2017 6:16:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :309/548 took 17539 ms. Total solver calls (SAT/UNSAT): 91191(1104/90087)
May 31, 2017 6:16:32 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :321/548 took 18543 ms. Total solver calls (SAT/UNSAT): 94709(1139/93570)
May 31, 2017 6:16:33 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :334/548 took 19598 ms. Total solver calls (SAT/UNSAT): 98505(1177/97328)
May 31, 2017 6:16:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :347/548 took 20653 ms. Total solver calls (SAT/UNSAT): 102301(1215/101086)
May 31, 2017 6:16:35 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :360/548 took 21759 ms. Total solver calls (SAT/UNSAT): 106278(1252/105026)
May 31, 2017 6:16:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :373/548 took 22813 ms. Total solver calls (SAT/UNSAT): 110075(1290/108785)
May 31, 2017 6:16:38 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :386/548 took 23869 ms. Total solver calls (SAT/UNSAT): 113871(1328/112543)
May 31, 2017 6:16:39 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :399/548 took 24928 ms. Total solver calls (SAT/UNSAT): 117667(1366/116301)
May 31, 2017 6:16:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed :410/548 took 25938 ms. Total solver calls (SAT/UNSAT): 120907(1398/119509)
May 31, 2017 6:16:40 PM fr.lip6.move.gal.itstools.Runner runTool
INFO: Standard error output from running tool CommandLine [args=[/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201705302212/bin/its-ctl-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityDeadlock.pnml.gal, -t, CGAL, -ctl, DEADLOCK], workingDir=/home/mcc/execution]
built 159 ordering constraints for composite.
Reverse transition relation is NOT exact ! Due to transitions enregistrement_A, liberation_A, basculement, liberation_B, enregistrement_B, altern_cpt, timeout_A, timeout_B, Intersection with reachable at each step enabled. (destroyed/reverse/intersect/total) :0/3/8/11
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BridgeAndVehicles-COL-V20P20N10"
export BK_EXAMINATION="ReachabilityDeadlock"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
tar xzf /home/mcc/BenchKit/INPUTS/BridgeAndVehicles-COL-V20P20N10.tgz
mv BridgeAndVehicles-COL-V20P20N10 execution
# this is for BenchKit: explicit launching of the test
cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-3254"
echo " Executing tool itstools"
echo " Input is BridgeAndVehicles-COL-V20P20N10, examination is ReachabilityDeadlock"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r010-csrt-149436129500305"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityDeadlock" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityDeadlock" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityDeadlock.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityDeadlock.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityDeadlock.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;