fond
Model Checking Contest @ Petri Nets 2016
6th edition, Toruń, Poland, June 21, 2016
Execution of r196kn-qhx2-146444261600589
Last Updated
June 30, 2016

About the Execution of Tapaal(PAR) for S_SwimmingPool-PT-03

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
111.110 586.00 80.00 0.00 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...........
=====================================================================
Generated by BenchKit 2-2979
Executing tool tapaalPAR
Input is S_SwimmingPool-PT-03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r196kn-qhx2-146444261600589
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-0
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-1
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-10
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-11
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-12
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-13
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-14
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-15
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-2
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-3
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-4
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-5
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-6
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-7
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-8
FORMULA_NAME SwimmingPool-PT-03-CTLFireability-9

=== Now, execution of the tool begins

BK_START 1465109186580


**********************************************
* TAPAAL Parallel verifying CTLFireability *
**********************************************

BK_STOP 1465109187166

--------------------
content from stderr:

/home/mcc/BenchKit/bin/ctl.sh: line 82: 336 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 338 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 340 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 342 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 344 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 346 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 348 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 350 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 352 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 354 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 356 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 358 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 360 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 362 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 364 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 366 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 368 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 370 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 372 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 374 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 376 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 378 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 380 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 382 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 384 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 386 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 388 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 390 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 392 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 394 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 396 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 398 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 400 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 402 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 404 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 406 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 408 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 410 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 412 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 414 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 416 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 418 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 420 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 422 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 424 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 426 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 428 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 430 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 432 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 433 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 434 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 435 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 436 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 437 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 438 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 439 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 440 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 441 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 442 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 443 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 444 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 445 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 446 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 447 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_SwimmingPool-PT-03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaalPAR"
export BK_RESULT_DIR="/home/fko/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_SwimmingPool-PT-03.tgz
mv S_SwimmingPool-PT-03 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-2979"
echo " Executing tool tapaalPAR"
echo " Input is S_SwimmingPool-PT-03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r196kn-qhx2-146444261600589"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;