fond
Model Checking Contest @ Petri Nets 2016
6th edition, Toruń, Poland, June 21, 2016
Execution of r136kn-smll-146384397900148
Last Updated
June 30, 2016

About the Execution of Tapaal(PAR) for TokenRing-PT-050

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1257.460 14719.00 20124.00 77.60 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...........
=====================================================================
Generated by BenchKit 2-2979
Executing tool tapaalPAR
Input is TokenRing-PT-050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r136kn-smll-146384397900148
=====================================================================


--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TokenRing-COL-050-CTLFireability-0
FORMULA_NAME TokenRing-COL-050-CTLFireability-1
FORMULA_NAME TokenRing-COL-050-CTLFireability-10
FORMULA_NAME TokenRing-COL-050-CTLFireability-11
FORMULA_NAME TokenRing-COL-050-CTLFireability-12
FORMULA_NAME TokenRing-COL-050-CTLFireability-13
FORMULA_NAME TokenRing-COL-050-CTLFireability-14
FORMULA_NAME TokenRing-COL-050-CTLFireability-15
FORMULA_NAME TokenRing-COL-050-CTLFireability-2
FORMULA_NAME TokenRing-COL-050-CTLFireability-3
FORMULA_NAME TokenRing-COL-050-CTLFireability-4
FORMULA_NAME TokenRing-COL-050-CTLFireability-5
FORMULA_NAME TokenRing-COL-050-CTLFireability-6
FORMULA_NAME TokenRing-COL-050-CTLFireability-7
FORMULA_NAME TokenRing-COL-050-CTLFireability-8
FORMULA_NAME TokenRing-COL-050-CTLFireability-9

=== Now, execution of the tool begins

BK_START 1463866859543


**********************************************
* TAPAAL Parallel verifying CTLFireability *
**********************************************

BK_STOP 1463866874262

--------------------
content from stderr:

/home/mcc/BenchKit/bin/ctl.sh: line 82: 382 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 384 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 386 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 388 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 390 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 392 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 394 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 396 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 398 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 402 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 404 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 406 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 408 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 410 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 414 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 82: 416 Illegal instruction timeout $TIMEOUT_SEQ $VERIFYPN_SEQ -ctl czero -s DFS -n -x $i model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 418 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 420 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 422 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 424 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 428 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 430 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 432 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 434 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 436 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 438 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 440 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 442 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 444 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 446 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 448 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 90: 450 Illegal instruction timeout $TIMEOUT_COM $VERIFYPN_COM -ctl czero -s DFS -n -x $j model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 452 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 454 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 456 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 458 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 460 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 462 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 464 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 466 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 468 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 470 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 472 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 474 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 476 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 478 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 480 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 98: 482 Illegal instruction timeout $TIMEOUT_PAR $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 484 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 485 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 486 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 487 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 488 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 489 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 490 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 491 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 492 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 493 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 494 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 495 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 496 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 497 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 498 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml
/home/mcc/BenchKit/bin/ctl.sh: line 105: 499 Illegal instruction $VERIFYPN_PAR -ctl par -s DFS -n -x $k model.pnml CTLFireability.xml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TokenRing-PT-050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaalPAR"
export BK_RESULT_DIR="/root/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/TokenRing-PT-050.tgz
mv TokenRing-PT-050 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-2979"
echo " Executing tool tapaalPAR"
echo " Input is TokenRing-PT-050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r136kn-smll-146384397900148"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;