Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
...........
=====================================================================
Generated by BenchKit 2-2979
Executing tool marcie
Input is S_PermAdmissibility-COL-01, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 1
Run identifier is r185kn-smll-146444131201218
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-0
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-1
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-10
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-11
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-12
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-13
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-14
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-15
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-2
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-3
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-4
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-5
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-6
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-7
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-8
FORMULA_NAME PermAdmissibility-COL-01-CTLCardinality-9

=== Now, execution of the tool begins

BK_START 1464972431905


Marcie rev. 8535M (built: crohr on 2016-04-27)
A model checker for Generalized Stochastic Petri nets

authors: Alex Tovchigrechko (IDD package and CTL model checking)

Martin Schwarick (Symbolic numerical analysis and CSL model checking)

Christian Rohr (Simulative and approximative numerical model checking)

marcie@informatik.tu-cottbus.de

called as: marcie --net-file=model.pnml --mcc-file=CTLCardinality.xml --mcc-mode --memory=6 --suppress

parse successfull
net created successfully

Unfolding complete |P|=208|T|=1024|A|=6080
Time for unfolding: 0m 2.718sec

Net: PermAdmissibility_COL_01
(NrP: 208 NrTr: 1024 NrArc: 5984)

net check time: 0m 0.001sec

parse formulas
formulas created successfully
place and transition orderings generation:0m 0.028sec

init dd package: 0m 3.684sec


RS generation: 0m27.806sec


-> reachability set: #nodes 55694 (5.6e+04) #states 52,537 (4)



starting MCC model checker
--------------------------

checking: AF [3<=c13_dot]
normalized: ~ [EG [~ [3<=c13_dot]]]

abstracting: (3<=c13_dot) states: 0

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-7 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.030sec

checking: AG [EF [~ [3<=c12_dot]]]
normalized: ~ [E [true U ~ [E [true U ~ [3<=c12_dot]]]]]

abstracting: (3<=c12_dot) states: 0
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-11 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m28.154sec

checking: EF [2<=c8_dot]
normalized: E [true U 2<=c8_dot]

abstracting: (2<=c8_dot) states: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-14 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.030sec

checking: EF [[AG [c11_dot<=c6_dot] & c19_dot<=c20_dot]]
normalized: E [true U [c19_dot<=c20_dot & ~ [E [true U ~ [c11_dot<=c6_dot]]]]]

abstracting: (c11_dot<=c6_dot) states: 52,473 (4)
abstracting: (c19_dot<=c20_dot) states: 47,865 (4)
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-13 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 4.021sec

checking: ~ [AF [AF [2<=sum(out4_input7, out4_input6, out4_input5, out4_input4, out4_input3, out4_input2, out4_input1, out4_input0)]]]
normalized: EG [EG [~ [2<=sum(out4_input7, out4_input6, out4_input5, out4_input4, out4_input3, out4_input2, out4_input1, out4_input0)]]]

abstracting: (2<=sum(out4_input7, out4_input6, out4_input5, out4_input4, out4_input3, out4_input2, out4_input1, out4_input0)) states: 0

EG iterations: 0

EG iterations: 0
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-12 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.050sec

checking: E [2<=c9_dot U AF [3<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0)]]
normalized: E [2<=c9_dot U ~ [EG [~ [3<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0)]]]]

abstracting: (3<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0)) states: 0

EG iterations: 0
abstracting: (2<=c9_dot) states: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-0 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.065sec

checking: EX [AF [[2<=c16_dot & 2<=sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)]]]
normalized: EX [~ [EG [~ [[2<=c16_dot & 2<=sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)]]]]]

abstracting: (2<=sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)) states: 1,888 (3)
abstracting: (2<=c16_dot) states: 0

EG iterations: 0
.-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-4 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.087sec

checking: EX [AG [[3<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0) | c17_dot<=c20_dot]]]
normalized: EX [~ [E [true U ~ [[3<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0) | c17_dot<=c20_dot]]]]]

abstracting: (c17_dot<=c20_dot) states: 51,369 (4)
abstracting: (3<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0)) states: 0
.-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-5 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 1m 1.362sec

checking: EG [[~ [2<=c15_dot] & AX [c19_dot<=sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)]]]
normalized: EG [[~ [2<=c15_dot] & ~ [EX [~ [c19_dot<=sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)]]]]]

abstracting: (c19_dot<=sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)) states: 47,865 (4)
.abstracting: (2<=c15_dot) states: 0
..............
EG iterations: 14
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-9 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 1.799sec

checking: A [~ [[3<=sum(out6_input7, out6_input6, out6_input5, out6_input4, out6_input3, out6_input2, out6_input1, out6_input0) & c20_dot<=c5_dot]] U AG [1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)]]
normalized: [~ [EG [E [true U ~ [1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)]]]] & ~ [E [E [true U ~ [1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)]] U [[3<=sum(out6_input7, out6_input6, out6_input5, out6_input4, out6_input3, out6_input2, out6_input1, out6_input0) & c20_dot<=c5_dot] & E [true U ~ [1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)]]]]]]

abstracting: (1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)) states: 1,408 (3)
abstracting: (c20_dot<=c5_dot) states: 33,849 (4)
abstracting: (3<=sum(out6_input7, out6_input6, out6_input5, out6_input4, out6_input3, out6_input2, out6_input1, out6_input0)) states: 0
abstracting: (1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)) states: 1,408 (3)
abstracting: (1<=sum(aux11_input7, aux11_input6, aux11_input5, aux11_input4, aux11_input3, aux11_input2, aux11_input1, aux11_input0)) states: 1,408 (3)

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-6 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m25.762sec

checking: [~ [E [2<=c9_dot U 2<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)]] & EF [AG [sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)<=c7_dot]]]
normalized: [E [true U ~ [E [true U ~ [sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)<=c7_dot]]]] & ~ [E [2<=c9_dot U 2<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)]]]

abstracting: (2<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)) states: 10,512 (4)
abstracting: (2<=c9_dot) states: 0
abstracting: (sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)<=c7_dot) states: 52,117 (4)
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-15 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 4.187sec

checking: E [AG [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=c19_dot] U ~ [[c8_dot<=c20_dot | sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)<=c17_dot]]]
normalized: E [~ [E [true U ~ [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=c19_dot]]] U ~ [[c8_dot<=c20_dot | sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)<=c17_dot]]]

abstracting: (sum(aux12_input7, aux12_input6, aux12_input5, aux12_input4, aux12_input3, aux12_input2, aux12_input1, aux12_input0)<=c17_dot) states: 48,313 (4)
abstracting: (c8_dot<=c20_dot) states: 52,521 (4)
abstracting: (sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=c19_dot) states: 20,265 (4)
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-10 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m17.921sec

checking: EF [EX [[sum(aux9_input7, aux9_input6, aux9_input5, aux9_input4, aux9_input3, aux9_input2, aux9_input1, aux9_input0)<=sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0) & 3<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)]]]
normalized: E [true U EX [[sum(aux9_input7, aux9_input6, aux9_input5, aux9_input4, aux9_input3, aux9_input2, aux9_input1, aux9_input0)<=sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0) & 3<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)]]]

abstracting: (3<=sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)) states: 0
abstracting: (sum(aux9_input7, aux9_input6, aux9_input5, aux9_input4, aux9_input3, aux9_input2, aux9_input1, aux9_input0)<=sum(aux15_input7, aux15_input6, aux15_input5, aux15_input4, aux15_input3, aux15_input2, aux15_input1, aux15_input0)) states: 51,001 (4)
.-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-8 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.173sec

checking: [AX [2<=sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)] | [AG [[3<=c110_dot | c8_dot<=c20_dot]] | [[[sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=c19_dot & 3<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)] & ~ [c14_dot<=c12_dot]] | AF [2<=c7_dot]]]]
normalized: [[[~ [EG [~ [2<=c7_dot]]] | [~ [c14_dot<=c12_dot] & [sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=c19_dot & 3<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)]]] | ~ [E [true U ~ [[3<=c110_dot | c8_dot<=c20_dot]]]]] | ~ [EX [~ [2<=sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)]]]]

abstracting: (2<=sum(aux7_input7, aux7_input6, aux7_input5, aux7_input4, aux7_input3, aux7_input2, aux7_input1, aux7_input0)) states: 32
.abstracting: (c8_dot<=c20_dot) states: 52,521 (4)
abstracting: (3<=c110_dot) states: 0
abstracting: (3<=sum(in4_input7, in4_input6, in4_input5, in4_input4, in4_input3, in4_input2, in4_input1, in4_input0)) states: 0
abstracting: (sum(aux14_input7, aux14_input6, aux14_input5, aux14_input4, aux14_input3, aux14_input2, aux14_input1, aux14_input0)<=c19_dot) states: 20,265 (4)
abstracting: (c14_dot<=c12_dot) states: 51,641 (4)
abstracting: (2<=c7_dot) states: 0

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-3 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 2.969sec

checking: ~ [AF [[[c9_dot<=sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0) & sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0)] & [3<=c12_dot & c12_dot<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)]]]]
normalized: EG [~ [[[c9_dot<=sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0) & sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0)] & [3<=c12_dot & c12_dot<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)]]]]

abstracting: (c12_dot<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)) states: 52,281 (4)
abstracting: (3<=c12_dot) states: 0
abstracting: (sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)<=sum(out5_input7, out5_input6, out5_input5, out5_input4, out5_input3, out5_input2, out5_input1, out5_input0)) states: 52,532 (4)
abstracting: (c9_dot<=sum(in1_input7, in1_input6, in1_input5, in1_input4, in1_input3, in1_input2, in1_input1, in1_input0)) states: 52,521 (4)

EG iterations: 0
-> the formula is TRUE

FORMULA PermAdmissibility-COL-01-CTLCardinality-1 TRUE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m 0.281sec

checking: A [sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0) U [~ [c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)] & [sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0) & sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)]]]
normalized: [~ [EG [~ [[[sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0) & sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)] & ~ [c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)]]]]] & ~ [E [~ [[[sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0) & sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)] & ~ [c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)]]] U [~ [[[sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0) & sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)] & ~ [c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)]]] & ~ [sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0)]]]]]

abstracting: (sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(out7_input7, out7_input6, out7_input5, out7_input4, out7_input3, out7_input2, out7_input1, out7_input0)) states: 24,505 (4)
abstracting: (c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)) states: 52,536 (4)
abstracting: (sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)) states: 52,532 (4)
abstracting: (sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)) states: 33,849 (4)
abstracting: (c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)) states: 52,536 (4)
abstracting: (sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)) states: 52,532 (4)
abstracting: (sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)) states: 33,849 (4)
abstracting: (c5_dot<=sum(aux13_input7, aux13_input6, aux13_input5, aux13_input4, aux13_input3, aux13_input2, aux13_input1, aux13_input0)) states: 52,536 (4)
abstracting: (sum(in2_input7, in2_input6, in2_input5, in2_input4, in2_input3, in2_input2, in2_input1, in2_input0)<=sum(aux6_input7, aux6_input6, aux6_input5, aux6_input4, aux6_input3, aux6_input2, aux6_input1, aux6_input0)) states: 52,532 (4)
abstracting: (sum(out1_input7, out1_input6, out1_input5, out1_input4, out1_input3, out1_input2, out1_input1, out1_input0)<=sum(aux16_input7, aux16_input6, aux16_input5, aux16_input4, aux16_input3, aux16_input2, aux16_input1, aux16_input0)) states: 33,849 (4)

EG iterations: 0
-> the formula is FALSE

FORMULA PermAdmissibility-COL-01-CTLCardinality-2 FALSE TECHNIQUES SEQUENTIAL_PROCESSING DECISION_DIAGRAMS UNFOLDING_TO_PT

MC time: 0m41.139sec


Total processing time: 4m 4.669sec


BK_STOP 1464972676674

--------------------
content from stderr:

check for maximal unmarked siphon
found
The net has a maximal unmarked siphon:
aux5_input2
aux7_input1
aux7_input0
aux6_input7
aux6_input6
aux6_input3
aux5_input7
aux5_input6
aux5_input3
aux6_input2
aux8_input4
aux8_input5
aux8_input0
aux8_input1
aux7_input4
aux7_input5
in1_input2
in1_input3
in1_input4
in1_input5
in1_input6
in1_input7
in2_input0
in2_input1
in2_input4
in2_input5
in2_input6
in2_input7
in3_input0
in3_input7
in4_input0
in4_input1
in4_input2
in4_input3
in4_input4
in4_input5
in3_input6
in3_input1
in3_input2
in3_input3

The net has transition(s) that can never fire:
switch1_0_2
switch5_0_5
switch1_0_3
switch1_0_6
switch1_0_7
switch1_1_0
switch1_1_1
switch1_1_2
switch1_1_3
switch3_3_0
switch3_3_1
switch3_3_2
switch3_3_4
switch3_3_3
switch1_0_1
switch3_4_6
switch5_0_1
switch3_4_7
switch3_5_0
switch3_5_1
switch3_5_2
switch1_0_0
switch5_0_4
switch5_1_0
switch5_1_1
switch5_2_1
switch5_1_4
switch5_1_5
switch5_2_0
switch5_4_1
switch5_2_2
switch5_2_3
switch5_2_4
switch5_2_5
switch1_1_6
switch1_1_7
switch1_2_0
switch1_2_1
switch1_2_2
switch1_2_3
switch1_2_4
switch1_2_5
switch1_2_6
switch1_2_7
switch1_3_0
switch1_3_1
switch1_3_2
switch1_3_3
switch1_3_4
switch1_3_5
switch1_3_6
switch1_3_7
switch1_4_0
switch1_4_1
switch1_4_2
switch1_4_3
switch1_4_5
switch1_4_4
switch1_4_6
switch1_4_7
switch1_5_0
switch1_5_1
switch1_5_2
switch1_5_3
switch1_5_4
switch1_5_5
switch1_5_6
switch1_5_7
switch1_6_0
switch1_6_1
switch1_6_2
switch1_6_3
switch1_6_4
switch1_6_5
switch1_6_6
switch1_6_7
switch1_7_0
switch1_7_1
switch1_7_2
switch1_7_3
switch1_7_4
switch1_7_5
switch1_7_6
switch1_7_7
switch3_0_0
switch3_0_1
switch3_0_2
switch3_0_3
switch3_0_5
switch3_0_4
switch3_0_6
switch3_0_7
switch3_1_0
switch3_1_1
switch3_1_2
switch3_1_3
switch3_1_4
switch3_1_5
switch3_1_6
switch3_1_7
switch3_2_0
switch3_2_1
switch3_2_2
switch3_2_3
switch3_2_4
switch3_2_5
switch6_5_5
switch6_6_0
switch6_6_1
switch6_6_2
switch6_6_3
switch6_6_4
switch6_6_5
switch6_6_6
switch6_6_7
switch3_3_5
switch3_4_0
switch3_4_1
switch3_4_2
switch3_4_3
switch3_4_5
switch3_4_4
switch7_2_1
switch7_1_4
switch7_1_5
switch7_2_0
switch7_4_1
switch7_2_2
switch7_2_3
switch7_2_5
switch7_2_4
switch3_5_3
switch3_5_4
switch3_5_5
switch3_5_6
switch3_5_7
switch3_6_0
switch3_6_1
switch3_6_2
switch3_6_3
switch3_6_4
switch3_6_5
switch3_6_6
switch3_6_7
switch3_7_0
switch3_7_1
switch3_7_2
switch3_7_3
switch3_7_4
switch3_7_5
switch3_7_6
switch3_7_7
switch2_0_0
switch2_0_1
switch2_0_2
switch2_0_3
switch2_0_6
switch2_0_7
switch2_1_0
switch2_1_1
switch2_1_2
switch2_1_3
switch2_1_6
switch2_1_7
switch2_2_0
switch2_2_1
switch2_2_2
switch2_2_3
switch2_2_4
switch2_2_5
switch2_2_6
switch2_2_7
switch2_3_0
switch2_3_1
switch2_3_2
switch2_3_3
switch2_3_4
switch2_3_5
switch2_3_6
switch2_3_7
switch2_4_0
switch2_4_1
switch2_4_2
switch2_4_3
switch2_4_4
switch2_4_5
switch2_4_6
switch2_4_7
switch2_5_0
switch2_5_1
switch2_5_2
switch2_5_3
switch2_5_4
switch2_5_5
switch2_5_6
switch2_5_7
switch2_6_0
switch2_6_1
switch2_6_2
switch2_6_3
switch2_6_4
switch2_6_5
switch2_6_6
switch2_6_7
switch2_7_0
switch2_7_1
switch2_7_2
switch2_7_3
switch2_7_4
switch2_7_5
switch2_7_6
switch2_7_7
switch4_0_0
switch4_0_1
switch4_0_2
switch4_0_3
switch4_0_5
switch4_0_4
switch4_0_6
switch4_0_7
switch4_1_0
switch4_1_1
switch4_1_2
switch4_1_3
switch4_1_4
switch4_1_5
switch4_1_6
switch4_1_7
switch4_2_0
switch4_2_1
switch4_2_2
switch4_2_3
switch4_2_4
switch4_2_5
switch4_3_0
switch4_3_1
switch4_3_2
switch4_3_3
switch4_3_4
switch4_3_5
switch4_4_0
switch4_4_1
switch4_4_2
switch4_4_3
switch4_4_4
switch4_4_5
switch4_4_6
switch4_4_7
switch4_5_0
switch4_5_1
switch4_5_2
switch4_5_3
switch4_5_4
switch4_5_5
switch4_5_6
switch4_5_7
switch4_6_0
switch4_6_1
switch4_6_2
switch4_6_3
switch4_6_4
switch4_6_5
switch4_6_6
switch4_6_7
switch4_7_0
switch4_7_1
switch4_7_2
switch4_7_3
switch4_7_4
switch4_7_5
switch4_7_6
switch4_7_7
switch5_0_0
switch5_2_6
switch5_2_7
switch5_3_0
switch5_3_1
switch5_3_2
switch5_3_3
switch5_3_4
switch5_3_5
switch5_3_6
switch5_3_7
switch5_4_0
switch5_4_5
switch5_4_4
switch7_1_1
switch5_5_0
switch5_5_1
switch5_5_4
switch5_5_5
switch5_6_0
switch5_6_1
switch5_6_2
switch5_6_3
switch5_6_4
switch5_6_5
switch5_6_6
switch5_6_7
switch5_7_0
switch5_7_1
switch5_7_2
switch5_7_3
switch5_7_4
switch5_7_5
switch5_7_6
switch5_7_7
switch8_0_0
switch8_0_1
switch8_0_5
switch8_0_4
switch8_1_0
switch8_1_1
switch8_2_1
switch8_1_4
switch8_1_5
switch8_2_0
switch8_4_1
switch8_2_2
switch8_2_3
switch8_2_4
switch8_2_5
switch8_2_6
switch8_2_7
switch8_3_0
switch8_3_1
switch8_3_2
switch8_3_3
switch8_3_4
switch8_3_5
switch8_3_6
switch8_3_7
switch8_4_0
switch8_4_5
switch8_4_4
switch8_5_0
switch8_5_1
switch8_5_4
switch8_5_5
switch8_6_0
switch8_6_1
switch8_6_2
switch8_6_3
switch8_6_4
switch8_6_5
switch8_6_6
switch8_6_7
switch8_7_0
switch8_7_1
switch8_7_2
switch8_7_3
switch8_7_4
switch8_7_5
switch8_7_6
switch8_7_7
switch6_0_0
switch6_0_1
switch6_0_5
switch6_0_4
switch6_1_0
switch6_1_1
switch6_2_1
switch6_1_4
switch6_1_5
switch6_2_0
switch6_4_1
switch6_2_2
switch6_2_3
switch6_2_4
switch6_2_5
switch6_2_6
switch6_2_7
switch6_3_0
switch6_3_1
switch6_3_2
switch6_3_3
switch6_3_4
switch6_3_5
switch6_3_6
switch6_3_7
switch6_4_0
switch6_4_4
switch6_4_5
switch6_5_0
switch6_5_1
switch6_5_4
switch6_7_0
switch6_7_1
switch6_7_2
switch6_7_3
switch6_7_4
switch6_7_5
switch6_7_6
switch6_7_7
switch7_0_0
switch7_0_1
switch7_0_5
switch7_0_4
switch7_1_0
switch7_2_6
switch7_2_7
switch7_3_0
switch7_3_1
switch7_3_2
switch7_3_3
switch7_3_4
switch7_3_5
switch7_3_6
switch7_3_7
switch7_4_0
switch7_4_4
switch7_4_5
switch7_5_0
switch7_5_1
switch7_5_4
switch7_5_5
switch7_6_0
switch7_6_1
switch7_6_2
switch7_6_3
switch7_6_4
switch7_6_5
switch7_6_6
switch7_6_7
switch7_7_0
switch7_7_1
switch7_7_2
switch7_7_3
switch7_7_4
switch7_7_5
switch7_7_6
switch7_7_7

check if there are places and transitions
ok
check if there are transitions without pre-places
ok
check if at least one transition is enabled in m0
ok
check if there are transitions that can never fire
ok


initing FirstDep: 0m 0.004sec

414 665 834 934 1014 1129 1205 1252 1256 1239 1254 1267 1277 1374 1422 1466 1477 2354 3081 3273 3444 3822 4279 4749 4783 4892 4919 4970 4996 5508 5812 5983 6264 6497 6579 6697 6749 6876 7000 7010 7523 7813 7958 8163 8152 8376 8395 8532 8685 8622 8702 8816 8886 8719 9453 9909 10157 10684 10532 10699 11179 11029 11151 10952 11445 11797 11641 11287 11678 11923 11553 12053 12162 11863 11942 12368 12615 12546 12295 12325 12365 12442 12569 12704 12822 12871 13104 13357 13566 13686 13692 13826 14090 14177 14294 14404 14509 14578 14612 14697 14854 14978 15105 15195 15250 15322 15378 15615 15662 15790 15906 15995 16071 16123 16168 16312 16435 16585 16685 16742 16814 16872 17057 17183 17287 17378 17478 17553 17592 17697 17754 17852 17975 18075 18129 18202 18256 18466 18508 18606 18721 18806 18887 18943 18997 19040 19142 19275 19385 19434 19514 19570 19727 19791 19825 19912 19975 20008 20039 20106 20201 20280 20384 20409 20471 20516 20549 20632 20675 20735 20783 20789 20884 21003 21063 21106 21133 21231 21275 21339 21375 21408 21476 21638 21724 21741 21792 21884 21959 22037 22113 22160 22184 22243 22288 22370 22442 22496 22648 22726 22754 22785 22881 22933 23026 23092 23125 23137 23173 23226 23299 23361 23435 23560 23667 23669 23711 23768 23801 23830 23885 23923 23914 23953 23975 24017 24049 24089 24184 24220 24234 24273 24333 24354 24399 24417 24453 24444 24470 24507 24553 24585 24627 24694 24745 24763 24788 24821 24862 24875 24877 24907 24932 25035 25097 25143 25150 25172 25193 25254 25305 25336 25350 25357 25373 25384 25433 25480 25551 25582 25580 25589 25619 25639 25647 25645 25656 25683 25691 25817 25886 25944 25953 26004 26043 26084 26137 26199 26241 26241 26301 26330 26376 26414 26502 26553 26611 26622 26664 26705 26743 26782 26806 26876 26876 26914 26967 27006 27037 27119 27133 27145 27164 27178 27209 27219 27229 27237 27250 27309 27381 27395 27433 27454 27482 27506 27577 27624 27647 27679 27699 27717 27726 27751 27864 27922 27936 27939 27976 28017 28043 28042 28042 28063 28139 28186 28202 28230 28230 28272 28303 28303 28326 28326 28336 28418 28485 28510 28532 28551 28574 28639 28653 28663 28677 28734 28796 28844 28851 28877 28909 28953 28996 29002 29021 29077 29109 29147 29196 29224 29252 29276 29332 29382 29388 29427 29456 29453 29478 29508 29535 29613 29664 29711 29734 29738 29756 29792 29840 29840 29889 29912 29906 29908 29937 29940 30000 30015 30027 30032 30047 30069 30063 30077 30082 30085 30138 30205 30228 30287 30310 30314 30334 30375 30406 30438 30483 30513 30516 30513 30531 30581 30646 30669 30692 30694 30697 30714 30747 30773 30787 30804 30807 30815 30804 30822 33043 34026 34117 35671 35874 37834 38425 39465 40142 40567 41356 41597 41981 42208 42521 42878 43007 43594 43697 45498 48273 49516 51102 51738 52371 52793 53492 53716 54002 54169 54431 54618 54763 55090 55132 55327 55398 55486 55556 55615 55694
iterations count:487864 (476), effective:1864 (1)

initing FirstDep: 0m 0.005sec

55694
iterations count:1024 (1), effective:0 (0)
1079 1133 1234 1423 1472 1517 1477
iterations count:7440 (7), effective:39 (0)
46320 46336 46589 46776 46801 46854 46827 47120 47190 47099 47261 47322 47190 47124 49275 50163 51959 52014 53252 53495 54315 54425 55091 55176 55529 55593 55714 55694
iterations count:28256 (27), effective:116 (0)
3249 3418 3682 3822 3906 3949 4028 4096 4216 4298 4374 4370 4433 4480 4538 4561 4555 4588 4644 4731 4795 4842 4836 4857 4910 4921 4936 4945 4976 4980 5002 5011 5024 5031 5035 5051 5032 5047 5076 5123 5150 5172 5190 5228 5227 5342 5385 5427 5436 5448 5449 5461 5480 5505 5515 5515 5554 5553 5550 5553 5545 5543 5554 5546 5557 5547 5527 5522 5638 5795 5832 5851 5936 5952 6016 6117 6143 6197 6196 6216 6242 6250 6255 6220 6202 6250 6300 6318 6352 6331 6356 6369 6355 6362 6340 6348 6333 6343 6348 6330 6337 6338 6304 6305 6300 6306 6337 6351 6365 6345 6355 6356 6428 6502 6550 6556 6512 6465 6467 6488 6493 6494 6495 6496 6483 6449 6451 6428 6430 6393 6390 6386 6386 6327 6310 6594 6717 6748 6790 6838 6859 6915 6953 6948 7063 7093 7149 7217 7249 7287 7298 7270 7440 7512 7545 7612 7621 7635 7676 7715 7720 7775 7809 7872 7879 7880 7918 7923 7904 8007 8159 8181 8192 8208 8218 8245 8257 8248 8240 8360 8433 8464 8486 8461 8474 8470 8460 8462 8469 8537 8609 8624 8628 8644 8649 8663 8651 8639 8666 8766 8782 8808 8770 8772 8774 8755 8746 8908 9010 9036 9076 9117 9141 9145 9146 9163 9224 9265 9295 9334 9357 9344 9422 9398 9509 9566 9594 9640 9635 9654 9647 9625 9656 9677 9676 9711 9715 9729 9729 9774 9745 9858 9979 10008 10007 10034 10060 10058 10055 10061 10051 10165 10215 10188 10215 10235 10228 10240 10239 10239 10246 10312 10365 10379 10401 10400 10408 10411 10399 10367 10389 10470 10452 10458 10457 10450 10432 10432 10429 10703 10726 10765 10776 10762 10798 10765 10755 10763 10761 10803 10774 10785 10819 10786 10776 10875 10938 10974 10990 10987 11010 11050 11089 11125 11124 11161 11171 11191 11201 11214 11226 11209 11275 11333 11376 11388 11380 11399 11424 11439 11456 11456 11470 11468 11476 11465 11485 11471 11443 11590 11649 11644 11645 11657 11667 11677 11708 11691 11677 11721 11792 11874 11904 11913 11916 11934 11945 12015 12094 12104 12123 12143 12167 12175 12175 12179 12163 12167 12164 12174 12273 12294 12306 12314 12320 12329 12338 12429 12436 12439 12441 12459 12458 12458 12457 12429 12437 12425 12422 12469 12473 12470 12470 12464 12473 12485 12522 12509 12584 12608 12606 12580 12600 12623 12620 12602 12603 12581 12562 12551 12607 12601 12598 12589 12585 12560 12550 12547 12517 12521 12642 12708 12756 12794 12825 12835 12848 12861 12894 12920 12940 12982 13002 13021 13017 13017 13018 13120 13123 13117 13124 13115 13201 13208 13207 13184 13180 13182 13168 13157 13146 13118 13156 13269 13301 13326 13344 13327 13338 13336 13324 13334 13348 13402 13434 13442 13424 13429 13431 13428 13417 13414 13422 13461 13458 13468 13471 13522 13518 13505 13500 13498 13482 13444 13441 13415 13520 13521 13601 13647 13672 13731 13754 13755 13809 13815 13820 13859 13883 13899 13936 13940 13946 13964 13976 14044 14045 14049 14038 14004 14007 14025 14086 14158 14228 14201 14225 14248 14268 14274 14284 14281 14287 14346 14389 14354 14362 14366 14383 14382 14385 14370 14380 14428 14429 14424 14429 14420 14421 14488 14501 14478 14468 14467 14424 14391 14374 14529 14530 14532 14484 14462 14453 14435 14391 14342 14344 14432 14489 14586 14732 14784 14791 14802 14805 14874 14917 14918
iterations count:558361 (545), effective:1777 (1)
51200 51303 51399 51409 51449 51514 51530 51497 51539 51596 51545 51541 51623 51564 51566 51568 51668 51696 51788 51728 51731 51748 51811 51763 51761 51795 51786 51812 51812 51805 51801 52041 52125 52144 52236 52275 52454 52534 52583 52654 52658 52880 52915 52972 53025 53131 53190 53222 53326 53329 53468 53498 53535 53573 53604 53701 53720 53764 53775 53923 53958 53956 54103 54137 54189 54209 54261 54349 54345 54420 54415 54499 54538 54536 54616 54630 54651 54655 54695 54713 54729 54726 54730 54831 54853 54903 54888 54931 54940 54924 54950 54952 54963 54966 55015 55023 55040 55040 55055 55073 55062 55056 55053 55012 55008 55114 55116 55128 55206 55209 55364 55364 55274 55273 55227 55322 55339 55383 55412 55412 55474 55568 55560 55560 55554 55600 55606 55667 55675 55681 55730 55746 55703 55676 55602 55631 55639 55680 55685 55696 55721 55714 55717 55711 55710 55824 55702 55742 55694
iterations count:149208 (145), effective:456 (0)
51200 51303 51399 51409 51449 51514 51530 51497 51539 51596 51545 51541 51623 51564 51566 51568 51668 51696 51788 51728 51731 51748 51811 51763 51761 51795 51786 51812 51812 51805 51801 52041 52125 52144 52236 52275 52454 52534 52583 52654 52658 52880 52915 52972 53025 53131 53190 53222 53326 53329 53468 53498 53535 53573 53604 53701 53720 53764 53775 53923 53958 53956 54103 54137 54189 54209 54261 54349 54345 54420 54415 54499 54538 54536 54616 54630 54651 54655 54695 54713 54729 54726 54730 54831 54853 54903 54888 54931 54940 54924 54950 54952 54963 54966 55015 55023 55040 55040 55055 55073 55062 55056 55053 55012 55008 55114 55116 55128 55206 55209 55364 55364 55274 55273 55227 55322 55339 55383 55412 55412 55474 55568 55560 55560 55554 55600 55606 55667 55675 55681 55730 55746 55703 55676 55602 55631 55639 55680 55685 55696 55721 55714 55717 55711 55710 55824 55702 55742 55694
iterations count:149208 (145), effective:456 (0)
51200 51303 51399 51409 51449 51514 51530 51497 51539 51596 51545 51541 51623 51564 51566 51568 51668 51696 51788 51728 51731 51748 51811 51763 51761 51795 51786 51812 51812 51805 51801 52041 52125 52144 52236 52275 52454 52534 52583 52654 52658 52880 52915 52972 53025 53131 53190 53222 53326 53329 53468 53498 53535 53573 53604 53701 53720 53764 53775 53923 53958 53956 54103 54137 54189 54209 54261 54349 54345 54420 54415 54499 54538 54536 54616 54630 54651 54655 54695 54713 54729 54726 54730 54831 54853 54903 54888 54931 54940 54924 54950 54952 54963 54966 55015 55023 55040 55040 55055 55073 55062 55056 55053 55012 55008 55114 55116 55128 55206 55209 55364 55364 55274 55273 55227 55322 55339 55383 55412 55412 55474 55568 55560 55560 55554 55600 55606 55667 55675 55681 55730 55746 55703 55676 55602 55631 55639 55680 55685 55696 55721 55714 55717 55711 55710 55824 55702 55742 55694
iterations count:149208 (145), effective:456 (0)
18800
iterations count:1024 (1), effective:0 (0)
3867
iterations count:1457 (1), effective:5 (0)
52612 52812 52904 53133 53195 53188 53390 53591 53643 53581 53716 53717 53654 54110 54175 54261 54349 54311 54230 54886 55200 55276 55319 55246 55249 55057 55107 55239 55710 55694
iterations count:30484 (29), effective:137 (0)
37897 38128 38236 38274 38418 38482 38466 38642 38665 38668 38687 38730 38780 38877 38815 38838 38881 38808 38850 38907 38856 38852 38963 38991 38932 38917 38919 38984 39142 39114 39167 39279 39263 39251 39343 39399 39336 39355 39370 39364 39465 39369 39382 39454 39352 39376 39423 39367 39358 39464 39517 39467 39381 39377 39579 39703 39746 39806 39880 40021 40112 40151 40236 40264 40490 40571 40642 40643 40755 40835 40838 41016 41064 41042 41117 41166 41155 41277 41320 41350 41400 41431 41528 41547 41584 41607 41633 41785 41826 41930 42036 42051 42071 42171 42224 42228 42325 42372 42337 42389 42427 42390 42400 42513 42511 42594 42593 42620 42622 42641 42692 42688 42707 42705 42711 42850 42841 42842 42870 42895 42879 42957 42984 43016 43039 43106 43116 43145 43129 43137 43111 43103 43041 43055 43107 43098 43056 43053 43053 43041 43114 43110 43128 43206 43209 43325 43364 43287 43273 43227 43322 43397 43428 43479 43458 43425 43425 43530 43581 43573 43573 43567 43613 43609 43680 43694 43694 43743 43759 43759 43689 43615 43718 43740 43750 43789 43759 43713 43724 43749 43742 43745 43739 43738 43852 43722 43770 43722
iterations count:188288 (183), effective:625 (0)
445
iterations count:1630 (1), effective:6 (0)
30471 30877 31159 31412 31548 31716 31682 31661 31721 32186 32384 32597 32649 32753 32790 32883 32966 33078 33166 33159 33190 33258 33294 33352 33379 33377 33397 33508 33582 33640 33627 33659 33704 33723 33738 33771 33768 33780 33799 33805 33849 33835 33836 33847 33848 33843 33853 33927 33943 33966 33994 34006 34027 34090 34180 34197 34239 34240 34250 34255 34277 34314 34321 34329 34343 34352 34357 34367 34346 34352 34348 34355 34361 34361 34350 34332 34384 34468 34634 34653 34753 34746 34770 34849 34951 34959 34994 35011 35029 35067 35041 35019 35002 35011 35064 35128 35142 35160 35145 35163 35183 35165 35168 35144 35147 35142 35149 35172 35136 35143 35104 35109 35097 35114 35122 35142 35161 35183 35151 35165 35219 35275 35321 35354 35313 35329 35269 35280 35296 35302 35289 35294 35298 35296 35253 35239 35232 35197 35191 35194 35190 35137 35118 35108 35428 35540 35597 35636 35658 35688 35719 35744 35780 35887 35938 36006 36026 36076 36090 36102 36219 36261 36335 36376 36406 36432 36463 36519 36508 36525 36594 36627 36673 36701 36724 36725 36724 36756 36878 36979 36996 37001 37043 37046 37060 37045 37043 37119 37230 37263 37282 37251 37276 37284 37271 37266 37269 37293 37409 37425 37432 37441 37456 37463 37461 37461 37450 37545 37579 37594 37569 37574 37572 37561 37545 37546 37743 37814 37864 37905 37921 37957 37950 37949 37994 38041 38077 38122 38149 38156 38192 38230 38286 38329 38386 38425 38449 38458 38470 38451 38441 38464 38475 38500 38529 38526 38512 38573 38565 38606 38730 38799 38814 38831 38856 38865 38869 38863 38852 38922 39008 39032 39014 39037 39032 39032 39036 39038 39045 39071 39166 39181 39193 39205 39211 39215 39203 39191 39181 39235 39297 39256 39265 39261 39244 39244 39240 39236 39535 39573 39577 39551 39566 39600 39582 39565 39569 39606 39592 39585 39589 39621 39567 39582 39708 39750 39794 39803 39809 39843 39873 39905 39925 39946 39975 39974 39995 40008 40043 40014 40079 40122 40150 40183 40192 40181 40228 40238 40261 40265 40285 40284 40261 40278 40258 40276 40247 40368 40418 40452 40452 40441 40459 40481 40508 40498 40495 40476 40577 40633 40698 40710 40717 40723 40743 40808 40862 40909 40908 40939 40953 40978 40982 40983 40962 40962 40971 40972 41032 41077 41110 41118 41121 41132 41138 41197 41233 41243 41243 41253 41269 41257 41255 41247 41237 41235 41223 41232 41278 41274 41274 41274 41268 41283 41324 41319 41300 41388 41421 41413 41393 41424 41423 41411 41407 41407 41370 41355 41373 41401 41408 41391 41392 41386 41360 41354 41333 41329 41424 41493 41525 41577 41624 41630 41658 41665 41649 41717 41738 41772 41796 41818 41812 41827 41823 41806 41926 41932 41926 41906 41978 42003 42002 42000 41991 41993 41969 41961 41961 41927 41909 42015 42097 42119 42128 42115 42140 42148 42131 42136 42143 42172 42230 42241 42261 42229 42235 42242 42226 42222 42222 42237 42261 42271 42275 42291 42317 42306 42302 42308 42290 42248 42246 42227 42217 42324 42404 42426 42480 42504 42539 42568 42593 42613 42620 42662 42681 42688 42730 42756 42753 42782 42774 42766 42849 42855 42839 42809 42817 42815 42833 42945 43032 43045 43023 43044 43062 43080 43083 43080 43085 43109 43185 43198 43161 43164 43186 43188 43184 43182 43179 43195 43231 43235 43228 43230 43233 43288 43305 43285 43282 43275 43276 43214 43178 43264 43333 43337 43324 43268 43256 43253 43197 43178 43148 43149 43236 43390 43465 43536 43595 43601 43606 43678 43720 43722
iterations count:566844 (553), effective:1818 (1)

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_PermAdmissibility-COL-01"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="marcie"
export BK_RESULT_DIR="/root/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_PermAdmissibility-COL-01.tgz
mv S_PermAdmissibility-COL-01 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-2979"
echo " Executing tool marcie"
echo " Input is S_PermAdmissibility-COL-01, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 1"
echo " Run identifier is r185kn-smll-146444131201218"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;