Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-2979
Executing tool itstools
Input is S_SharedMemory-PT-000005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r181kn-smll-146444111800751
=====================================================================

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-0
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-1
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-10
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-11
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-12
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-13
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-14
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-15
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-2
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-3
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-4
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-5
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-6
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-7
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-8
FORMULA_NAME SharedMemory-COL-000005-CTLFireability-9

=== Now, execution of the tool begins

BK_START 1464623815587


its-ctl command run as :

/home/mcc/BenchKit/eclipse/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201605191313/bin/its-ctl-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/CTLFireability.gal -t CGAL -ctl /home/mcc/execution/CTLFireability.ctl
No direction supplied, using forward translation only.
Parsed 16 CTL formulae.
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
reachable,1863,0.02687,5028,2,593,5,1830,6,0,222,1126,0


Converting to forward existential form...Done !
original formula: EF(AG(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U !(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))] != FALSE
Checking (exact) 0 :[(FwdU(Init,TRUE) * !(E(TRUE U !(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))] != FALSE
Checking (exact) 0 :(FwdU(Init,TRUE) * !(E(TRUE U !(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))
Checking (exact) 1 :!(E(TRUE U !(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))
Checking (exact) 1 :E(TRUE U !(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))
Checking (exact) 1 :!(EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))
Checking (exact) 1 :EX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))
(forward)formula 0,0,0.127709,7884,1,0,8,20112,37,1,1103,7983,6
FORMULA SharedMemory-COL-000005-CTLFireability-0 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: E(AF((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1))) U AG(!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))
=> equivalent forward existential formula: [(FwdU(Init,!(EG(!((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * !(E(TRUE U !(!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))))] != FALSE
Checking (exact) 0 :[(FwdU(Init,!(EG(!((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * !(E(TRUE U !(!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))))] != FALSE
Checking (exact) 0 :(FwdU(Init,!(EG(!((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * !(E(TRUE U !(!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))))
Checking (exact) 1 :!(E(TRUE U !(!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))))
Checking (exact) 1 :E(TRUE U !(!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))
(forward)formula 1,0,0.135008,8152,1,0,9,20173,76,1,1140,7997,9
FORMULA SharedMemory-COL-000005-CTLFireability-1 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: AG(((EF(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))) + ((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))) * AF((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))
=> equivalent forward existential formula: ([((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))) * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))] = FALSE * [FwdG((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))] = FALSE)
Checking (exact) 0 :([((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))) * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))] = FALSE * [FwdG((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))] = FALSE)
Checking (exact) 1 :[FwdG((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))] = FALSE
Checking (exact) 0 :FwdG((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))
Checking (exact) 1 :(FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))
Checking (exact) 1 :!((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
Checking (exact) 1 :(E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))
Checking (exact) 1 :E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))
Checking (exact) 1 :[((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))) * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))] = FALSE
Checking (exact) 0 :((FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))) * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))
Checking (exact) 1 :!((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))
Checking (exact) 1 :(FwdU(Init,TRUE) * !((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))
Checking (exact) 1 :!((E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
Checking (exact) 1 :(E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)) + !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))
Checking (exact) 1 :E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))
(forward)formula 2,1,0.189451,9636,1,0,14,24438,199,3,1417,12621,17
FORMULA SharedMemory-COL-000005-CTLFireability-2 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AG((EX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))) + !(((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))))
=> equivalent forward existential formula: [((FwdU(Init,TRUE) * !(!(((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))) * !(EX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))))] = FALSE
Checking (exact) 0 :[((FwdU(Init,TRUE) * !(!(((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))) * !(EX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))))] = FALSE
Checking (exact) 0 :((FwdU(Init,TRUE) * !(!(((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))) * !(EX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))))
Checking (exact) 1 :!(EX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))
Checking (exact) 1 :EX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))
(forward)formula 3,1,0.203388,9852,1,0,15,25268,200,3,1441,12981,19
FORMULA SharedMemory-COL-000005-CTLFireability-3 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: E(AX((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))) U AG((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
=> equivalent forward existential formula: [(FwdU(Init,!(EX(!((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))) * !(E(TRUE U !((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))))] != FALSE
Checking (exact) 0 :[(FwdU(Init,!(EX(!((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))) * !(E(TRUE U !((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))))] != FALSE
Checking (exact) 0 :(FwdU(Init,!(EX(!((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))) * !(E(TRUE U !((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))))
Checking (exact) 1 :!(E(TRUE U !((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))
Checking (exact) 1 :E(TRUE U !((((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
(forward)formula 4,0,0.251666,10228,1,0,16,25925,202,3,1452,13651,22
FORMULA SharedMemory-COL-000005-CTLFireability-4 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: E(A((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) U ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) U ((((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))) * AX((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))
=> equivalent forward existential formula: [((FwdU(Init,!((E(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) U (!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))) + EG(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * (((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))) * !(EX(!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))] != FALSE
Checking (exact) 0 :[((FwdU(Init,!((E(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) U (!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))) + EG(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * (((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))) * !(EX(!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))] != FALSE
Checking (exact) 0 :((FwdU(Init,!((E(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) U (!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))) + EG(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * (((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))) * !(EX(!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))
Checking (exact) 1 :!(EX(!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))
Checking (exact) 1 :EX(!((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))
Checking (exact) 1 :(FwdU(Init,!((E(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) U (!((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))) + EG(!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))))) * (((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))
Checking (exact) 1 :(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1) * !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))
Checking (exact) 1 :!(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))
(forward)formula 5,0,0.278596,10488,1,0,19,31435,205,6,1454,18033,23
FORMULA SharedMemory-COL-000005-CTLFireability-5 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EF(AX((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))] != FALSE
Checking (exact) 0 :[(FwdU(Init,TRUE) * !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))] != FALSE
Checking (exact) 0 :(FwdU(Init,TRUE) * !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))
Checking (exact) 1 :!(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
Checking (exact) 1 :EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))
Checking (exact) 1 :FwdU(Init,TRUE)
Checking (exact) 1 :Init
(forward)formula 6,1,0.297399,10564,1,0,21,32210,205,8,1454,19265,24
FORMULA SharedMemory-COL-000005-CTLFireability-6 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AF(EF(AX((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
=> equivalent forward existential formula: [FwdG(Init,!(E(TRUE U !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))))] = FALSE
Checking (exact) 0 :[FwdG(Init,!(E(TRUE U !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))))] = FALSE
Checking (exact) 0 :FwdG(Init,!(E(TRUE U !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))))
Checking (exact) 1 :Init
Checking (exact) 1 :!(E(TRUE U !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))))
Checking (exact) 1 :E(TRUE U !(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))
Checking (exact) 1 :!(EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
Checking (exact) 1 :EX(!((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))
(forward)formula 7,1,0.322375,10740,1,0,21,32362,208,8,1454,19381,26
FORMULA SharedMemory-COL-000005-CTLFireability-7 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: (((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))) + AG((((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))) * EF((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))
=> equivalent forward existential formula: ([(FwdU((Init * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),TRUE) * !((((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))] = FALSE * [(Init * !(E(TRUE U (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))] = FALSE)
Checking (exact) 0 :([(FwdU((Init * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),TRUE) * !((((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))] = FALSE * [(Init * !(E(TRUE U (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))] = FALSE)
Checking (exact) 1 :[(Init * !(E(TRUE U (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))] = FALSE
Checking (exact) 0 :(Init * !(E(TRUE U (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))
Checking (exact) 1 :!(E(TRUE U (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))
Checking (exact) 1 :E(TRUE U (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))
Checking (exact) 1 :[(FwdU((Init * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),TRUE) * !((((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))] = FALSE
Checking (exact) 0 :(FwdU((Init * !((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) + (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))),TRUE) * !((((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)) + ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)) + !(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))))
(forward)formula 8,1,0.334383,10740,1,0,21,32455,210,8,1456,19403,26
FORMULA SharedMemory-COL-000005-CTLFireability-8 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

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original formula: AG(EF(((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))] = FALSE
Checking (exact) 0 :[(FwdU(Init,TRUE) * !(E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))] = FALSE
Checking (exact) 0 :(FwdU(Init,TRUE) * !(E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))))
Checking (exact) 1 :!(E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1)))
Checking (exact) 1 :E(TRUE U ((((Active_2>=1 + Active_1>=1) + Active_4>=1) + Active_3>=1) + Active_5>=1))
(forward)formula 9,1,0.335749,10800,1,0,21,32455,210,8,1456,19403,26
FORMULA SharedMemory-COL-000005-CTLFireability-9 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: EF(AX(AG((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(EX(!(!(E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))))] != FALSE
Checking (exact) 0 :[(FwdU(Init,TRUE) * !(EX(!(!(E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))))] != FALSE
Checking (exact) 0 :(FwdU(Init,TRUE) * !(EX(!(!(E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))))
Checking (exact) 1 :!(EX(!(!(E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))))
Checking (exact) 1 :EX(!(!(E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))))
Checking (exact) 1 :!(!(E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))
Checking (exact) 1 :E(TRUE U !((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))
(forward)formula 10,0,0.340211,10884,1,0,21,32461,210,8,1456,19413,28
FORMULA SharedMemory-COL-000005-CTLFireability-10 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EF(AF((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) * (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))
=> equivalent forward existential formula: [(FwdU(Init,TRUE) * !(EG(!((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) * (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))))] != FALSE
Checking (exact) 0 :[(FwdU(Init,TRUE) * !(EG(!((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) * (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))))] != FALSE
Checking (exact) 0 :(FwdU(Init,TRUE) * !(EG(!((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) * (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))))
Checking (exact) 1 :!(EG(!((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) * (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1)))))
Checking (exact) 1 :EG(!((((((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) * (((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1))))
(forward)formula 11,0,0.366127,10888,1,0,21,32470,216,8,1502,19839,30
FORMULA SharedMemory-COL-000005-CTLFireability-11 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************

original formula: EF(EX((((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) + (((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))))
=> equivalent forward existential formula: [(EY(FwdU(Init,TRUE)) * (((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) + (((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))] != FALSE
Checking (exact) 0 :[(EY(FwdU(Init,TRUE)) * (((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) + (((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))] != FALSE
Checking (exact) 0 :(EY(FwdU(Init,TRUE)) * (((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) + (((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1)))))
Checking (exact) 1 :(((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) * (((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))) + ((((((((((((((((((((Ext_Mem_Acc_4_1>=1 + Ext_Mem_Acc_5_1>=1) + Ext_Mem_Acc_2_1>=1) + Ext_Mem_Acc_3_1>=1) + Ext_Mem_Acc_5_2>=1) + Ext_Mem_Acc_4_2>=1) + Ext_Mem_Acc_3_2>=1) + Ext_Mem_Acc_1_2>=1) + Ext_Mem_Acc_5_3>=1) + Ext_Mem_Acc_4_3>=1) + Ext_Mem_Acc_2_3>=1) + Ext_Mem_Acc_1_3>=1) + Ext_Mem_Acc_5_4>=1) + Ext_Mem_Acc_3_4>=1) + Ext_Mem_Acc_2_4>=1) + Ext_Mem_Acc_1_4>=1) + Ext_Mem_Acc_4_5>=1) + Ext_Mem_Acc_3_5>=1) + Ext_Mem_Acc_2_5>=1) + Ext_Mem_Acc_1_5>=1) + (((((OwnMemAcc_5>=1 * Memory_5>=1) + (OwnMemAcc_4>=1 * Memory_4>=1)) + (OwnMemAcc_1>=1 * Memory_1>=1)) + (OwnMemAcc_3>=1 * Memory_3>=1)) + (OwnMemAcc_2>=1 * Memory_2>=1))))
Checking (exact) 1 :EY(FwdU(Init,TRUE))
Checking (exact) 1 :FwdU(Init,TRUE)
Checking (exact) 1 :Init
(forward)formula 12,1,0.393129,10888,1,0,23,32575,220,9,1543,20099,33
FORMULA SharedMemory-COL-000005-CTLFireability-12 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)
=> equivalent forward existential formula: [(Init * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1))] != FALSE
Checking (exact) 0 :[(Init * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1))] != FALSE
Checking (exact) 0 :(Init * ((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1))
(forward)formula 13,1,0.39399,11116,1,0,24,32577,220,9,1543,20102,34
FORMULA SharedMemory-COL-000005-CTLFireability-13 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: !(AG(AG(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1))))
=> equivalent forward existential formula: [(FwdU(FwdU(Init,TRUE),TRUE) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))] != FALSE
Checking (exact) 0 :[(FwdU(FwdU(Init,TRUE),TRUE) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))] != FALSE
Checking (exact) 0 :(FwdU(FwdU(Init,TRUE),TRUE) * !(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1)))
Checking (exact) 1 :!(((((Active_2>=1 + Active_1>=1) + Active_5>=1) + Active_3>=1) + Active_4>=1))
Checking (exact) 1 :FwdU(FwdU(Init,TRUE),TRUE)
Checking (exact) 1 :FwdU(Init,TRUE)
Checking (exact) 1 :Init
(forward)formula 14,1,0.39761,11172,1,0,25,32577,221,10,1590,20537,36
FORMULA SharedMemory-COL-000005-CTLFireability-14 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is TRUE !

***************************************

original formula: AX(EG(AG((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
=> equivalent forward existential formula: [(EY(Init) * !(EG(!(E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))))] = FALSE
Checking (exact) 0 :[(EY(Init) * !(EG(!(E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))))] = FALSE
Checking (exact) 0 :(EY(Init) * !(EG(!(E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))))
Checking (exact) 1 :!(EG(!(E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))))
Checking (exact) 1 :EG(!(E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))))
Checking (exact) 1 :!(E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1)))))
Checking (exact) 1 :E(TRUE U !((((((((((((((((((((((Ext_Bus>=1 * Memory_2>=1) * Queue_1>=1) + ((Ext_Bus>=1 * Queue_3>=1) * Memory_2>=1)) + ((Ext_Bus>=1 * Queue_4>=1) * Memory_2>=1)) + ((Queue_5>=1 * Memory_2>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_1>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_3>=1)) + ((Ext_Bus>=1 * Memory_1>=1) * Queue_4>=1)) + ((Memory_1>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_4>=1) * Queue_1>=1)) + ((Ext_Bus>=1 * Queue_2>=1) * Memory_4>=1)) + ((Queue_3>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Queue_5>=1 * Memory_4>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Queue_1>=1) * Memory_3>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_2>=1)) + ((Ext_Bus>=1 * Memory_3>=1) * Queue_4>=1)) + ((Memory_3>=1 * Queue_5>=1) * Ext_Bus>=1)) + ((Ext_Bus>=1 * Memory_5>=1) * Queue_2>=1)) + ((Queue_1>=1 * Memory_5>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_4>=1) * Ext_Bus>=1)) + ((Memory_5>=1 * Queue_3>=1) * Ext_Bus>=1))))
Fast SCC detection found none.
Checking (exact) 1 :EY(Init)
Checking (exact) 1 :Init
(forward)formula 15,0,0.423853,11216,1,0,26,32648,226,11,1592,20644,39
FORMULA SharedMemory-COL-000005-CTLFireability-15 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL
Formula is FALSE !

***************************************


BK_STOP 1464623820341

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ CTLFireability = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution CTLFireability -its
+ ulimit -s 65536
+ java -Dosgi.requiredJavaVersion=1.6 -XX:MaxPermSize=512m -Xss8m -Xms40m -Xmx8192m -Declipse.pde.launch=true -Dfile.encoding=UTF-8 -classpath /home/mcc/BenchKit//eclipse/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar org.eclipse.equinox.launcher.Main -application fr.lip6.move.gal.application.pnmcc -data /home/mcc/BenchKit//workspace -os linux -ws gtk -arch x86_64 -nl en_US -consoleLog -pnfolder /home/mcc/execution -examination CTLFireability -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its
Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=512m; support was removed in 8.0
May 30, 2016 3:56:58 PM fr.lip6.move.gal.application.Application transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
May 30, 2016 3:56:59 PM fr.lip6.move.gal.nupn.PTNetReader loadFromXML
INFO: Load time of PNML (sax parser for PT used): 54 ms
May 30, 2016 3:56:59 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 41 places.
May 30, 2016 3:56:59 PM fr.lip6.move.gal.pnml.togal.PTGALTransformer handlePage
INFO: Transformed 55 transitions.
May 30, 2016 3:56:59 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 53 ms
May 30, 2016 3:56:59 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/CTLFireability.gal : 15 ms
May 30, 2016 3:56:59 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSCTLTools
INFO: Time to serialize properties into /home/mcc/execution/CTLFireability.ctl : 7 ms

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="S_SharedMemory-PT-000005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/root/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

tar xzf /home/mcc/BenchKit/INPUTS/S_SharedMemory-PT-000005.tgz
mv S_SharedMemory-PT-000005 execution

# this is for BenchKit: explicit launching of the test

cd execution
echo "====================================================================="
echo " Generated by BenchKit 2-2979"
echo " Executing tool itstools"
echo " Input is S_SharedMemory-PT-000005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r181kn-smll-146444111800751"
echo "====================================================================="
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;