fond
Model Checking Contest 2022
12th edition, Bergen, Norway, June 21, 2022
Execution of r075-tall-165260107300634
Last Updated
Jun 22, 2022

About the Execution of Tapaal for FamilyReunion-COL-L00050M0005C002P002G001

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16181.104 3592840.00 13377675.00 1536.00 ?F???T???TT?T??F normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2022-input.r075-tall-165260107300634.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2022-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool tapaal
Input is FamilyReunion-COL-L00050M0005C002P002G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r075-tall-165260107300634
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 360K
-rw-r--r-- 1 mcc users 5.6K Apr 30 08:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 50K Apr 30 08:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Apr 30 08:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Apr 30 08:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 5 May 10 09:33 equiv_pt
-rw-r--r-- 1 mcc users 4.2K May 10 09:33 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 10 09:33 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 24 May 10 09:33 instance
-rw-r--r-- 1 mcc users 5 May 10 09:33 iscolored
-rw-r--r-- 1 mcc users 4.2K May 9 07:48 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 9 07:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K May 9 07:48 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 9 07:48 LTLFireability.xml
-rw-r--r-- 1 mcc users 137K May 10 09:33 model.pnml
-rw-r--r-- 1 mcc users 2.0K May 9 07:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 9 07:48 UpperBounds.xml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1652705196754

tapaal
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> tapaal --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e
MF=/home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-15
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-14
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-13
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-12
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-11
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-10
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-08
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-07
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-06
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-05
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-04
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-03
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-02
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-01
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-00

Unable to decide if FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-09 is satisfied.

Query is MAYBE satisfied.

Spent 0.002636 on verification
Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

Time left: 2873

---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (16 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved

Query is satisfied.

Spent 0.068026 on verification
@@@0.39,41092@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --binary-query-io 1 -x 1 -n

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT EXPLICIT STATE_COMPRESSION STUBBORN_SETS
Time left: 2872
------------------- QUERY 2 ----------------------
No solution found



Time left: 2570
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.140666 on verification
@@@0.49,77200@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --binary-query-io 1 -x 3 -n

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2570
------------------- QUERY 4 ----------------------
No solution found



Time left: 2268
------------------- QUERY 5 ----------------------
No solution found



Time left: 1966
------------------- QUERY 6 ----------------------
No solution found
Command terminated by signal 9
@@@158.26,4186256@@@
Command terminated by signal 9
@@@209.19,5678688@@@


Time left: 1664
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.078131 on verification


Query index 0 was solved
Query is satisfied.

Spent 0.064678 on verification
@@@0.51,76288@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --binary-query-io 1 -x 7 -n

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1663
------------------- QUERY 8 ----------------------
No solution found



Time left: 1361
------------------- QUERY 9 ----------------------
No solution found



Time left: 1060
------------------- QUERY 10 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 1.96965 on verification
@@@2.37,117356@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --binary-query-io 1 -x 10 -n

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1057
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.059488 on verification
@@@0.45,76992@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --binary-query-io 1 -x 11 -n

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 1056
------------------- QUERY 12 ----------------------
No solution found



Time left: 755
------------------- QUERY 13 ----------------------
No solution found



Time left: 453
------------------- QUERY 14 ----------------------
No solution found



Time left: 151
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.090095 on verification
@@@0.50,77296@@@


Query index 0 was solved
Query is NOT satisfied.

Spent 0.103124 on verification
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.Zhf3vDscsC /home/mcc/BenchKit/bin/tmp/tmp.abHeVIGC8e --binary-query-io 1 -x 15 -n

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 151
------------------- QUERY 16 ----------------------
No solution found



Time left: -3
Out of time, terminating!
terminated-with-cleanup

BK_STOP 1652708789594

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00050M0005C002P002G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaal"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool tapaal"
echo " Input is FamilyReunion-COL-L00050M0005C002P002G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r075-tall-165260107300634"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00050M0005C002P002G001.tgz
mv FamilyReunion-COL-L00050M0005C002P002G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;