Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2019-input.r196-smll-155246587200152.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2019-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-3957
Executing tool itstoolsm
Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r196-smll-155246587200152
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 208K
-rw-r--r-- 1 mcc users 4.0K Feb 11 22:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 11 22:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 7 23:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 7 23:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.0K Mar 10 17:31 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Mar 10 17:31 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 109 Feb 24 15:05 GlobalProperties.txt
-rw-r--r-- 1 mcc users 347 Feb 24 15:05 GlobalProperties.xml
-rw-r--r-- 1 mcc users 2.6K Feb 5 00:11 LTLCardinality.txt
-rw-r--r-- 1 mcc users 12K Feb 5 00:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 4 22:36 LTLFireability.txt
-rw-r--r-- 1 mcc users 8.7K Feb 4 22:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 4 06:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Feb 4 06:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K Jan 31 23:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 16K Jan 31 23:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 4 22:21 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 4 22:21 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 equiv_pt
-rw-r--r-- 1 mcc users 2 Jan 29 09:34 instance
-rw-r--r-- 1 mcc users 5 Jan 29 09:34 iscolored
-rw-r--r-- 1 mcc users 41K Mar 10 17:31 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-COL-5-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1553639942359

22:39:05.293 [main] ERROR PNML validation - The rng grammar file can't be accessed : www.pnml.org
22:39:05.296 [main] ERROR import - Grammar file errors have been raised, the validation can't be done, process will continue without Grammar validation
Working with output stream class java.io.PrintStream
Using solver Z3 to compute partial order matrices.
Built C files in :
/home/mcc/execution
Running greatSPN : CommandLine [args=[/home/mcc/BenchKit//greatspn//bin/pinvar, /home/mcc/execution/gspn], workingDir=/home/mcc/execution]
Run of greatSPN captured in /home/mcc/execution/outPut.txt
Running greatSPN : CommandLine [args=[/home/mcc/BenchKit//greatspn//bin/RGMEDD2, /home/mcc/execution/gspn, -META, -varord-only], workingDir=/home/mcc/execution]
Run of greatSPN captured in /home/mcc/execution/outPut.txt
Using order generated by GreatSPN with heuristic : META
Invoking ITS tools like this :CommandLine [args=[/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-reach-linux64, --gc-threshold, 2000000, --quiet, -i, /home/mcc/execution/ReachabilityCardinality.pnml.gal, -t, CGAL, -reachable-file, ReachabilityCardinality.prop, --nowitness, --load-order, /home/mcc/execution/model.ord], workingDir=/home/mcc/execution]

its-reach command run as :

/home/mcc/BenchKit/itstools/plugins/fr.lip6.move.gal.itstools.binaries_1.0.0.201903251645/bin/its-reach-linux64 --gc-threshold 2000000 --quiet -i /home/mcc/execution/ReachabilityCardinality.pnml.gal -t CGAL -reachable-file ReachabilityCardinality.prop --nowitness --load-order /home/mcc/execution/model.ord
Successfully loaded order from file /home/mcc/execution/model.ord
Loading property file ReachabilityCardinality.prop.
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-00 with value :((!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3))||(!(((((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5)>=2)&&((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-01 with value :(true)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-02 with value :((((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)>=3)&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=3)&&((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1)))&&(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5))||((((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-03 with value :((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-04 with value :(((((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)>=2)||((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)>=2))&&(((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5))||((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)>=1)))&&(((((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))&&(!((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=3))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-05 with value :((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)<=(((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-06 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=3)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-07 with value :((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-08 with value :(!((((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5))||((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((((((((((((((((((((((((((((((((wait_0+wait_1)+wait_2)+wait_3)+wait_4)+wait_5)+wait_6)+wait_7)+wait_8)+wait_9)+wait_10)+wait_11)+wait_12)+wait_13)+wait_14)+wait_15)+wait_16)+wait_17)+wait_18)+wait_19)+wait_20)+wait_21)+wait_22)+wait_23)+wait_24)+wait_25)+wait_26)+wait_27)+wait_28)+wait_29)+wait_30)+wait_31)+wait_32)+wait_33)+wait_34)+wait_35)))||(((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_setbi_24_0+P_setbi_24_1)+P_setbi_24_2)+P_setbi_24_3)+P_setbi_24_4)+P_setbi_24_5))&&((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=2))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-09 with value :(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)>=3)||((((((P_setbi_11_0+P_setbi_11_1)+P_setbi_11_2)+P_setbi_11_3)+P_setbi_11_4)+P_setbi_11_5)>=2))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-10 with value :(!((((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5))&&((((((y_0+y_1)+y_2)+y_3)+y_4)+y_5)>=3))&&(!((((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)>=3))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-11 with value :(((!((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5)))||(((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5))||((((((((((((b_0+b_1)+b_2)+b_3)+b_4)+b_5)+b_6)+b_7)+b_8)+b_9)+b_10)+b_11)>=2)))||(!((((((P_ifyi_15_0+P_ifyi_15_1)+P_ifyi_15_2)+P_ifyi_15_3)+P_ifyi_15_4)+P_ifyi_15_5)<=(((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-12 with value :(!((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)>=1))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-13 with value :((((((((((((((((((((((((((((((((((((((done_0+done_1)+done_2)+done_3)+done_4)+done_5)+done_6)+done_7)+done_8)+done_9)+done_10)+done_11)+done_12)+done_13)+done_14)+done_15)+done_16)+done_17)+done_18)+done_19)+done_20)+done_21)+done_22)+done_23)+done_24)+done_25)+done_26)+done_27)+done_28)+done_29)+done_30)+done_31)+done_32)+done_33)+done_34)+done_35)<=(((((P_ifxi_10_0+P_ifxi_10_1)+P_ifxi_10_2)+P_ifxi_10_3)+P_ifxi_10_4)+P_ifxi_10_5))||((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2))||(((((((P_setbi_5_0+P_setbi_5_1)+P_setbi_5_2)+P_setbi_5_3)+P_setbi_5_4)+P_setbi_5_5)>=2)&&((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))
Read [reachable] property : LamportFastMutEx-COL-5-ReachabilityCardinality-14 with value :(((((((((P_CS_21_0+P_CS_21_1)+P_CS_21_2)+P_CS_21_3)+P_CS_21_4)+P_CS_21_5)<=(((((P_sety_9_0+P_sety_9_1)+P_sety_9_2)+P_sety_9_3)+P_sety_9_4)+P_sety_9_5))&&((((((P_await_13_0+P_await_13_1)+P_await_13_2)+P_await_13_3)+P_await_13_4)+P_await_13_5)>=1))||(!((((((P_awaity_0+P_awaity_1)+P_awaity_2)+P_awaity_3)+P_awaity_4)+P_awaity_5)<=(((((P_start_1_0+P_start_1_1)+P_start_1_2)+P_start_1_3)+P_start_1_4)+P_start_1_5))))||(!(((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)<=(((((P_setx_3_0+P_setx_3_1)+P_setx_3_2)+P_setx_3_3)+P_setx_3_4)+P_setx_3_5))||((((((P_ify0_4_0+P_ify0_4_1)+P_ify0_4_2)+P_ify0_4_3)+P_ify0_4_4)+P_ify0_4_5)<=(((((x_0+x_1)+x_2)+x_3)+x_4)+x_5)))))
Read [invariant] property : LamportFastMutEx-COL-5-ReachabilityCardinality-15 with value :((((((P_fordo_12_0+P_fordo_12_1)+P_fordo_12_2)+P_fordo_12_3)+P_fordo_12_4)+P_fordo_12_5)<=(((((y_0+y_1)+y_2)+y_3)+y_4)+y_5))
Presburger conditions satisfied. Using coverability to approximate state space in K-Induction.
Normalized transition count is 246
// Phase 1: matrix 246 rows 174 cols
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-01 TRUE TECHNIQUES SAT_SMT TAUTOLOGY
invariant :P_start_1_1 + P_setx_3_1 + P_setbi_5_1 + P_ify0_4_1 + P_sety_9_1 + P_ifxi_10_1 + P_setbi_11_1 + P_fordo_12_1 + P_await_13_1 + P_ifyi_15_1 + P_awaity_1 + P_CS_21_1 + P_setbi_24_1 = 1
invariant :wait_11 + -1'P_await_13_1 + done_11 = 0
invariant :wait_6 + done_6 = 0
invariant :wait_9 + -1'P_await_13_1 + done_9 = 0
invariant :wait_13 + -1'P_await_13_2 + done_13 = 0
invariant :wait_35 + -1'P_await_13_5 + done_35 = 0
invariant :wait_23 + -1'P_await_13_3 + done_23 = 0
invariant :wait_5 + -1'P_await_13_0 + done_5 = 0
invariant :wait_25 + -1'P_await_13_4 + done_25 = 0
invariant :wait_31 + -1'P_await_13_5 + done_31 = 0
invariant :wait_10 + -1'P_await_13_1 + done_10 = 0
invariant :y_0 + y_1 + y_2 + y_3 + y_4 + y_5 = 1
invariant :b_2 + b_3 = 1
invariant :wait_16 + -1'P_await_13_2 + done_16 = 0
invariant :wait_20 + -1'P_await_13_3 + done_20 = 0
invariant :wait_26 + -1'P_await_13_4 + done_26 = 0
invariant :wait_29 + -1'P_await_13_4 + done_29 = 0
invariant :P_start_1_5 + P_setx_3_5 + P_setbi_5_5 + P_ify0_4_5 + P_sety_9_5 + P_ifxi_10_5 + P_setbi_11_5 + P_fordo_12_5 + P_await_13_5 + P_ifyi_15_5 + P_awaity_5 + P_CS_21_5 + P_setbi_24_5 = 1
invariant :wait_30 + done_30 = 0
invariant :wait_22 + -1'P_await_13_3 + done_22 = 0
invariant :P_start_1_4 + P_setx_3_4 + P_setbi_5_4 + P_ify0_4_4 + P_sety_9_4 + P_ifxi_10_4 + P_setbi_11_4 + P_fordo_12_4 + P_await_13_4 + P_ifyi_15_4 + P_awaity_4 + P_CS_21_4 + P_setbi_24_4 = 1
invariant :wait_27 + -1'P_await_13_4 + done_27 = 0
invariant :wait_21 + -1'P_await_13_3 + done_21 = 0
invariant :wait_33 + -1'P_await_13_5 + done_33 = 0
invariant :x_0 + x_1 + x_2 + x_3 + x_4 + x_5 = 1
invariant :wait_1 + -1'P_await_13_0 + done_1 = 0
invariant :P_start_1_2 + P_setx_3_2 + P_setbi_5_2 + P_ify0_4_2 + P_sety_9_2 + P_ifxi_10_2 + P_setbi_11_2 + P_fordo_12_2 + P_await_13_2 + P_ifyi_15_2 + P_awaity_2 + P_CS_21_2 + P_setbi_24_2 = 1
invariant :wait_17 + -1'P_await_13_2 + done_17 = 0
invariant :wait_18 + done_18 = 0
invariant :P_start_1_3 + P_setx_3_3 + P_setbi_5_3 + P_ify0_4_3 + P_sety_9_3 + P_ifxi_10_3 + P_setbi_11_3 + P_fordo_12_3 + P_await_13_3 + P_ifyi_15_3 + P_awaity_3 + P_CS_21_3 + P_setbi_24_3 = 1
invariant :b_4 + b_5 = 1
invariant :wait_0 + done_0 = 0
invariant :b_10 + b_11 = 1
invariant :wait_8 + -1'P_await_13_1 + done_8 = 0
invariant :wait_7 + -1'P_await_13_1 + done_7 = 0
invariant :P_start_1_0 + P_setx_3_0 + P_setbi_5_0 + P_ify0_4_0 + P_sety_9_0 + P_ifxi_10_0 + P_setbi_11_0 + P_fordo_12_0 + P_await_13_0 + P_ifyi_15_0 + P_awaity_0 + P_CS_21_0 + P_setbi_24_0 = 0
invariant :wait_3 + -1'P_await_13_0 + done_3 = 0
invariant :wait_28 + -1'P_await_13_4 + done_28 = 0
invariant :wait_34 + -1'P_await_13_5 + done_34 = 0
invariant :b_8 + b_9 = 1
invariant :wait_19 + -1'P_await_13_3 + done_19 = 0
invariant :wait_14 + -1'P_await_13_2 + done_14 = 0
invariant :wait_24 + done_24 = 0
invariant :wait_4 + -1'P_await_13_0 + done_4 = 0
invariant :wait_32 + -1'P_await_13_5 + done_32 = 0
invariant :wait_12 + done_12 = 0
invariant :b_6 + b_7 = 1
invariant :b_0 + b_1 = 0
invariant :wait_2 + -1'P_await_13_0 + done_2 = 0
invariant :wait_15 + -1'P_await_13_2 + done_15 = 0
Running compilation step : CommandLine [args=[gcc, -c, -I/home/mcc/BenchKit//lts_install_dir//include, -I., -std=c99, -fPIC, -O2, model.c], workingDir=/home/mcc/execution]
Compilation finished in 6137 ms.
Running link step : CommandLine [args=[gcc, -shared, -o, gal.so, model.o], workingDir=/home/mcc/execution]
Link finished in 60 ms.
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality00==true], workingDir=/home/mcc/execution]
LTSmin run took 7117 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-00 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality03==true], workingDir=/home/mcc/execution]
LTSmin run took 16321 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-03 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality04==true], workingDir=/home/mcc/execution]
LTSmin run took 726 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-04 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality05==true], workingDir=/home/mcc/execution]
LTSmin run took 612 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-05 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality06==true], workingDir=/home/mcc/execution]
LTSmin run took 1649 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-06 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality07==true], workingDir=/home/mcc/execution]
LTSmin run took 571 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-07 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality08==true], workingDir=/home/mcc/execution]
LTSmin run took 5627 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-08 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality09==true], workingDir=/home/mcc/execution]
LTSmin run took 2208 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-09 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality10==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality11==true], workingDir=/home/mcc/execution]
WARNING : LTSmin timed out (>225 s) on command CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality11==true], workingDir=/home/mcc/execution]
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality12==true], workingDir=/home/mcc/execution]
LTSmin run took 910 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-12 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality13==true], workingDir=/home/mcc/execution]
LTSmin run took 1094 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-13 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality14==true], workingDir=/home/mcc/execution]
LTSmin run took 670 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-14 TRUE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality15==true], workingDir=/home/mcc/execution]
LTSmin run took 4301 ms.
Found Violation
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-15 FALSE TECHNIQUES PARTIAL_ORDER EXPLICIT LTSMIN SAT_SMT
Retrying LTSmin with larger timeout 1800 s
Running LTSmin : CommandLine [args=[/home/mcc/BenchKit//lts_install_dir//bin/pins2lts-mc, ./gal.so, --threads=8, -p, --pins-guards, --when, -i, LamportFastMutExCOL5ReachabilityCardinality02==true], workingDir=/home/mcc/execution]
Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
petri,5.30682e+08,347.578,5168516,2,186052,5,1.69101e+07,6,0,993,1.19718e+07,0
Total reachable state count : 530682432

Verifying 16 reachability properties.
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-00 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-00,160,348.063,5168548,2,1920,6,1.69101e+07,7,0,1082,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-01 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-01,0,348.084,5168612,1,0,6,1.69101e+07,7,0,1082,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-02 does not hold.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-02 FALSE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN
No reachable states exhibit your property : LamportFastMutEx-COL-5-ReachabilityCardinality-02

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-02,0,348.206,5168612,1,0,6,1.69101e+07,8,0,1100,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-03 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-03,2,348.271,5168612,2,191,7,1.69101e+07,9,0,1144,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-04 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-04,86512,349.228,5168612,2,34271,8,1.69101e+07,10,0,3304,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-05 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-05,1,349.27,5168612,2,175,9,1.69101e+07,11,0,3401,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-06 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-06,1,349.276,5168612,2,175,10,1.69101e+07,12,0,3414,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-07 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-07,1,349.277,5168612,2,175,11,1.69101e+07,13,0,3423,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-08 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-08,329935,383.674,5168612,2,129331,12,1.69101e+07,14,0,121428,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-09 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-09,1,383.864,5168612,2,175,13,1.69101e+07,15,0,121442,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-10 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-10 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-10,0,383.925,5168612,1,0,13,1.69101e+07,16,0,121506,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-11 is true.
FORMULA LamportFastMutEx-COL-5-ReachabilityCardinality-11 TRUE TECHNIQUES DECISION_DIAGRAMS TOPOLOGICAL COLLATERAL_PROCESSING USE_NUPN

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-11,0,384.305,5168612,1,0,13,1.69101e+07,17,0,121668,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-12 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-12,1,384.343,5168612,2,175,14,1.69101e+07,18,0,121724,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-13 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-13,1,384.447,5168612,2,175,14,1.69101e+07,19,0,121846,1.19718e+07,0
Reachability property LamportFastMutEx-COL-5-ReachabilityCardinality-14 is true.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-14,1,384.471,5168612,2,175,14,1.69101e+07,20,0,121873,1.19718e+07,0
Invariant property LamportFastMutEx-COL-5-ReachabilityCardinality-15 does not hold.

Model ,|S| ,Time ,Mem(kb) ,fin. SDD ,fin. DDD ,peak SDD ,peak DDD ,SDD Hom ,SDD cache peak ,DDD Hom ,DDD cachepeak ,SHom cache
LamportFastMutEx-COL-5-ReachabilityCardinality-15,1,384.528,5168612,2,175,15,1.69101e+07,21,0,121895,1.19718e+07,0
WARNING : LTS min runner thread was asked to interrupt. Dying gracefully.

BK_STOP 1553640834577

--------------------
content from stderr:

+ export BINDIR=/home/mcc/BenchKit/
+ BINDIR=/home/mcc/BenchKit/
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ ReachabilityCardinality = StateSpace ]]
+ /home/mcc/BenchKit//runeclipse.sh /home/mcc/execution ReachabilityCardinality -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ /home/mcc/BenchKit//itstools/its-tools -data /home/mcc/execution/workspace -pnfolder /home/mcc/execution -examination ReachabilityCardinality -z3path /home/mcc/BenchKit//z3/bin/z3 -yices2path /home/mcc/BenchKit//yices/bin/yices -its -ltsminpath /home/mcc/BenchKit//lts_install_dir/ -greatspnpath /home/mcc/BenchKit//greatspn/ -order META -manyOrder -smt -vmargs -Dosgi.locking=none -Declipse.stateSaveDelayInterval=-1 -Dosgi.configuration.area=/tmp/.eclipse -Xss8m -Xms40m -Xmx8192m -Dfile.encoding=UTF-8 -Dosgi.requiredJavaVersion=1.6
Mar 26, 2019 10:39:04 PM fr.lip6.move.gal.application.Application start
INFO: Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -z3path, /home/mcc/BenchKit//z3/bin/z3, -yices2path, /home/mcc/BenchKit//yices/bin/yices, -its, -ltsminpath, /home/mcc/BenchKit//lts_install_dir/, -greatspnpath, /home/mcc/BenchKit//greatspn/, -order, META, -manyOrder, -smt]
Mar 26, 2019 10:39:04 PM fr.lip6.move.gal.application.MccTranslator transformPNML
INFO: Parsing pnml file : /home/mcc/execution/model.pnml
Mar 26, 2019 10:39:04 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Load time of PNML (colored model parsed with PNMLFW) : 940 ms
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 18 places.
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Computed order using colors.
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: sort/places :pid * pid->wait,done,
pid * bool->b,
pid->P-start_1,x,y,P-setx_3,P-setbi_5,P-ify0_4,P-sety_9,P-ifxi_10,P-setbi_11,P-fordo_12,P-await_13,P-ifyi_15,P-awaity,P-CS_21,P-setbi_24,

Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.pnml.togal.HLGALTransformer handlePage
INFO: Transformed 17 transitions.
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.pnml.togal.PnmlToGalTransformer transform
INFO: Computed order based on color domains.
Mar 26, 2019 10:39:05 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/model.pnml.img.gal : 8 ms
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $y of transition T_yeqi_15
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.instantiate.Instantiator fuseEqualParameters
INFO: Fused parameters : $i and $x of transition T_xeqi_10
Mar 26, 2019 10:39:05 PM fr.lip6.move.gal.instantiate.Instantiator instantiateParameters
INFO: On-the-fly reduction of False transitions avoided exploring 13.0 instantiations of transitions. Total transitions/syncs built is 317
Mar 26, 2019 10:39:06 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 151 ms
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 99 ms
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.instantiate.GALRewriter flatten
INFO: Flatten gal took : 103 ms
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 66 transitions. Expanding to a total of 383 deterministic transitions.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 66 transitions. Expanding to a total of 383 deterministic transitions.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 15 ms.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 11 ms.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Input system was not deterministic with 66 transitions. Expanding to a total of 383 deterministic transitions.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.semantics.DeterministicNextBuilder getDeterministicNext
INFO: Determinization took 3 ms.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.application.StructuralToGreatSPN handlePage
INFO: Transformed 174 places.
Mar 26, 2019 10:39:07 PM fr.lip6.move.gal.application.StructuralToGreatSPN handlePage
INFO: Transformed 318 transitions.
Mar 26, 2019 10:39:07 PM fr.lip6.move.serialization.SerializationUtil systemToFile
INFO: Time to serialize gal into /home/mcc/execution/ReachabilityCardinality.pnml.gal : 8 ms
Mar 26, 2019 10:39:07 PM fr.lip6.move.serialization.SerializationUtil serializePropertiesForITSTools
INFO: Time to serialize properties into /home/mcc/execution/ReachabilityCardinality.prop : 2 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver computeAndDeclareInvariants
INFO: Computed 50 place invariants in 203 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
INFO: Ran tautology test, simplified 1 / 16 in 1351 ms.
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=0 took 31 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=0 took 5 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=0 took 20 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=0 took 19 ms
Exception in thread "Thread-8" java.lang.NullPointerException
at fr.lip6.move.gal.semantics.DeterministicNextBuilder$1.visit(DeterministicNextBuilder.java:49)
at fr.lip6.move.gal.semantics.DeterministicNextBuilder$1.visit(DeterministicNextBuilder.java:1)
at fr.lip6.move.gal.semantics.Sequence.accept(Sequence.java:67)
at fr.lip6.move.gal.semantics.DeterministicNextBuilder$1.visit(DeterministicNextBuilder.java:40)
at fr.lip6.move.gal.semantics.DeterministicNextBuilder$1.visit(DeterministicNextBuilder.java:1)
at fr.lip6.move.gal.semantics.Alternative.accept(Alternative.java:71)
at fr.lip6.move.gal.semantics.DeterministicNextBuilder.getDeterministicNext(DeterministicNextBuilder.java:56)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.init(NextBMCSolver.java:83)
at fr.lip6.move.gal.gal2smt.bmc.KInductionSolver.init(KInductionSolver.java:59)
at fr.lip6.move.gal.gal2smt.smt.ISMTSolver.init(ISMTSolver.java:17)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runKInduction(Gal2SMTFrontEnd.java:278)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$1(Gal2SMTFrontEnd.java:274)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$2.run(Gal2SMTFrontEnd.java:166)
at java.lang.Thread.run(Thread.java:748)
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=0 took 33 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=0 took 8 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=0 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=0 took 13 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=0 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=0 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=0 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=0 took 4 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=0 took 2 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=0 took 8 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=0 took 7 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=1 took 18 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=1 took 8 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=1 took 9 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=1 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=1 took 9 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=1 took 17 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=1 took 13 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=1 took 25 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=1 took 7 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=1 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=1 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=1 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=1 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=1 took 10 ms
Mar 26, 2019 10:39:08 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=1 took 6 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=2 took 104 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=2 took 130 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=2 took 192 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=2 took 71 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=2 took 248 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.bmc.KInductionSolver init
INFO: Proved 174 variables to be positive in 1684 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may disable matrix : 318 transitions.
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of disable matrix completed :0/318 took 0 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=2 took 62 ms
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete disable matrix. took 56 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeAblingMatrix
INFO: Computing symmetric may enable matrix : 318 transitions.
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Complete enable matrix. took 16 ms. Total solver calls (SAT/UNSAT): 0(0/0)
Mar 26, 2019 10:39:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=2 took 245 ms
Mar 26, 2019 10:39:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=2 took 624 ms
Mar 26, 2019 10:39:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=2 took 154 ms
Mar 26, 2019 10:39:10 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=2 took 145 ms
Mar 26, 2019 10:39:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=2 took 109 ms
Mar 26, 2019 10:39:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=2 took 100 ms
Mar 26, 2019 10:39:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=2 took 73 ms
Mar 26, 2019 10:39:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=2 took 272 ms
Mar 26, 2019 10:39:11 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=2 took 146 ms
Mar 26, 2019 10:39:12 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=3 took 733 ms
Mar 26, 2019 10:39:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=3 took 2571 ms
Mar 26, 2019 10:39:18 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=3 took 3659 ms
Mar 26, 2019 10:39:22 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=3 took 3786 ms
Mar 26, 2019 10:39:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeCoEnablingMatrix
INFO: Computing symmetric co enabling matrix : 318 transitions.
Mar 26, 2019 10:39:24 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(0/318) took 43 ms. Total solver calls (SAT/UNSAT): 57(0/57)
Mar 26, 2019 10:39:27 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=3 took 4755 ms
Mar 26, 2019 10:39:27 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(35/318) took 3077 ms. Total solver calls (SAT/UNSAT): 3042(165/2877)
Mar 26, 2019 10:39:28 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=3 took 1289 ms
Mar 26, 2019 10:39:29 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=3 took 772 ms
Mar 26, 2019 10:39:31 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(60/318) took 6159 ms. Total solver calls (SAT/UNSAT): 6127(405/5722)
Mar 26, 2019 10:39:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=3 took 3711 ms
Mar 26, 2019 10:39:33 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=3 took 868 ms
Mar 26, 2019 10:39:34 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(92/318) took 9241 ms. Total solver calls (SAT/UNSAT): 9573(732/8841)
Mar 26, 2019 10:39:37 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(127/318) took 12300 ms. Total solver calls (SAT/UNSAT): 13668(1134/12534)
Mar 26, 2019 10:39:39 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=3 took 5444 ms
Mar 26, 2019 10:39:40 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(167/318) took 15483 ms. Total solver calls (SAT/UNSAT): 15948(1305/14643)
Mar 26, 2019 10:39:40 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=3 took 1463 ms
Mar 26, 2019 10:39:41 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=3 took 624 ms
Mar 26, 2019 10:39:43 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of co-enabling matrix(223/318) took 18486 ms. Total solver calls (SAT/UNSAT): 17268(1450/15818)
Mar 26, 2019 10:39:43 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=3 took 2622 ms
Mar 26, 2019 10:39:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Finished co-enabling matrix. took 21434 ms. Total solver calls (SAT/UNSAT): 20133(1725/18408)
Mar 26, 2019 10:39:46 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver computeDoNotAccord
INFO: Computing Do-Not-Accords matrix : 318 transitions.
Mar 26, 2019 10:39:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=3 took 5142 ms
Mar 26, 2019 10:39:49 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=3 took 762 ms
Mar 26, 2019 10:39:50 PM fr.lip6.move.gal.gal2smt.bmc.NecessaryEnablingsolver printStats
INFO: Computation of Completed DNA matrix. took 4146 ms. Total solver calls (SAT/UNSAT): 235(0/235)
Mar 26, 2019 10:39:50 PM fr.lip6.move.gal.gal2pins.Gal2PinsTransformerNext transform
INFO: Built C files in 43350ms conformant to PINS in folder :/home/mcc/execution
Mar 26, 2019 10:40:35 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-00(UNSAT) depth K=4 took 45764 ms
Mar 26, 2019 10:41:32 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-02(UNSAT) depth K=4 took 56475 ms
Mar 26, 2019 10:42:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-03(UNSAT) depth K=4 took 33882 ms
Mar 26, 2019 10:42:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-04(UNSAT) depth K=4 took 50806 ms
Mar 26, 2019 10:43:48 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-05(UNSAT) depth K=4 took 51466 ms
Mar 26, 2019 10:44:24 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-06(UNSAT) depth K=4 took 36181 ms
Mar 26, 2019 10:45:07 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-07(UNSAT) depth K=4 took 42841 ms
Mar 26, 2019 10:45:56 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-08(UNSAT) depth K=4 took 49203 ms
Mar 26, 2019 10:46:26 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-09(UNSAT) depth K=4 took 30248 ms
Mar 26, 2019 10:47:15 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-10(UNSAT) depth K=4 took 48335 ms
Mar 26, 2019 10:48:09 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-11(UNSAT) depth K=4 took 54562 ms
Mar 26, 2019 10:49:14 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-12(UNSAT) depth K=4 took 65296 ms
Mar 26, 2019 10:50:05 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-13(UNSAT) depth K=4 took 50609 ms
Mar 26, 2019 10:51:25 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-14(UNSAT) depth K=4 took 80008 ms
Mar 26, 2019 10:52:19 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solution for property LamportFastMutEx-COL-5-ReachabilityCardinality-15(UNSAT) depth K=4 took 53900 ms
Mar 26, 2019 10:53:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd checkProperties
WARNING: Interrupting SMT solver.
java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Mar 26, 2019 10:53:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
WARNING: Unexpected error occurred while running SMT. Was verifying LamportFastMutEx-COL-5-ReachabilityCardinality-10 SMT depth 5
java.lang.RuntimeException: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:404)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.access$0(Gal2SMTFrontEnd.java:350)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd$1.run(Gal2SMTFrontEnd.java:159)
at java.lang.Thread.run(Thread.java:748)
Caused by: java.lang.RuntimeException: SMT solver raised an exception or timeout :(error "Solver has unexpectedly terminated")
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.checkSat(NextBMCSolver.java:297)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verifyAssertion(NextBMCSolver.java:452)
at fr.lip6.move.gal.gal2smt.bmc.NextBMCSolver.verify(NextBMCSolver.java:435)
at fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd.runBMC(Gal2SMTFrontEnd.java:378)
... 3 more
Mar 26, 2019 10:53:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: During BMC, SMT solver timed out at depth 5
Mar 26, 2019 10:53:53 PM fr.lip6.move.gal.gal2smt.Gal2SMTFrontEnd runBMC
INFO: BMC solving timed out (3600000 secs) at depth 5
Mar 26, 2019 10:53:53 PM fr.lip6.move.gal.application.SMTRunner$2 run
INFO: SMT solved 1/ 16 properties. Interrupting other analysis methods.

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-5"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="itstoolsm"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-3957"
echo " Executing tool itstoolsm"
echo " Input is LamportFastMutEx-COL-5, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r196-smll-155246587200152"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-5.tgz
mv LamportFastMutEx-COL-5 execution
cd execution
if [ "ReachabilityCardinality" = "GlobalProperties" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;